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authorLionel Landwerlin <[email protected]>2020-01-15 15:14:23 +0200
committerLionel Landwerlin <[email protected]>2020-01-16 11:51:30 +0200
commit308efbf2f3504e787705968de02044916afdd265 (patch)
tree32d339385db38e50429c92a3bfe06a72398eb8d0 /src
parent9eca823cce84d7b055714ebda303f7e299a680d5 (diff)
anv: implement another workaround for non pipelined states
Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
Diffstat (limited to 'src')
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index fa3476095a5..79c10e1f757 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -56,6 +56,7 @@ void
genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_device *device = cmd_buffer->device;
+ UNUSED const struct gen_device_info *devinfo = &device->info;
uint32_t mocs = device->isl_dev.mocs.internal;
/* If we are emitting a new state base address we probably need to re-emit
@@ -77,6 +78,17 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
#endif
+#if GEN_GEN == 12
+ /* GEN:BUG:1606662791:
+ *
+ * Software must program PIPE_CONTROL command with "HDC Pipeline
+ * Flush" prior to programming of the below two non-pipeline state :
+ * * STATE_BASE_ADDRESS
+ * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
+ */
+ if (devinfo->revision == 0 /* A0 */)
+ pc.HDCPipelineFlushEnable = true;
+#endif
}
#if GEN_GEN == 12