radeonsi: add PKT3_CONTEXT_REG_RMW

Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>

2 files changed, 31 insertions, 0 deletions

diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 0b996e54884..387689876d1 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -181,6 +181,7 @@
 /* fix CP DMA before uncommenting: */
 /*#define PKT3_EVENT_WRITE_EOS                   0x48*/ /* not on GFX9 */
 #define PKT3_RELEASE_MEM                       0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */
+#define PKT3_CONTEXT_REG_RMW                   0x51 /* older firmware versions on older chips don't have this */
 #define PKT3_ONE_REG_WRITE                     0x57 /* not on CIK */
 #define PKT3_ACQUIRE_MEM                       0x58 /* new for CIK */
 #define PKT3_REWIND                            0x59 /* VI+ [any ring] or CIK [compute ring only] */
diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h
index 4e8890a5f97..0b0b64ca13c 100644
--- a/src/gallium/drivers/radeonsi/si_build_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_build_pm4.h
@@ -116,6 +116,36 @@ static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
 	radeon_emit(cs, value);
 }
 
+static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg,
+					      unsigned value, unsigned mask)
+{
+	assert(reg >= SI_CONTEXT_REG_OFFSET);
+	assert(cs->current.cdw + 4 <= cs->current.max_dw);
+	radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));
+	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
+	radeon_emit(cs, mask);
+	radeon_emit(cs, value);
+}
+
+/* Emit PKT3_CONTEXT_REG_RMW if the register value is different. */
+static inline void radeon_opt_set_context_reg_rmw(struct si_context *sctx, unsigned offset,
+						  enum si_tracked_reg reg, unsigned value,
+						  unsigned mask)
+{
+	struct radeon_cmdbuf *cs = sctx->gfx_cs;
+
+	assert((value & ~mask) == 0);
+	value &= mask;
+
+	if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
+	    sctx->tracked_regs.reg_value[reg] != value) {
+		radeon_set_context_reg_rmw(cs, offset, value, mask);
+
+		sctx->tracked_regs.reg_saved |= 0x1ull << reg;
+		sctx->tracked_regs.reg_value[reg] = value;
+	}
+}
+
 /* Emit PKT3_SET_CONTEXT_REG if the register value is different. */
 static inline void radeon_opt_set_context_reg(struct si_context *sctx, unsigned offset,
 					      enum si_tracked_reg reg, unsigned value)