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authorMarek Olšák <[email protected]>2013-12-17 03:11:30 +0100
committerMarek Olšák <[email protected]>2013-12-17 15:41:46 +0100
commit2b404a650493514896b345e70713c1c3bbe58a26 (patch)
treef669d90677268e8497c60e110d60ff1801f34631 /src
parent1a63f278f2d312937a6d429c2b39db5307fb46ab (diff)
radeonsi: improve HiZ precision for less and lequal depth functions
r600g needs this too. Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 8e0880419bc..c1107c66001 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1815,7 +1815,13 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
/* use htile only for first level */
if (rtex->htile_buffer && !level) {
z_info |= S_028040_TILE_SURFACE_ENABLE(1);
- /* Force off means no force, DB_SHADER_CONTROL decides */
+
+ /* This is optimal for the clear value of 1.0 and using
+ * the LESS and LEQUAL test functions. Set this to 0
+ * for the opposite case. This can only be changed when
+ * clearing. */
+ z_info |= S_028040_ZRANGE_PRECISION(1);
+
uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
db_htile_data_base = va >> 8;
db_htile_surface = S_028ABC_FULL_CACHE(1);