diff options
| author | Rob Clark <[email protected]> | 2020-03-06 08:46:43 -0800 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-03-27 22:41:36 +0000 |
| commit | 142f2d45516132dfe577815859179f661828c32b (patch) | |
| tree | 768473a05034c6b2b321d26db9c2d3466ea74705 /src | |
| parent | 3d0905582a3d75882e1fd3846a500934045aa622 (diff) | |
freedreno/ir3: convert debug bitfield to BITFIELD_BIT()
(Little more verbose than the kernel's BIT())
Signed-off-by: Rob Clark <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Diffstat (limited to 'src')
| -rw-r--r-- | src/freedreno/ir3/ir3_compiler.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h index 2824b3fe5f4..1a370ae2068 100644 --- a/src/freedreno/ir3/ir3_compiler.h +++ b/src/freedreno/ir3/ir3_compiler.h @@ -82,18 +82,18 @@ unsigned ir3_pointer_size(struct ir3_compiler *compiler) } enum ir3_shader_debug { - IR3_DBG_SHADER_VS = 0x001, - IR3_DBG_SHADER_TCS = 0x002, - IR3_DBG_SHADER_TES = 0x004, - IR3_DBG_SHADER_GS = 0x008, - IR3_DBG_SHADER_FS = 0x010, - IR3_DBG_SHADER_CS = 0x020, - IR3_DBG_DISASM = 0x040, - IR3_DBG_OPTMSGS = 0x080, - IR3_DBG_FORCES2EN = 0x100, - IR3_DBG_NOUBOOPT = 0x200, - IR3_DBG_SCHEDMSGS = 0x400, - IR3_DBG_NOFP16 = 0x800, + IR3_DBG_SHADER_VS = BITFIELD_BIT(0), + IR3_DBG_SHADER_TCS = BITFIELD_BIT(1), + IR3_DBG_SHADER_TES = BITFIELD_BIT(2), + IR3_DBG_SHADER_GS = BITFIELD_BIT(3), + IR3_DBG_SHADER_FS = BITFIELD_BIT(4), + IR3_DBG_SHADER_CS = BITFIELD_BIT(5), + IR3_DBG_DISASM = BITFIELD_BIT(6), + IR3_DBG_OPTMSGS = BITFIELD_BIT(7), + IR3_DBG_FORCES2EN = BITFIELD_BIT(8), + IR3_DBG_NOUBOOPT = BITFIELD_BIT(9), + IR3_DBG_SCHEDMSGS = BITFIELD_BIT(10), + IR3_DBG_NOFP16 = BITFIELD_BIT(11), }; extern enum ir3_shader_debug ir3_shader_debug; |