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authorFrancisco Jerez <[email protected]>2019-09-27 14:49:42 -0700
committerFrancisco Jerez <[email protected]>2019-10-11 12:24:16 -0700
commiteeaad2992cc45c22f5e188d0a814db795112964d (patch)
treec69df378eddd6df2f873eca6339face6a500cfb1 /src
parent152754665abb937a49e451331c88266ef5c3cdf1 (diff)
intel/ir: Represent physical edge of ELSE instruction.
This edge doesn't exist in the original scalar program, but it represents a potential control flow path the EU will take in cases where the condition isn't uniform across channels of the same SIMD thread. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/intel/compiler/brw_cfg.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_cfg.cpp b/src/intel/compiler/brw_cfg.cpp
index 70a7530e265..d5e0a08c74c 100644
--- a/src/intel/compiler/brw_cfg.cpp
+++ b/src/intel/compiler/brw_cfg.cpp
@@ -221,6 +221,7 @@ cfg_t::cfg_t(exec_list *instructions)
next = new_block();
assert(cur_if != NULL);
cur_if->add_successor(mem_ctx, next, bblock_link_logical);
+ cur_else->add_successor(mem_ctx, next, bblock_link_physical);
set_next_block(&cur, next, ip);
break;