i965: Port Gen6+ DEPTH_STENCIL state to genxml.

This emits 3DSTATE_WM_DEPTH_STENCIL on Gen8+ or DEPTH_STENCIL_STATE
(and the relevant pointer packets) on Gen6-7.5 from a single function.

v3:
   - Watch for BRW_NEW_BATCH too on gen < 8 (Ken)

Signed-off-by: Kenneth Graunke <[email protected]>
Signed-off-by: Rafael Antognolli <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>

5 files changed, 101 insertions, 238 deletions

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 41f4d839823..b0852513cd4 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -80,7 +80,6 @@ i965_FILES = \
 	gen6_clip_state.c \
 	gen6_constant_state.c \
 	gen6_depth_state.c \
-	gen6_depthstencil.c \
 	gen6_gs_state.c \
 	gen6_multisample_state.c \
 	gen6_queryobj.c \
@@ -119,7 +118,6 @@ i965_FILES = \
 	gen8_surface_state.c \
 	gen8_viewport_state.c \
 	gen8_vs_state.c \
-	gen8_wm_depth_stencil.c \
 	hsw_queryobj.c \
 	hsw_sol.c \
 	intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 64035702e47..7b6d7184186 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -112,7 +112,6 @@ extern const struct brw_tracked_state gen6_blend_state;
 extern const struct brw_tracked_state gen6_clip_state;
 extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_depth_stencil_state;
 extern const struct brw_tracked_state gen6_gs_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
@@ -157,7 +156,6 @@ extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
-extern const struct brw_tracked_state gen8_wm_depth_stencil;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_raster_state;
 extern const struct brw_tracked_state gen8_sbe_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
deleted file mode 100644
index 0f9626cd15a..00000000000
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <[email protected]>
- *
- */
-
-#include "intel_batchbuffer.h"
-#include "intel_fbo.h"
-#include "brw_context.h"
-#include "brw_defines.h"
-#include "brw_state.h"
-
-static void
-gen6_upload_depth_stencil_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = &brw->ctx;
-   struct gen6_depth_stencil_state *ds;
-   struct intel_renderbuffer *depth_irb;
-
-   /* _NEW_BUFFERS */
-   depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
-
-   ds = brw_state_batch(brw, sizeof(*ds), 64,
-			&brw->cc.depth_stencil_state_offset);
-   memset(ds, 0, sizeof(*ds));
-
-   /* _NEW_STENCIL | _NEW_BUFFERS */
-   if (ctx->Stencil._Enabled) {
-      int back = ctx->Stencil._BackFace;
-
-      ds->ds0.stencil_enable = 1;
-      ds->ds0.stencil_func =
-	 intel_translate_compare_func(ctx->Stencil.Function[0]);
-      ds->ds0.stencil_fail_op =
-	 intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
-      ds->ds0.stencil_pass_depth_fail_op =
-	 intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
-      ds->ds0.stencil_pass_depth_pass_op =
-	 intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
-      ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
-      ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0];
-
-      if (ctx->Stencil._TestTwoSide) {
-	 ds->ds0.bf_stencil_enable = 1;
-	 ds->ds0.bf_stencil_func =
-	    intel_translate_compare_func(ctx->Stencil.Function[back]);
-	 ds->ds0.bf_stencil_fail_op =
-	    intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
-	 ds->ds0.bf_stencil_pass_depth_fail_op =
-	    intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
-	 ds->ds0.bf_stencil_pass_depth_pass_op =
-	    intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
-	 ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
-	 ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
-      }
-
-      ds->ds0.stencil_write_enable = ctx->Stencil._WriteEnabled;
-   }
-
-   /* _NEW_DEPTH */
-   if (ctx->Depth.Test && depth_irb) {
-      ds->ds2.depth_test_enable = ctx->Depth.Test;
-      ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
-      ds->ds2.depth_write_enable = brw_depth_writes_enabled(brw);
-   }
-
-   /* Point the GPU at the new indirect state. */
-   if (brw->gen == 6) {
-      BEGIN_BATCH(4);
-      OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      BEGIN_BATCH(2);
-      OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
-      OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
-      ADVANCE_BATCH();
-   }
-}
-
-const struct brw_tracked_state gen6_depth_stencil_state = {
-   .dirty = {
-      .mesa = _NEW_BUFFERS |
-              _NEW_DEPTH |
-              _NEW_STENCIL,
-      .brw  = BRW_NEW_BATCH |
-              BRW_NEW_BLORP |
-              BRW_NEW_STATE_BASE_ADDRESS,
-   },
-   .emit = gen6_upload_depth_stencil_state,
-};
diff --git a/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c b/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
deleted file mode 100644
index 9a6c9e060bb..00000000000
--- a/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright © 2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "intel_batchbuffer.h"
-#include "intel_fbo.h"
-#include "brw_context.h"
-#include "brw_defines.h"
-#include "brw_state.h"
-#include "main/stencil.h"
-
-static void
-gen8_upload_wm_depth_stencil(struct brw_context *brw)
-{
-   struct gl_context *ctx = &brw->ctx;
-   uint32_t dw1 = 0, dw2 = 0, dw3 = 0;
-
-   /* _NEW_BUFFERS */
-   struct intel_renderbuffer *depth_irb =
-      intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
-
-   struct gl_stencil_attrib *stencil = &ctx->Stencil;
-
-   /* _NEW_STENCIL | _NEW_BUFFERS */
-   if (stencil->_Enabled) {
-      #define FUNC intel_translate_compare_func
-      #define OP intel_translate_stencil_op
-
-      dw1 |=
-         GEN8_WM_DS_STENCIL_TEST_ENABLE |
-         FUNC(stencil->Function[0]) << GEN8_WM_DS_STENCIL_FUNC_SHIFT |
-         OP(stencil->FailFunc[0])  << GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT |
-         OP(stencil->ZFailFunc[0]) << GEN8_WM_DS_Z_FAIL_OP_SHIFT |
-         OP(stencil->ZPassFunc[0]) << GEN8_WM_DS_Z_PASS_OP_SHIFT;
-
-      if (stencil->_WriteEnabled)
-         dw1 |= GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE;
-
-      dw2 |=
-         SET_FIELD(stencil->WriteMask[0] & 0xff, GEN8_WM_DS_STENCIL_WRITE_MASK) |
-         SET_FIELD(stencil->ValueMask[0] & 0xff, GEN8_WM_DS_STENCIL_TEST_MASK);
-
-      if (stencil->_TestTwoSide) {
-         const int b = stencil->_BackFace;
-
-         dw1 |=
-            GEN8_WM_DS_DOUBLE_SIDED_STENCIL_ENABLE |
-            FUNC(stencil->Function[b]) << GEN8_WM_DS_BF_STENCIL_FUNC_SHIFT |
-            OP(stencil->FailFunc[b]) << GEN8_WM_DS_BF_STENCIL_FAIL_OP_SHIFT |
-            OP(stencil->ZFailFunc[b]) << GEN8_WM_DS_BF_Z_FAIL_OP_SHIFT |
-            OP(stencil->ZPassFunc[b]) << GEN8_WM_DS_BF_Z_PASS_OP_SHIFT;
-
-         dw2 |= SET_FIELD(stencil->WriteMask[b] & 0xff,
-                          GEN8_WM_DS_BF_STENCIL_WRITE_MASK) |
-                SET_FIELD(stencil->ValueMask[b] & 0xff,
-                          GEN8_WM_DS_BF_STENCIL_TEST_MASK);
-      }
-
-      if (brw->gen >= 9) {
-         int stencil_ref  = _mesa_get_stencil_ref(ctx, 0);
-         int backface_ref = _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
-
-         dw3 = SET_FIELD(stencil_ref, GEN9_WM_DS_STENCIL_REF) |
-               SET_FIELD(backface_ref, GEN9_WM_DS_BF_STENCIL_REF);
-      }
-   }
-
-   /* _NEW_DEPTH */
-   if (ctx->Depth.Test && depth_irb) {
-      dw1 |=
-         GEN8_WM_DS_DEPTH_TEST_ENABLE |
-         FUNC(ctx->Depth.Func) << GEN8_WM_DS_DEPTH_FUNC_SHIFT;
-
-      if (brw_depth_writes_enabled(brw))
-         dw1 |= GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE;
-   }
-
-   int pkt_len = brw->gen >= 9 ? 4 : 3;
-
-   BEGIN_BATCH(pkt_len);
-   OUT_BATCH(_3DSTATE_WM_DEPTH_STENCIL << 16 | (pkt_len - 2));
-   OUT_BATCH(dw1);
-   OUT_BATCH(dw2);
-   if (pkt_len > 3) {
-      OUT_BATCH(dw3);
-   }
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen8_wm_depth_stencil = {
-   .dirty = {
-      .mesa = _NEW_BUFFERS |
-              _NEW_DEPTH |
-              _NEW_STENCIL,
-      .brw  = BRW_NEW_BLORP |
-              BRW_NEW_CONTEXT,
-   },
-   .emit = gen8_upload_wm_depth_stencil,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index b0487f9ccaf..49caf63262c 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -30,6 +30,9 @@
 #include "brw_state.h"
 
 #include "intel_batchbuffer.h"
+#include "intel_fbo.h"
+
+#include "main/stencil.h"
 
 UNUSED static void *
 emit_dwords(struct brw_context *brw, unsigned n)
@@ -108,9 +111,105 @@ __gen_combine_address(struct brw_context *brw, void *location,
 
 /* ---------------------------------------------------------------------- */
 
+#if GEN_GEN >= 6
 
 /* ---------------------------------------------------------------------- */
 
+static void
+genX(upload_depth_stencil_state)(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+
+   /* _NEW_BUFFERS */
+   struct intel_renderbuffer *depth_irb =
+      intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
+
+   /* _NEW_DEPTH */
+   struct gl_depthbuffer_attrib *depth = &ctx->Depth;
+
+   /* _NEW_STENCIL */
+   struct gl_stencil_attrib *stencil = &ctx->Stencil;
+   const int b = stencil->_BackFace;
+
+#if GEN_GEN >= 8
+   brw_batch_emit(brw, GENX(3DSTATE_WM_DEPTH_STENCIL), wmds) {
+#else
+   uint32_t ds_offset;
+   brw_state_emit(brw, GENX(DEPTH_STENCIL_STATE), 64, &ds_offset, wmds) {
+#endif
+      if (depth->Test && depth_irb) {
+         wmds.DepthTestEnable = true;
+         wmds.DepthBufferWriteEnable = brw_depth_writes_enabled(brw);
+         wmds.DepthTestFunction = intel_translate_compare_func(depth->Func);
+      }
+
+      if (stencil->_Enabled) {
+         wmds.StencilTestEnable = true;
+         wmds.StencilWriteMask = stencil->WriteMask[0] & 0xff;
+         wmds.StencilTestMask = stencil->ValueMask[0] & 0xff;
+
+         wmds.StencilTestFunction =
+            intel_translate_compare_func(stencil->Function[0]);
+         wmds.StencilFailOp =
+            intel_translate_stencil_op(stencil->FailFunc[0]);
+         wmds.StencilPassDepthPassOp =
+            intel_translate_stencil_op(stencil->ZPassFunc[0]);
+         wmds.StencilPassDepthFailOp =
+            intel_translate_stencil_op(stencil->ZFailFunc[0]);
+
+         wmds.StencilBufferWriteEnable = stencil->_WriteEnabled;
+
+         if (stencil->_TestTwoSide) {
+            wmds.DoubleSidedStencilEnable = true;
+            wmds.BackfaceStencilWriteMask = stencil->WriteMask[b] & 0xff;
+            wmds.BackfaceStencilTestMask = stencil->ValueMask[b] & 0xff;
+
+            wmds.BackfaceStencilTestFunction =
+               intel_translate_compare_func(stencil->Function[b]);
+            wmds.BackfaceStencilFailOp =
+               intel_translate_stencil_op(stencil->FailFunc[b]);
+            wmds.BackfaceStencilPassDepthPassOp =
+               intel_translate_stencil_op(stencil->ZPassFunc[b]);
+            wmds.BackfaceStencilPassDepthFailOp =
+               intel_translate_stencil_op(stencil->ZFailFunc[b]);
+         }
+
+#if GEN_GEN >= 9
+         wmds.StencilReferenceValue = _mesa_get_stencil_ref(ctx, 0);
+         wmds.BackfaceStencilReferenceValue = _mesa_get_stencil_ref(ctx, b);
+#endif
+      }
+   }
+
+#if GEN_GEN == 6
+   brw_batch_emit(brw, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
+      ptr.PointertoDEPTH_STENCIL_STATE = ds_offset;
+      ptr.DEPTH_STENCIL_STATEChange = true;
+   }
+#elif GEN_GEN == 7
+   brw_batch_emit(brw, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), ptr) {
+      ptr.PointertoDEPTH_STENCIL_STATE = ds_offset;
+   }
+#endif
+}
+
+static const struct brw_tracked_state genX(depth_stencil_state) = {
+   .dirty = {
+      .mesa = _NEW_BUFFERS |
+              _NEW_DEPTH |
+              _NEW_STENCIL,
+      .brw  = BRW_NEW_BLORP |
+              (GEN_GEN >= 8 ? BRW_NEW_CONTEXT
+                            : BRW_NEW_BATCH |
+                              BRW_NEW_STATE_BASE_ADDRESS),
+   },
+   .emit = genX(upload_depth_stencil_state),
+};
+
+/* ---------------------------------------------------------------------- */
+
+#endif
+
 void
 genX(init_atoms)(struct brw_context *brw)
 {
@@ -250,7 +349,7 @@ genX(init_atoms)(struct brw_context *brw)
       &gen7_urb,
       &gen6_blend_state,		/* must do before cc unit */
       &gen6_color_calc_state,	/* must do before cc unit */
-      &gen6_depth_stencil_state,	/* must do before cc unit */
+      &genX(depth_stencil_state),	/* must do before cc unit */
 
       &brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
       &brw_tcs_image_surfaces, /* Before tcs push/pull constants and binding table */
@@ -398,7 +497,7 @@ genX(init_atoms)(struct brw_context *brw)
       &gen8_ps_blend,
       &gen8_ps_extra,
       &gen8_ps_state,
-      &gen8_wm_depth_stencil,
+      &genX(depth_stencil_state),
       &gen8_wm_state,
 
       &gen6_scissor_state,