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authorAnuj Phogat <[email protected]>2018-05-31 15:41:53 -0700
committerAnuj Phogat <[email protected]>2018-07-09 15:38:42 -0700
commitc1d8300117891ec87762caa30d14307622c65bcf (patch)
treef3ee9eee84887d1c1dd17125f549b36df509679e /src
parent227dabc2664b886e621de03d9ba82073e2fd16aa (diff)
anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS
CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/intel/vulkan/genX_state.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 213b6061278..b1014d9e797 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -121,18 +121,6 @@ genX(init_device_state)(struct anv_device *device)
}
#endif
-#if GEN_GEN == 10 || GEN_GEN == 11
- uint32_t cache_mode_ss;
- anv_pack_struct(&cache_mode_ss, GENX(CACHE_MODE_SS),
- .FloatBlendOptimizationEnable = true,
- .FloatBlendOptimizationEnableMask = true);
-
- anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
- lri.RegisterOffset = GENX(CACHE_MODE_SS_num);
- lri.DataDWord = cache_mode_ss;
- }
-#endif
-
anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {