diff options
| author | Leo Liu <[email protected]> | 2017-02-09 10:16:06 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | 9d5db4e8f409baa4a32d4cd34d735877125684b4 (patch) | |
| tree | 09a8a92c0cc63afd5b76255973943b2cd72d433e /src | |
| parent | 474468fbf935fcd26704061054ccb4d1629009ed (diff) | |
radeon/uvd: add uvd soc15 register
Signed-off-by: Leo Liu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_uvd.c | 26 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_uvd.h | 5 |
2 files changed, 27 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index c1746f8325f..7c6ea9324ca 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -91,6 +91,12 @@ struct ruvd_decoder { bool use_legacy; struct rvid_buffer ctx; struct rvid_buffer sessionctx; + struct { + unsigned data0; + unsigned data1; + unsigned cmd; + unsigned cntl; + } reg; }; /* flush IB to the hardware */ @@ -120,14 +126,14 @@ static void send_cmd(struct ruvd_decoder *dec, unsigned cmd, uint64_t addr; addr = dec->ws->buffer_get_virtual_address(buf); addr = addr + off; - set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr); - set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32); + set_reg(dec, dec->reg.data0, addr); + set_reg(dec, dec->reg.data1, addr >> 32); } else { off += dec->ws->buffer_get_reloc_offset(buf); set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off); set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4); } - set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1); + set_reg(dec, dec->reg.cmd, cmd << 1); } /* do the codec needs an IT buffer ?*/ @@ -1150,7 +1156,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder, if (have_it(dec)) send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf, FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT); - set_reg(dec, RUVD_ENGINE_CNTL, 1); + set_reg(dec, dec->reg.cntl, 1); flush(dec, RADEON_FLUSH_ASYNC); next_buffer(dec); @@ -1284,6 +1290,18 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context, rvid_clear_buffer(context, &dec->sessionctx); } + if (info.family >= CHIP_VEGA10) { + dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0_SOC15; + dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1_SOC15; + dec->reg.cmd = RUVD_GPCOM_VCPU_CMD_SOC15; + dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15; + } else { + dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0; + dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1; + dec->reg.cmd = RUVD_GPCOM_VCPU_CMD; + dec->reg.cntl = RUVD_ENGINE_CNTL; + } + map_msg_fb_it_buf(dec); dec->msg->size = sizeof(*dec->msg); dec->msg->msg_type = RUVD_MSG_CREATE; diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h index e3f8504d843..a5af9eaafad 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.h +++ b/src/gallium/drivers/radeon/radeon_uvd.h @@ -56,6 +56,11 @@ #define RUVD_GPCOM_VCPU_DATA1 0xEF14 #define RUVD_ENGINE_CNTL 0xEF18 +#define RUVD_GPCOM_VCPU_CMD_SOC15 0x2070c +#define RUVD_GPCOM_VCPU_DATA0_SOC15 0x20710 +#define RUVD_GPCOM_VCPU_DATA1_SOC15 0x20714 +#define RUVD_ENGINE_CNTL_SOC15 0x20718 + /* UVD commands to VCPU */ #define RUVD_CMD_MSG_BUFFER 0x00000000 #define RUVD_CMD_DPB_BUFFER 0x00000001 |