diff options
| author | Marek Olšák <[email protected]> | 2016-06-28 13:15:45 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-06-29 16:34:22 +0200 |
| commit | 9a71bf88582164413a021a2fc26c894512bd52af (patch) | |
| tree | e8a0529f94aecd3129146a61f76abd8f69e3f305 /src | |
| parent | 4b11ef23b4c064a6db5fae313b4e2e6bf027c7e1 (diff) | |
radeonsi: enable CU0 in each SE for LS-HS execution
Offchip-only tessellation allows this.
Reviewed-by: Edward O'Callaghan <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index b21fa5ca7ab..54febce4226 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3829,6 +3829,7 @@ static void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); if (sctx->b.chip_class >= CIK) { + si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff)); si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0); si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff)); si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff)); @@ -3841,7 +3842,6 @@ static void si_init_config(struct si_context *sctx) * * LATE_ALLOC_VS = 2 is the highest safe number. */ - si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff)); si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff)); si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2)); } else { @@ -3850,7 +3850,6 @@ static void si_init_config(struct si_context *sctx) * - VS can't execute on CU0. * - If HS writes outputs to LDS, LS can't execute on CU0. */ - si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe)); si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe)); si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31)); } |