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authorRob Clark <[email protected]>2019-05-31 07:07:57 -0700
committerRob Clark <[email protected]>2019-05-31 12:58:33 -0700
commit8eaa2d502131bdce874603f522eabc4a5719f2e6 (patch)
tree1d2adcebd79f48f13b09f4c050c84633f2fd9014 /src
parentf9fa456e1d09f1a6b2dccde056b3754f3f198ba7 (diff)
freedreno/a6xx: fix GPU crash on small render targets
Fixes dEQP-GLES2.functional.multisampled_render_to_texture.readpixels Signed-off-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_gmem.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index a00e4446333..6ad0bc68ef4 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -640,6 +640,13 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
+ /* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for
+ * small render targets. But since we align pitch to binw I think
+ * we can get away avoiding GPU hangs a simpler way, by just rounding
+ * up the blit scissor:
+ */
+ blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw);
+
OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
OUT_RING(ring,
A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |