diff options
author | Eric Anholt <eric@anholt.net> | 2013-10-08 00:20:04 -0700 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2013-10-09 11:28:19 -0700 |
commit | 791550aa8e70dd5e0bdd5a996ef66b5964cf9095 (patch) | |
tree | e567481bcd407807617c5ce204010ffd9ec86314 /src | |
parent | e6fb7441415ba641dd712f561a322fd85c662cb3 (diff) |
i965: Don't forget the cube map padding on gen5+.
We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd
experimentally found to be necessary!), but while the spec still requires
it on gen5, we'd been missing it in the array-layout cubemaps.
Cc: "9.1 9.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index e4e66b4219c..e9128a38244 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -197,6 +197,18 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt) } static void +align_cube(struct intel_mipmap_tree *mt) +{ + /* The 965's sampler lays cachelines out according to how accesses + * in the texture surfaces run, so they may be "vertical" through + * memory. As a result, the docs say in Surface Padding Requirements: + * Sampling Engine Surfaces that two extra rows of padding are required. + */ + if (mt->target == GL_TEXTURE_CUBE_MAP) + mt->total_height += 2; +} + +static void brw_miptree_layout_texture_array(struct brw_context *brw, struct intel_mipmap_tree *mt) { @@ -220,6 +232,8 @@ brw_miptree_layout_texture_array(struct brw_context *brw, } } mt->total_height = qpitch * mt->physical_depth0; + + align_cube(mt); } static void @@ -291,13 +305,7 @@ brw_miptree_layout_texture_3d(struct brw_context *brw, } } - /* The 965's sampler lays cachelines out according to how accesses - * in the texture surfaces run, so they may be "vertical" through - * memory. As a result, the docs say in Surface Padding Requirements: - * Sampling Engine Surfaces that two extra rows of padding are required. - */ - if (mt->target == GL_TEXTURE_CUBE_MAP) - mt->total_height += 2; + align_cube(mt); } void |