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authorJason Ekstrand <[email protected]>2016-04-05 14:06:10 -0700
committerJason Ekstrand <[email protected]>2016-04-15 14:04:37 -0700
commit75b68f9114dc3ba1b501fb7de8198c03b3dcb1fd (patch)
tree544c063ae3711cc50ca9ab8f9fd86892da67de88 /src
parent4a80890177015fef792ac2e069452fe340f36769 (diff)
i965/vec4: Move can_do_writemask to vec4_instruction
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_ir_vec4.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4.cpp28
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp31
3 files changed, 30 insertions, 30 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 2b6872e6d31..81b6a139f44 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -172,6 +172,7 @@ public:
int swizzle, int swizzle_mask);
void reswizzle(int dst_writemask, int swizzle);
bool can_do_source_mods(const struct brw_device_info *devinfo);
+ bool can_do_writemask(const struct brw_device_info *devinfo);
bool can_change_types() const;
bool has_source_and_destination_hazard() const;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 00253438c44..4d0efa8fbfd 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -239,6 +239,34 @@ vec4_instruction::can_do_source_mods(const struct brw_device_info *devinfo)
}
bool
+vec4_instruction::can_do_writemask(const struct brw_device_info *devinfo)
+{
+ switch (opcode) {
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
+ case VS_OPCODE_PULL_CONSTANT_LOAD:
+ case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
+ case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
+ case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
+ case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
+ case TES_OPCODE_CREATE_INPUT_READ_HEADER:
+ case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
+ case VEC4_OPCODE_URB_READ:
+ return false;
+ default:
+ /* The MATH instruction on Gen6 only executes in align1 mode, which does
+ * not support writemasking.
+ */
+ if (devinfo->gen == 6 && is_math())
+ return false;
+
+ if (is_tex())
+ return false;
+
+ return true;
+ }
+}
+
+bool
vec4_instruction::can_change_types() const
{
return dst.type == src[0].type &&
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
index 166bc17e1e1..c643212494b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
@@ -36,35 +36,6 @@
using namespace brw;
-static bool
-can_do_writemask(const struct brw_device_info *devinfo,
- const vec4_instruction *inst)
-{
- switch (inst->opcode) {
- case SHADER_OPCODE_GEN4_SCRATCH_READ:
- case VS_OPCODE_PULL_CONSTANT_LOAD:
- case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
- case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
- case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
- case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
- case TES_OPCODE_CREATE_INPUT_READ_HEADER:
- case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
- case VEC4_OPCODE_URB_READ:
- return false;
- default:
- /* The MATH instruction on Gen6 only executes in align1 mode, which does
- * not support writemasking.
- */
- if (devinfo->gen == 6 && inst->is_math())
- return false;
-
- if (inst->is_tex())
- return false;
-
- return true;
- }
-}
-
bool
vec4_visitor::dead_code_eliminate()
{
@@ -101,7 +72,7 @@ vec4_visitor::dead_code_eliminate()
/* If the instruction can't do writemasking, then it's all or
* nothing.
*/
- if (!can_do_writemask(devinfo, inst)) {
+ if (!inst->can_do_writemask(devinfo)) {
bool result = result_live[0] | result_live[1] |
result_live[2] | result_live[3];
result_live[0] = result;