i965/blorp: store x and y offsets in brw_blorp_mip_info.

Currently, gen{6,7}_blorp_emit_surface_state assumes that the src and
dst surfaces are mapped to miplevel 0 and layer 0 (thus no surface
offset is required).  This is a bug, since the user might try to blit
to and from levels/layers other than 0.

To fix this bug, it will not be sufficient to have
gen6_{6,7}_blorp_emit_surface_state look up the surface offset at the
time they set up the surface state, since these offsets will need to
be tweaked when blitting stencil buffers (due to the fact that stencil
buffer blits have to swizzle between W and Y tiling formats).

So, to pave the way for the bug fix, this patch causes the x and y
offsets to be computed during blit setup and stored in
brw_blorp_mip_info.

As a result of this change, brw_blorp_mip_info doesn't need to store
the level and layer anymore.

For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.

Reviewed-by: Eric Anholt <[email protected]>
(cherry picked from commit c130ce7b2b26b4b67d4bf2b6dd1044a200efe25d)

4 files changed, 31 insertions, 28 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 7322a046112..6acc59187d4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -30,10 +30,10 @@
 
 brw_blorp_mip_info::brw_blorp_mip_info()
    : mt(NULL),
-     level(0),
-     layer(0),
      width(0),
-     height(0)
+     height(0),
+     x_offset(0),
+     y_offset(0)
 {
 }
 
@@ -50,10 +50,17 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
    intel_miptree_check_level_layer(mt, level, layer);
 
    this->mt = mt;
-   this->level = level;
-   this->layer = layer;
    this->width = mt->level[level].width;
    this->height = mt->level[level].height;
+
+   /* Construct a dummy renderbuffer just to extract tile offsets. */
+   struct intel_renderbuffer rb;
+   rb.mt = mt;
+   rb.mt_level = level;
+   rb.mt_layer = layer;
+   intel_renderbuffer_set_draw_offset(&rb);
+   x_offset = rb.draw_x;
+   y_offset = rb.draw_y;
 }
 
 void
@@ -107,19 +114,6 @@ brw_blorp_surface_info::set(struct brw_context *brw,
    }
 }
 
-void
-brw_blorp_mip_info::get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const
-{
-   /* Construct a dummy renderbuffer just to extract tile offsets. */
-   struct intel_renderbuffer rb;
-   rb.mt = mt;
-   rb.mt_level = level;
-   rb.mt_layer = layer;
-   intel_renderbuffer_set_draw_offset(&rb);
-   *draw_x = rb.draw_x;
-   *draw_y = rb.draw_y;
-}
-
 brw_blorp_params::brw_blorp_params()
    : x0(0),
      y0(0),
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index a19d2833baa..d6239b48e58 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -63,11 +63,8 @@ public:
 
    void set(struct intel_mipmap_tree *mt,
             unsigned int level, unsigned int layer);
-   void get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const;
 
    struct intel_mipmap_tree *mt;
-   unsigned int level;
-   unsigned int layer;
 
    /**
     * Width of the miplevel to be used.  For surfaces using
@@ -80,6 +77,20 @@ public:
     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
     */
    uint32_t height;
+
+   /**
+    * X offset within the surface to texture from (or render to).  For
+    * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
+    * pixels.
+    */
+   uint32_t x_offset;
+
+   /**
+    * Y offset within the surface to texture from (or render to).  For
+    * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
+    * pixels.
+    */
+   uint32_t y_offset;
 };
 
 class brw_blorp_surface_info : public brw_blorp_mip_info
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 14e85632b9e..d5d65c635f2 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -823,11 +823,11 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
                                      const brw_blorp_params *params)
 {
    struct intel_context *intel = &brw->intel;
-   uint32_t draw_x, draw_y;
+   uint32_t draw_x = params->depth.x_offset;
+   uint32_t draw_y = params->depth.y_offset;
    uint32_t tile_mask_x, tile_mask_y;
 
    gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
-   params->depth.get_draw_offsets(&draw_x, &draw_y);
 
    /* 3DSTATE_DEPTH_BUFFER */
    {
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index ae78fa665f6..3520ff60265 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -568,13 +568,11 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
                                      const brw_blorp_params *params)
 {
    struct intel_context *intel = &brw->intel;
-   uint32_t draw_x, draw_y;
+   uint32_t draw_x = params->depth.x_offset;
+   uint32_t draw_y = params->depth.y_offset;
    uint32_t tile_mask_x, tile_mask_y;
 
-   if (params->depth.mt) {
-      params->depth.get_draw_offsets(&draw_x, &draw_y);
-      gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
-   }
+   gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
 
    /* 3DSTATE_DEPTH_BUFFER */
    {