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authorMarek Olšák <[email protected]>2016-06-24 00:03:26 +0200
committerMarek Olšák <[email protected]>2016-06-24 16:24:53 +0200
commit0d638f4b3d2ff9c5a00828bd3d6743d1a70cf8be (patch)
tree24efed7f587b7f208fe5e9f7e30995d66c7262a5 /src
parent8f3ef4e8b800ba7d14cd10250382a01f0bb829b0 (diff)
radeonsi: set some VGT context registers on SI-CI
the kernel sets them, but other UMDs can change them Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index d12c89b9401..7e09c8da1a5 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3883,6 +3883,9 @@ static void si_init_config(struct si_context *sctx)
vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
+ } else {
+ si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
+ si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
}
if (sctx->b.family == CHIP_STONEY)