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authorPierre-Eric Pelloux-Prayer <[email protected]>2019-06-21 10:02:49 +0200
committerJuan A. Suarez Romero <[email protected]>2019-07-01 09:53:20 +0200
commitac3c9a4195bbca215af236628a011501ac3eba8f (patch)
tree2551a69598c8af16a16556ac1b83c11b2d9af208 /src
parent22b21623f3136951be120c1a48499868d4550001 (diff)
radeon/uvd: fix calc_ctx_size_h265_main10
Left shift was applied twice. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110702 Reviewed-by: Leo Liu <[email protected]> Tested-by: <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Cc: <[email protected]> (cherry picked from commit c81c784a4a05f8a957a649d73c8194247de47b56)
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/r600/radeon_uvd.c6
-rw-r--r--src/gallium/drivers/radeon/radeon_uvd.c6
-rw-r--r--src/gallium/drivers/radeon/radeon_vcn_dec.c6
3 files changed, 9 insertions, 9 deletions
diff --git a/src/gallium/drivers/r600/radeon_uvd.c b/src/gallium/drivers/r600/radeon_uvd.c
index 5568f2138e4..0f5bcc53212 100644
--- a/src/gallium/drivers/r600/radeon_uvd.c
+++ b/src/gallium/drivers/r600/radeon_uvd.c
@@ -247,7 +247,7 @@ static unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec, struct pipe_h265_picture_desc *pic)
{
- unsigned block_size, log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
+ unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
@@ -262,8 +262,8 @@ static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec, struct pipe_
else
max_references = MAX2(max_references, 17);
- block_size = (1 << (pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3));
- log2_ctb_size = block_size + pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
+ log2_ctb_size = pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3 +
+ pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
index ca066e89823..95e8007cae2 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -298,7 +298,7 @@ static unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec, struct pipe_h265_picture_desc *pic)
{
- unsigned block_size, log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
+ unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
@@ -313,8 +313,8 @@ static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec, struct pipe_
else
max_references = MAX2(max_references, 17);
- block_size = (1 << (pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3));
- log2_ctb_size = block_size + pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
+ log2_ctb_size = pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3 +
+ pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 688cef90103..b1d6edba466 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -552,7 +552,7 @@ static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec)
static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec, struct pipe_h265_picture_desc *pic)
{
- unsigned block_size, log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
+ unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
@@ -568,8 +568,8 @@ static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec, struct pip
else
max_references = MAX2(max_references, 17);
- block_size = (1 << (pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3));
- log2_ctb_size = block_size + pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
+ log2_ctb_size = pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3 +
+ pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;