Merge branch 'mesa_7_5_branch' into mesa_7_6_branch

Conflicts:

	Makefile
	configs/default
	progs/glsl/Makefile
	src/gallium/auxiliary/util/u_simple_shaders.c
	src/gallium/state_trackers/glx/xlib/xm_api.c
	src/mesa/drivers/dri/i965/brw_draw_upload.c
	src/mesa/drivers/dri/i965/brw_vs_emit.c
	src/mesa/drivers/dri/intel/intel_context.h
	src/mesa/drivers/dri/intel/intel_pixel.c
	src/mesa/drivers/dri/intel/intel_pixel_read.c
	src/mesa/main/texenvprogram.c
	src/mesa/main/version.h

6 files changed, 24 insertions, 3 deletions

diff --git a/src/gallium/auxiliary/util/u_simple_shaders.c b/src/gallium/auxiliary/util/u_simple_shaders.c
index 1b8da9b6853..ab754296fa8 100644
--- a/src/gallium/auxiliary/util/u_simple_shaders.c
+++ b/src/gallium/auxiliary/util/u_simple_shaders.c
@@ -131,8 +131,6 @@ util_make_fragment_tex_shader(struct pipe_context *pipe )
 
 
 
-
-
 /**
  * Make simple fragment color pass-through shader.
  */
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 26a64d65280..a5209ac41be 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -390,6 +390,8 @@ struct brw_cached_batch_item {
 struct brw_vertex_element {
    const struct gl_client_array *glarray;
 
+   /** The corresponding Mesa vertex attribute */
+   gl_vert_attrib attrib;
    /** Size of a complete element */
    GLuint element_size;
    /** Number of uploaded elements for this input. */
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 682094ff139..c53bd47bb57 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -187,6 +187,7 @@ static void brw_merge_inputs( struct brw_context *brw,
 
    for (i = 0; i < VERT_ATTRIB_MAX; i++) {
       brw->vb.inputs[i].glarray = arrays[i];
+      brw->vb.inputs[i].attrib = (gl_vert_attrib) i;
 
       if (arrays[i]->StrideB != 0)
 	 brw->vb.info.sizes[i/16] |= (brw->vb.inputs[i].glarray->Size - 1) <<
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index d49fb0fd951..4aa17fa02d7 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -423,7 +423,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
 	 /* Queue the buffer object up to be uploaded in the next pass,
 	  * when we've decided if we're doing interleaved or not.
 	  */
-	 if (i == 0) {
+	 if (input->attrib == VERT_ATTRIB_POS) {
 	    /* Position array not properly enabled:
 	     */
             if (input->glarray->StrideB == 0) {
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c
index 8713463ace2..30b06f281e9 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@ -261,6 +261,7 @@ do_blit_readpixels(GLcontext * ctx,
          if (!intel_intersect_cliprects(&rect, &src_rect, &box[i]))
             continue;
 
+<<<<<<< HEAD:src/mesa/drivers/dri/intel/intel_pixel_read.c
          if (!intelEmitCopyBlit(intel,
 				src->cpp,
 				src->pitch, src->buffer, 0, src->tiling,
@@ -274,6 +275,18 @@ do_blit_readpixels(GLcontext * ctx,
 	    UNLOCK_HARDWARE(intel);
 	    return GL_FALSE;
 	 }
+=======
+         intelEmitCopyBlit(intel,
+                           src->cpp,
+                           src->pitch, src->buffer, 0, src->tiling,
+                           rowLength, dst_buffer, dst_offset, GL_FALSE,
+                           rect.x1,
+                           rect.y1,
+                           rect.x1 - src_rect.x1,
+                           rect.y2 - src_rect.y2,
+                           rect.x2 - rect.x1, rect.y2 - rect.y1,
+			   GL_COPY);
+>>>>>>> mesa_7_5_branch:src/mesa/drivers/dri/intel/intel_pixel_read.c
       }
    }
    UNLOCK_HARDWARE(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 068a3f33797..a86c66a8443 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -196,6 +196,13 @@ intel_region_alloc(struct intel_context *intel,
    else
       height = ALIGN(height, 2);
 
+   /* If we're untiled, we have to align to 2 rows high because the
+    * data port accesses 2x2 blocks even if the bottom row isn't to be
+    * rendered, so failure to align means we could walk off the end of the
+    * GTT and fault.
+    */
+   height = ALIGN(height, 2);
+
    if (expect_accelerated_upload) {
       buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
 					     pitch * cpp * height, 64);