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authorKristian Høgsberg <krh@bitplanet.net>2014-11-13 16:28:08 -0800
committerKenneth Graunke <kenneth@whitecape.org>2014-11-14 19:38:03 -0800
commitf2bb655ac75d04dc033546479aabbbf4112cc54e (patch)
treef9c05b55e1b4d2eb937c95fa47b90836311c6c47 /src
parent13849f327cb3e6aa34a8a91fbbc7d68fd010d7ec (diff)
i965: Refactor fs_generator API
We split out SIMD8 and SIMD16 generation into seperate calls to new method generate_code(), which returns the start offset for the generated code. A new get_assembly() method returns the generated code. This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data in the generator. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp4
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp9
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h6
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_generator.cpp43
4 files changed, 23 insertions, 39 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index 3afe0e71519..7802c9f5021 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -45,7 +45,9 @@ const unsigned *
brw_blorp_eu_emitter::get_program(unsigned *program_size)
{
cfg_t cfg(&insts);
- return generator.generate_assembly(NULL, &cfg, program_size);
+ generator.generate_code(&cfg, 16);
+
+ return generator.get_assembly(program_size);
}
/**
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 39c6231b5c1..1289a400f36 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3729,11 +3729,12 @@ brw_wm_fs_emit(struct brw_context *brw,
prog_data->no_8 = false;
}
- const unsigned *assembly = NULL;
fs_generator g(brw, mem_ctx, key, prog_data, prog, fp,
v.runtime_check_aads_emit, INTEL_DEBUG & DEBUG_WM);
- assembly = g.generate_assembly(simd8_cfg, simd16_cfg,
- final_assembly_size);
+ if (simd8_cfg)
+ g.generate_code(simd8_cfg, 8);
+ if (simd16_cfg)
+ prog_data->prog_offset_16 = g.generate_code(simd16_cfg, 16);
if (unlikely(brw->perf_debug) && shader) {
if (shader->compiled_once)
@@ -3746,7 +3747,7 @@ brw_wm_fs_emit(struct brw_context *brw,
}
}
- return assembly;
+ return g.get_assembly(final_assembly_size);
}
bool
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index d9150c31053..8a8b72158bd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -697,12 +697,10 @@ public:
bool debug_flag);
~fs_generator();
- const unsigned *generate_assembly(const cfg_t *simd8_cfg,
- const cfg_t *simd16_cfg,
- unsigned *assembly_size);
+ int generate_code(const cfg_t *cfg, int dispatch_width);
+ const unsigned *get_assembly(unsigned int *assembly_size);
private:
- void generate_code(const cfg_t *cfg);
void fire_fb_write(fs_inst *inst,
struct brw_reg payload,
struct brw_reg implied_header,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index c95beb6bc06..0622b0740c9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1512,9 +1512,17 @@ fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
brw_mark_surface_used(prog_data, surf_index.dw1.ud);
}
-void
-fs_generator::generate_code(const cfg_t *cfg)
+int
+fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
{
+ /* align to 64 byte boundary. */
+ while (p->next_insn_offset % 64)
+ brw_NOP(p);
+
+ this->dispatch_width = dispatch_width;
+ if (dispatch_width == 16)
+ brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+
int start_offset = p->next_insn_offset;
int loop_count = 0;
@@ -2024,37 +2032,12 @@ fs_generator::generate_code(const cfg_t *cfg)
dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
ralloc_free(annotation.ann);
}
+
+ return start_offset;
}
const unsigned *
-fs_generator::generate_assembly(const cfg_t *simd8_cfg,
- const cfg_t *simd16_cfg,
- unsigned *assembly_size)
+fs_generator::get_assembly(unsigned int *assembly_size)
{
- assert(simd8_cfg || simd16_cfg);
-
- if (simd8_cfg) {
- dispatch_width = 8;
- generate_code(simd8_cfg);
- }
-
- if (simd16_cfg) {
- /* align to 64 byte boundary. */
- while (p->next_insn_offset % 64) {
- brw_NOP(p);
- }
-
- assert(stage == MESA_SHADER_FRAGMENT);
- brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
-
- /* Save off the start of this SIMD16 program */
- prog_data->prog_offset_16 = p->next_insn_offset;
-
- brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
-
- dispatch_width = 16;
- generate_code(simd16_cfg);
- }
-
return brw_get_program(p, assembly_size);
}