diff options
| author | Rafael Antognolli <[email protected]> | 2017-11-08 11:39:52 -0800 |
|---|---|---|
| committer | Rafael Antognolli <[email protected]> | 2017-12-01 11:27:27 -0800 |
| commit | e20830db96f744f326a995541da1fcafaa3f96ff (patch) | |
| tree | 61ed792799c1a93aa3041156645d3b477b9fbe5b /src | |
| parent | 2919adffe9f8ac4ea9e152db45c410cdc4514b7d (diff) | |
i965/gen10: Change the order of PIPE_CONTROL and load register.
I believe the workaround describes that the MI_LOAD_REGISTER_IMM should
come right after the 3DSTATE_SAMPLE_PATTERN.
This fixes GPU hangs in the i965 initial state batchbuffer when running
some Piglit tests with always_flush_batch=true.
Signed-off-by: Rafael Antognolli <[email protected]>
Cc: Kenneth Graunke <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_multisample_state.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c b/src/mesa/drivers/dri/i965/gen8_multisample_state.c index 9f849d64bbc..904e0fee2e5 100644 --- a/src/mesa/drivers/dri/i965/gen8_multisample_state.c +++ b/src/mesa/drivers/dri/i965/gen8_multisample_state.c @@ -57,15 +57,15 @@ gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context *brw) const struct gen_device_info *devinfo = &brw->screen->devinfo; assert(devinfo->gen == 10); + /* Write to CACHE_MODE_0 (0x7000) */ + brw_load_register_imm32(brw, GEN7_CACHE_MODE_0, 0); + /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must * be idle; i.e., full flush is required. */ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CACHE_INVALIDATE_BITS); - - /* Write to CACHE_MODE_0 (0x7000) */ - brw_load_register_imm32(brw, GEN7_CACHE_MODE_0, 0); } /** |