diff options
| author | Marek Olšák <[email protected]> | 2013-08-14 01:04:39 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2013-08-31 01:34:30 +0200 |
| commit | a81c3e00fee0626e63b1fb8ebb4c2cef3fb23367 (patch) | |
| tree | 663b943d05880c68b9d7f9d6d5ef26bdd7a5aed9 /src | |
| parent | d5b23dfc1c07f98afe749053b9cb4b69829fe3d4 (diff) | |
radeonsi: use r600_common_context, r600_common_screen, r600_resource
Also r600_hw_context_priv.h and si_state_streamout.c are removed, because
they are no longer needed.
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Christian König <[email protected]>
Tested-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src')
28 files changed, 338 insertions, 777 deletions
diff --git a/src/gallium/drivers/radeon/r600_cs.h b/src/gallium/drivers/radeon/r600_cs.h index c8bb2976f84..f56c92c1017 100644 --- a/src/gallium/drivers/radeon/r600_cs.h +++ b/src/gallium/drivers/radeon/r600_cs.h @@ -30,7 +30,7 @@ #ifndef R600_CS_H #define R600_CS_H -#include "../../winsys/radeon/drm/radeon_winsys.h" +#include "r600_pipe_common.h" #include "r600d_common.h" static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 0bfdb47b62b..98c113f91e1 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -176,4 +176,11 @@ static INLINE struct r600_resource *r600_resource(struct pipe_resource *r) return (struct r600_resource*)r; } +static INLINE void +r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res) +{ + pipe_resource_reference((struct pipe_resource **)ptr, + (struct pipe_resource *)res); +} + #endif diff --git a/src/gallium/drivers/radeonsi/Makefile.sources b/src/gallium/drivers/radeonsi/Makefile.sources index 68c82820015..3b04c80a0aa 100644 --- a/src/gallium/drivers/radeonsi/Makefile.sources +++ b/src/gallium/drivers/radeonsi/Makefile.sources @@ -12,7 +12,6 @@ C_SOURCES := \ radeonsi_compute.c \ si_descriptors.c \ si_state.c \ - si_state_streamout.c \ si_state_draw.c \ si_commands.c \ radeonsi_uvd.c diff --git a/src/gallium/drivers/radeonsi/r600.h b/src/gallium/drivers/radeonsi/r600.h index ac3b2f181ea..531ff4094d0 100644 --- a/src/gallium/drivers/radeonsi/r600.h +++ b/src/gallium/drivers/radeonsi/r600.h @@ -62,22 +62,13 @@ struct r600_query { /* The buffer where query results are stored. It's used as a ring, * data blocks for current query are stored sequentially from * results_start to results_end, with wrapping on the buffer end */ - struct si_resource *buffer; + struct r600_resource *buffer; /* The number of dwords for begin_query or end_query. */ unsigned num_cs_dw; /* linked list of queries */ struct list_head list; }; -struct r600_so_target { - struct pipe_stream_output_target b; - - /* The buffer where BUFFER_FILLED_SIZE is stored. */ - struct si_resource *filled_size; - unsigned stride; - unsigned so_index; -}; - #define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) #define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) @@ -98,10 +89,9 @@ void r600_context_queries_suspend(struct r600_context *ctx); void r600_context_queries_resume(struct r600_context *ctx); void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, int flag_wait); -void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence, +void si_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence, unsigned offset, unsigned value); -void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t); bool si_is_timer_query(unsigned type); bool si_query_needs_begin(unsigned type); void si_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); diff --git a/src/gallium/drivers/radeonsi/r600_blit.c b/src/gallium/drivers/radeonsi/r600_blit.c index 692e00b7799..92b5a153ec3 100644 --- a/src/gallium/drivers/radeonsi/r600_blit.c +++ b/src/gallium/drivers/radeonsi/r600_blit.c @@ -84,7 +84,7 @@ static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op rctx->saved_render_cond = rctx->current_render_cond; rctx->saved_render_cond_cond = rctx->current_render_cond_cond; rctx->saved_render_cond_mode = rctx->current_render_cond_mode; - rctx->context.render_condition(&rctx->context, NULL, FALSE, 0); + rctx->b.b.render_condition(&rctx->b.b, NULL, FALSE, 0); } } @@ -93,7 +93,7 @@ static void r600_blitter_end(struct pipe_context *ctx) { struct r600_context *rctx = (struct r600_context *)ctx; if (rctx->saved_render_cond) { - rctx->context.render_condition(&rctx->context, + rctx->b.b.render_condition(&rctx->b.b, rctx->saved_render_cond, rctx->saved_render_cond_cond, rctx->saved_render_cond_mode); @@ -212,13 +212,13 @@ static void si_blit_decompress_depth_in_place(struct r600_context *rctx, surf_tmpl.u.tex.first_layer = layer; surf_tmpl.u.tex.last_layer = layer; - zsurf = rctx->context.create_surface(&rctx->context, &texture->resource.b.b, &surf_tmpl); + zsurf = rctx->b.b.create_surface(&rctx->b.b, &texture->resource.b.b, &surf_tmpl); - r600_blitter_begin(&rctx->context, R600_DECOMPRESS); + r600_blitter_begin(&rctx->b.b, R600_DECOMPRESS); util_blitter_custom_depth_stencil(rctx->blitter, zsurf, NULL, ~0, rctx->custom_dsa_flush_inplace, 1.0f); - r600_blitter_end(&rctx->context); + r600_blitter_end(&rctx->b.b); pipe_surface_reference(&zsurf, NULL); } @@ -316,7 +316,7 @@ void r600_decompress_color_textures(struct r600_context *rctx, tex = (struct r600_texture *)view->texture; assert(tex->cmask.size || tex->fmask.size); - r600_blit_decompress_color(&rctx->context, tex, + r600_blit_decompress_color(&rctx->b.b, tex, view->u.tex.first_level, view->u.tex.last_level, 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level)); } @@ -721,9 +721,9 @@ static void si_blit(struct pipe_context *ctx, void si_init_blit_functions(struct r600_context *rctx) { - rctx->context.clear = r600_clear; - rctx->context.clear_render_target = r600_clear_render_target; - rctx->context.clear_depth_stencil = r600_clear_depth_stencil; - rctx->context.resource_copy_region = r600_resource_copy_region; - rctx->context.blit = si_blit; + rctx->b.b.clear = r600_clear; + rctx->b.b.clear_render_target = r600_clear_render_target; + rctx->b.b.clear_depth_stencil = r600_clear_depth_stencil; + rctx->b.b.resource_copy_region = r600_resource_copy_region; + rctx->b.b.blit = si_blit; } diff --git a/src/gallium/drivers/radeonsi/r600_buffer.c b/src/gallium/drivers/radeonsi/r600_buffer.c index 2bc47c1e5b0..12e5c4d366b 100644 --- a/src/gallium/drivers/radeonsi/r600_buffer.c +++ b/src/gallium/drivers/radeonsi/r600_buffer.c @@ -38,7 +38,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen, struct pipe_resource *buf) { - struct si_resource *rbuffer = si_resource(buf); + struct r600_resource *rbuffer = r600_resource(buf); pb_reference(&rbuffer->buf, NULL); FREE(rbuffer); @@ -53,10 +53,10 @@ static void *r600_buffer_transfer_map(struct pipe_context *ctx, { struct r600_context *rctx = (struct r600_context*)ctx; struct pipe_transfer *transfer; - struct si_resource *rbuffer = si_resource(resource); + struct r600_resource *rbuffer = r600_resource(resource); uint8_t *data; - data = rctx->ws->buffer_map(rbuffer->cs_buf, rctx->cs, usage); + data = rctx->b.ws->buffer_map(rbuffer->cs_buf, rctx->b.rings.gfx.cs, usage); if (!data) { return NULL; } @@ -97,7 +97,7 @@ static const struct u_resource_vtbl r600_buffer_vtbl = }; bool si_init_resource(struct r600_screen *rscreen, - struct si_resource *res, + struct r600_resource *res, unsigned size, unsigned alignment, boolean use_reusable_pool, unsigned usage) { @@ -128,14 +128,14 @@ bool si_init_resource(struct r600_screen *rscreen, } } - res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment, + res->buf = rscreen->b.ws->buffer_create(rscreen->b.ws, size, alignment, use_reusable_pool, initial_domain); if (!res->buf) { return false; } - res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf); + res->cs_buf = rscreen->b.ws->buffer_get_cs_handle(res->buf); res->domains = domains; return true; } @@ -144,16 +144,17 @@ struct pipe_resource *si_buffer_create(struct pipe_screen *screen, const struct pipe_resource *templ) { struct r600_screen *rscreen = (struct r600_screen*)screen; - struct si_resource *rbuffer; + struct r600_resource *rbuffer; /* XXX We probably want a different alignment for buffers and textures. */ unsigned alignment = 4096; - rbuffer = MALLOC_STRUCT(si_resource); + rbuffer = MALLOC_STRUCT(r600_resource); rbuffer->b.b = *templ; pipe_reference_init(&rbuffer->b.b.reference, 1); rbuffer->b.b.screen = screen; rbuffer->b.vtbl = &r600_buffer_vtbl; + util_range_init(&rbuffer->valid_buffer_range); if (!si_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE, templ->usage)) { FREE(rbuffer); @@ -169,7 +170,7 @@ void r600_upload_index_buffer(struct r600_context *rctx, ib->user_buffer, &ib->offset, &ib->buffer); } -void r600_upload_const_buffer(struct r600_context *rctx, struct si_resource **rbuffer, +void r600_upload_const_buffer(struct r600_context *rctx, struct r600_resource **rbuffer, const uint8_t *ptr, unsigned size, uint32_t *const_offset) { diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c index f050b3b965e..d3c9140f1f1 100644 --- a/src/gallium/drivers/radeonsi/r600_hw_context.c +++ b/src/gallium/drivers/radeonsi/r600_hw_context.c @@ -23,7 +23,7 @@ * Authors: * Jerome Glisse */ -#include "r600_hw_context_priv.h" +#include "../radeon/r600_cs.h" #include "radeonsi_pm4.h" #include "radeonsi_pipe.h" #include "sid.h" @@ -35,16 +35,16 @@ /* Get backends mask */ void si_get_backend_mask(struct r600_context *ctx) { - struct radeon_winsys_cs *cs = ctx->cs; - struct si_resource *buffer; + struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; + struct r600_resource *buffer; uint32_t *results; - unsigned num_backends = ctx->screen->info.r600_num_backends; + unsigned num_backends = ctx->screen->b.info.r600_num_backends; unsigned i, mask = 0; /* if backend_map query is supported by the kernel */ - if (ctx->screen->info.r600_backend_map_valid) { - unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes; - unsigned backend_map = ctx->screen->info.r600_backend_map; + if (ctx->screen->b.info.r600_backend_map_valid) { + unsigned num_tile_pipes = ctx->screen->b.info.r600_num_tile_pipes; + unsigned backend_map = ctx->screen->b.info.r600_backend_map; unsigned item_width = 4, item_mask = 0x7; while(num_tile_pipes--) { @@ -61,43 +61,43 @@ void si_get_backend_mask(struct r600_context *ctx) /* otherwise backup path for older kernels */ /* create buffer for event data */ - buffer = si_resource_create_custom(&ctx->screen->screen, + buffer = r600_resource_create_custom(&ctx->screen->b.b, PIPE_USAGE_STAGING, ctx->max_db*16); if (!buffer) goto err; /* initialize buffer with zeroes */ - results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); + results = ctx->b.ws->buffer_map(buffer->cs_buf, ctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE); if (results) { uint64_t va = 0; memset(results, 0, ctx->max_db * 4 * 4); - ctx->ws->buffer_unmap(buffer->cs_buf); + ctx->b.ws->buffer_unmap(buffer->cs_buf); /* emit EVENT_WRITE for ZPASS_DONE */ - va = r600_resource_va(&ctx->screen->screen, (void *)buffer); + va = r600_resource_va(&ctx->screen->b.b, (void *)buffer); cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); cs->buf[cs->cdw++] = va; cs->buf[cs->cdw++] = va >> 32; cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE); + cs->buf[cs->cdw++] = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx, buffer, RADEON_USAGE_WRITE); /* analyze results */ - results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ); + results = ctx->b.ws->buffer_map(buffer->cs_buf, ctx->b.rings.gfx.cs, PIPE_TRANSFER_READ); if (results) { for(i = 0; i < ctx->max_db; i++) { /* at least highest bit will be set if backend is used */ if (results[i*4 + 1]) mask |= (1<<i); } - ctx->ws->buffer_unmap(buffer->cs_buf); + ctx->b.ws->buffer_unmap(buffer->cs_buf); } } - si_resource_reference(&buffer, NULL); + r600_resource_reference(&buffer, NULL); if (mask != 0) { ctx->backend_mask = mask; @@ -129,7 +129,7 @@ void si_need_cs_space(struct r600_context *ctx, unsigned num_dw, int i; /* The number of dwords we already used in the CS so far. */ - num_dw += ctx->cs->cdw; + num_dw += ctx->b.rings.gfx.cs->cdw; for (i = 0; i < SI_NUM_ATOMS(ctx); i++) { if (ctx->atoms.array[i]->dirty) { @@ -170,7 +170,7 @@ void si_need_cs_space(struct r600_context *ctx, unsigned num_dw, /* Flush if there's not enough space. */ if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { - radeonsi_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC); + radeonsi_flush(&ctx->b.b, NULL, RADEON_FLUSH_ASYNC); } } @@ -207,7 +207,7 @@ static void r600_flush_framebuffer(struct r600_context *ctx) void si_context_flush(struct r600_context *ctx, unsigned flags) { - struct radeon_winsys_cs *cs = ctx->cs; + struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; bool queries_suspended = false; #if 0 @@ -252,7 +252,7 @@ void si_context_flush(struct r600_context *ctx, unsigned flags) #endif /* Flush the CS. */ - ctx->ws->cs_flush(ctx->cs, flags, 0); + ctx->b.ws->cs_flush(ctx->b.rings.gfx.cs, flags, 0); #if R600_TRACE_CS if (ctx->screen->trace_bo) { @@ -301,14 +301,14 @@ void si_context_flush(struct r600_context *ctx, unsigned flags) si_all_descriptors_begin_new_cs(ctx); } -void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence_bo, unsigned offset, unsigned value) +void si_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value) { - struct radeon_winsys_cs *cs = ctx->cs; + struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; uint64_t va; si_need_cs_space(ctx, 10, FALSE); - va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo); + va = r600_resource_va(&ctx->screen->b.b, (void*)fence_bo); va = va + (offset << 2); cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); @@ -321,7 +321,7 @@ void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence_b cs->buf[cs->cdw++] = value; /* DATA_LO */ cs->buf[cs->cdw++] = 0; /* DATA_HI */ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE); + cs->buf[cs->cdw++] = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx, fence_bo, RADEON_USAGE_WRITE); } static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index, @@ -347,7 +347,7 @@ static boolean r600_query_result(struct r600_context *ctx, struct r600_query *qu unsigned results_base = query->results_start; char *map; - map = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, + map = ctx->b.ws->buffer_map(query->buffer->cs_buf, ctx->b.rings.gfx.cs, PIPE_TRANSFER_READ | (wait ? 0 : PIPE_TRANSFER_DONTBLOCK)); if (!map) @@ -425,13 +425,13 @@ static boolean r600_query_result(struct r600_context *ctx, struct r600_query *qu } query->results_start = query->results_end; - ctx->ws->buffer_unmap(query->buffer->cs_buf); + ctx->b.ws->buffer_unmap(query->buffer->cs_buf); return TRUE; } void r600_query_begin(struct r600_context *ctx, struct r600_query *query) { - struct radeon_winsys_cs *cs = ctx->cs; + struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; unsigned new_results_end, i; uint32_t *results; uint64_t va; @@ -448,7 +448,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query) switch (query->type) { case PIPE_QUERY_OCCLUSION_COUNTER: case PIPE_QUERY_OCCLUSION_PREDICATE: - results = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); + results = ctx->b.ws->buffer_map(query->buffer->cs_buf, ctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE); if (results) { results = (uint32_t*)((char*)results + query->results_end); memset(results, 0, query->result_size); @@ -460,7 +460,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query) results[(i * 4)+3] = 0x80000000; } } - ctx->ws->buffer_unmap(query->buffer->cs_buf); + ctx->b.ws->buffer_unmap(query->buffer->cs_buf); } break; case PIPE_QUERY_TIME_ELAPSED: @@ -469,17 +469,17 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query) case PIPE_QUERY_PRIMITIVES_GENERATED: case PIPE_QUERY_SO_STATISTICS: case PIPE_QUERY_SO_OVERFLOW_PREDICATE: - results = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); + results = ctx->b.ws->buffer_map(query->buffer->cs_buf, ctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE); results = (uint32_t*)((char*)results + query->results_end); memset(results, 0, query->result_size); - ctx->ws->buffer_unmap(query->buffer->cs_buf); + ctx->b.ws->buffer_unmap(query->buffer->cs_buf); break; default: assert(0); } /* emit begin query */ - va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); + va = r600_resource_va(&ctx->screen->b.b, (void*)query->buffer); va += query->results_end; switch (query->type) { @@ -511,7 +511,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query) assert(0); } cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); + cs->buf[cs->cdw++] = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx, query->buffer, RADEON_USAGE_WRITE); if (!si_is_timer_query(query->type)) { ctx->num_cs_dw_nontimer_queries_suspend += query->num_cs_dw; @@ -520,7 +520,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query) void r600_query_end(struct r600_context *ctx, struct r600_query *query) { - struct radeon_winsys_cs *cs = ctx->cs; + struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; uint64_t va; unsigned new_results_end; @@ -536,7 +536,7 @@ void r600_query_end(struct r600_context *ctx, struct r600_query *query) } } - va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); + va = r600_resource_va(&ctx->screen->b.b, (void*)query->buffer); /* emit end query */ switch (query->type) { case PIPE_QUERY_OCCLUSION_COUNTER: @@ -571,7 +571,7 @@ void r600_query_end(struct r600_context *ctx, struct r600_query *query) assert(0); } cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); + cs->buf[cs->cdw++] = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx, query->buffer, RADEON_USAGE_WRITE); query->results_end = (query->results_end + query->result_size) % query->buffer->b.b.width0; @@ -583,7 +583,7 @@ void r600_query_end(struct r600_context *ctx, struct r600_query *query) void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, int flag_wait) { - struct radeon_winsys_cs *cs = ctx->cs; + struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; uint64_t va; if (operation == PREDICATION_OP_CLEAR) { @@ -605,7 +605,7 @@ void r600_query_predication(struct r600_context *ctx, struct r600_query *query, op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE | (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW); - va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); + va = r600_resource_va(&ctx->screen->b.b, (void*)query->buffer); /* emit predicate packets for all data blocks */ while (results_base != query->results_end) { @@ -613,8 +613,8 @@ void r600_query_predication(struct r600_context *ctx, struct r600_query *query, cs->buf[cs->cdw++] = (va + results_base) & 0xFFFFFFFFUL; cs->buf[cs->cdw++] = op | (((va + results_base) >> 32UL) & 0xFF); cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, - RADEON_USAGE_READ); + cs->buf[cs->cdw++] = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx, + query->buffer, RADEON_USAGE_READ); results_base = (results_base + query->result_size) % query->buffer->b.b.width0; /* set CONTINUE bit for all packets except the first */ @@ -669,7 +669,7 @@ struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned * being written by the gpu, hence staging is probably a good * usage pattern. */ - query->buffer = si_resource_create_custom(&ctx->screen->screen, + query->buffer = r600_resource_create_custom(&ctx->screen->b.b, PIPE_USAGE_STAGING, buffer_size); if (!query->buffer) { @@ -681,7 +681,7 @@ struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query) { - si_resource_reference(&query->buffer, NULL); + r600_resource_reference(&query->buffer, NULL); free(query); } @@ -709,7 +709,7 @@ boolean r600_context_query_result(struct r600_context *ctx, break; case PIPE_QUERY_TIMESTAMP: case PIPE_QUERY_TIME_ELAPSED: - *result_u64 = (1000000 * query->result.u64) / ctx->screen->info.r600_clock_crystal_freq; + *result_u64 = (1000000 * query->result.u64) / ctx->screen->b.info.r600_clock_crystal_freq; break; case PIPE_QUERY_SO_STATISTICS: *result_so = query->result.so; @@ -741,33 +741,6 @@ void r600_context_queries_resume(struct r600_context *ctx) } } -void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t) -{ - struct radeon_winsys_cs *cs = ctx->cs; - si_need_cs_space(ctx, 14 + 21, TRUE); - - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - SI_CONTEXT_REG_OFFSET) >> 2; - cs->buf[cs->cdw++] = 0; - - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - SI_CONTEXT_REG_OFFSET) >> 2; - cs->buf[cs->cdw++] = t->stride >> 2; - -#if 0 - cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); - cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; - cs->buf[cs->cdw++] = 0; /* src address lo */ - cs->buf[cs->cdw++] = 0; /* src address hi */ - cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ - cs->buf[cs->cdw++] = 0; /* unused */ -#endif - - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ); - -} - #if R600_TRACE_CS void r600_trace_emit(struct r600_context *rctx) { diff --git a/src/gallium/drivers/radeonsi/r600_hw_context_priv.h b/src/gallium/drivers/radeonsi/r600_hw_context_priv.h deleted file mode 100644 index c2a15ebb966..00000000000 --- a/src/gallium/drivers/radeonsi/r600_hw_context_priv.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse <[email protected]> - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - */ -#ifndef R600_PRIV_H -#define R600_PRIV_H - -#include "radeonsi_pipe.h" -#include "util/u_hash_table.h" -#include "os/os_thread.h" - -#define SI_MAX_DRAW_CS_DWORDS 18 - -#define PKT_COUNT_C 0xC000FFFF -#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) - -static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct si_resource *rbo, - enum radeon_bo_usage usage) -{ - assert(usage); - return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; -} - -#endif diff --git a/src/gallium/drivers/radeonsi/r600_query.c b/src/gallium/drivers/radeonsi/r600_query.c index aa51e741739..e9fce94ee93 100644 --- a/src/gallium/drivers/radeonsi/r600_query.c +++ b/src/gallium/drivers/radeonsi/r600_query.c @@ -136,12 +136,12 @@ static void r600_render_condition(struct pipe_context *ctx, void r600_init_query_functions(struct r600_context *rctx) { - rctx->context.create_query = r600_create_query; - rctx->context.destroy_query = r600_destroy_query; - rctx->context.begin_query = r600_begin_query; - rctx->context.end_query = r600_end_query; - rctx->context.get_query_result = r600_get_query_result; - - if (rctx->screen->info.r600_num_backends > 0) - rctx->context.render_condition = r600_render_condition; + rctx->b.b.create_query = r600_create_query; + rctx->b.b.destroy_query = r600_destroy_query; + rctx->b.b.begin_query = r600_begin_query; + rctx->b.b.end_query = r600_end_query; + rctx->b.b.get_query_result = r600_get_query_result; + + if (rctx->screen->b.info.r600_num_backends > 0) + rctx->b.b.render_condition = r600_render_condition; } diff --git a/src/gallium/drivers/radeonsi/r600_resource.c b/src/gallium/drivers/radeonsi/r600_resource.c index 33ccd003090..660e279ac2e 100644 --- a/src/gallium/drivers/radeonsi/r600_resource.c +++ b/src/gallium/drivers/radeonsi/r600_resource.c @@ -54,8 +54,8 @@ void r600_init_screen_resource_functions(struct pipe_screen *screen) void r600_init_context_resource_functions(struct r600_context *r600) { - r600->context.transfer_map = u_transfer_map_vtbl; - r600->context.transfer_flush_region = u_transfer_flush_region_vtbl; - r600->context.transfer_unmap = u_transfer_unmap_vtbl; - r600->context.transfer_inline_write = u_default_transfer_inline_write; + r600->b.b.transfer_map = u_transfer_map_vtbl; + r600->b.b.transfer_flush_region = u_transfer_flush_region_vtbl; + r600->b.b.transfer_unmap = u_transfer_unmap_vtbl; + r600->b.b.transfer_inline_write = u_default_transfer_inline_write; } diff --git a/src/gallium/drivers/radeonsi/r600_resource.h b/src/gallium/drivers/radeonsi/r600_resource.h index da02b070bf5..3f9c7692728 100644 --- a/src/gallium/drivers/radeonsi/r600_resource.h +++ b/src/gallium/drivers/radeonsi/r600_resource.h @@ -37,7 +37,7 @@ struct r600_transfer { /* Buffer transfer. */ struct pipe_transfer *buffer_transfer; unsigned offset; - struct si_resource *staging; + struct r600_resource *staging; }; struct r600_fmask_info { @@ -58,7 +58,7 @@ struct r600_cmask_info { }; struct r600_texture { - struct si_resource resource; + struct r600_resource resource; unsigned size; unsigned pitch_override; @@ -93,7 +93,7 @@ bool r600_init_flushed_depth_texture(struct pipe_context *ctx, struct r600_context; -void r600_upload_const_buffer(struct r600_context *rctx, struct si_resource **rbuffer, +void r600_upload_const_buffer(struct r600_context *rctx, struct r600_resource **rbuffer, const uint8_t *ptr, unsigned size, uint32_t *const_offset); diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c index 8e01b141af8..bc66dc3b8b4 100644 --- a/src/gallium/drivers/radeonsi/r600_texture.c +++ b/src/gallium/drivers/radeonsi/r600_texture.c @@ -219,7 +219,7 @@ static int r600_setup_surface(struct pipe_screen *screen, struct r600_screen *rscreen = (struct r600_screen*)screen; int r; - r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); + r = rscreen->b.ws->surface_init(rscreen->b.ws, &rtex->surface); if (r) { return r; } @@ -246,11 +246,11 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen, struct winsys_handle *whandle) { struct r600_texture *rtex = (struct r600_texture*)ptex; - struct si_resource *resource = &rtex->resource; + struct r600_resource *resource = &rtex->resource; struct radeon_surface *surface = &rtex->surface; struct r600_screen *rscreen = (struct r600_screen*)screen; - rscreen->ws->buffer_set_tiling(resource->buf, + rscreen->b.ws->buffer_set_tiling(resource->buf, NULL, surface->level[0].mode >= RADEON_SURF_MODE_1D ? RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, @@ -262,7 +262,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen, surface->mtilea, surface->level[0].pitch_bytes); - return rscreen->ws->buffer_get_handle(resource->buf, + return rscreen->b.ws->buffer_get_handle(resource->buf, surface->level[0].pitch_bytes, whandle); } @@ -270,10 +270,10 @@ static void r600_texture_destroy(struct pipe_screen *screen, struct pipe_resource *ptex) { struct r600_texture *rtex = (struct r600_texture*)ptex; - struct si_resource *resource = &rtex->resource; + struct r600_resource *resource = &rtex->resource; if (rtex->flushed_depth_texture) - si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL); + r600_resource_reference((struct r600_resource **)&rtex->flushed_depth_texture, NULL); pb_reference(&resource->buf, NULL); FREE(rtex); @@ -312,7 +312,7 @@ static void r600_texture_get_fmask_info(struct r600_screen *rscreen, return; } - if (rscreen->ws->surface_init(rscreen->ws, &fmask)) { + if (rscreen->b.ws->surface_init(rscreen->b.ws, &fmask)) { R600_ERR("Got error in surface_init while allocating FMASK.\n"); return; } @@ -402,7 +402,7 @@ r600_texture_create_object(struct pipe_screen *screen, struct radeon_surface *surface) { struct r600_texture *rtex; - struct si_resource *resource; + struct r600_resource *resource; struct r600_screen *rscreen = (struct r600_screen*)screen; int r; @@ -448,13 +448,13 @@ r600_texture_create_object(struct pipe_screen *screen, } } else if (buf) { resource->buf = buf; - resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); + resource->cs_buf = rscreen->b.ws->buffer_get_cs_handle(buf); resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; } if (rtex->cmask.size) { /* Initialize the cmask to 0xCC (= compressed state). */ - char *map = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE); + char *map = rscreen->b.ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE); memset(map + rtex->cmask.offset, 0xCC, rtex->cmask.size); } @@ -526,7 +526,7 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen, templ->target != PIPE_TEXTURE_1D && templ->target != PIPE_TEXTURE_1D_ARRAY && templ->height0 > 3 && - rscreen->chip_class < CIK /* XXX fix me */) { + rscreen->b.chip_class < CIK /* XXX fix me */) { array_mode = V_009910_ARRAY_2D_TILED_THIN1; } else { array_mode = V_009910_ARRAY_1D_TILED_THIN1; @@ -538,7 +538,7 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen, if (r) { return NULL; } - r = rscreen->ws->surface_best(rscreen->ws, &surface); + r = rscreen->b.ws->surface_best(rscreen->b.ws, &surface); if (r) { return NULL; } @@ -599,11 +599,11 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, templ->depth0 != 1 || templ->last_level != 0) return NULL; - buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); + buf = rscreen->b.ws->buffer_from_handle(rscreen->b.ws, whandle, &stride); if (!buf) return NULL; - rscreen->ws->buffer_get_tiling(buf, µ, ¯o, + rscreen->b.ws->buffer_get_tiling(buf, µ, ¯o, &surface.bankw, &surface.bankh, &surface.tile_split, &surface.stencil_tile_split, @@ -731,8 +731,8 @@ static void *si_texture_transfer_map(struct pipe_context *ctx, /* Use a staging texture for uploads if the underlying BO is busy. */ if (!(usage & PIPE_TRANSFER_READ) && - (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) || - rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) { + (rctx->b.ws->cs_is_buffer_referenced(rctx->b.rings.gfx.cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) || + rctx->b.ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) { use_staging_texture = TRUE; } @@ -804,7 +804,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx, trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes; trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size; - trans->staging = (struct si_resource*)staging_depth; + trans->staging = (struct r600_resource*)staging_depth; } else if (use_staging_texture) { struct pipe_resource resource; struct r600_texture *staging; @@ -838,7 +838,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx, buf = rtex->resource.cs_buf; } - if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) { + if (!(map = rctx->b.ws->buffer_map(buf, rctx->b.rings.gfx.cs, usage))) { pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL); FREE(trans); return NULL; @@ -860,9 +860,9 @@ static void si_texture_transfer_unmap(struct pipe_context *ctx, if (rtransfer->staging) { buf = rtransfer->staging->cs_buf; } else { - buf = si_resource(transfer->resource)->cs_buf; + buf = r600_resource(transfer->resource)->cs_buf; } - rctx->ws->buffer_unmap(buf); + rctx->b.ws->buffer_unmap(buf); if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) { @@ -883,8 +883,8 @@ static void si_texture_transfer_unmap(struct pipe_context *ctx, void si_init_surface_functions(struct r600_context *r600) { - r600->context.create_surface = r600_create_surface; - r600->context.surface_destroy = r600_surface_destroy; + r600->b.b.create_surface = r600_create_surface; + r600->b.b.surface_destroy = r600_surface_destroy; } static const struct u_resource_vtbl r600_texture_vtbl = diff --git a/src/gallium/drivers/radeonsi/r600_translate.c b/src/gallium/drivers/radeonsi/r600_translate.c index 8633d770d10..ccb72d5fca1 100644 --- a/src/gallium/drivers/radeonsi/r600_translate.c +++ b/src/gallium/drivers/radeonsi/r600_translate.c @@ -42,7 +42,7 @@ void r600_translate_index_buffer(struct r600_context *r600, &out_offset, &out_buffer, &ptr); util_shorten_ubyte_elts_to_userptr( - &r600->context, ib, 0, ib->offset, count, ptr); + &r600->b.b, ib, 0, ib->offset, count, ptr); pipe_resource_reference(&ib->buffer, NULL); ib->buffer = out_buffer; diff --git a/src/gallium/drivers/radeonsi/radeonsi_compute.c b/src/gallium/drivers/radeonsi/radeonsi_compute.c index 10309bad0e1..41354806434 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_compute.c +++ b/src/gallium/drivers/radeonsi/radeonsi_compute.c @@ -1,5 +1,6 @@ #include "util/u_memory.h" +#include "../radeon/r600_cs.h" #include "radeonsi_pipe.h" #include "radeonsi_shader.h" @@ -91,7 +92,7 @@ static void radeonsi_launch_grid( struct r600_context *rctx = (struct r600_context*)ctx; struct si_pipe_compute *program = rctx->cs_shader_state.program; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - struct si_resource *kernel_args_buffer = NULL; + struct r600_resource *kernel_args_buffer = NULL; unsigned kernel_args_size; unsigned num_work_size_bytes = 36; uint32_t kernel_args_offset = 0; @@ -152,8 +153,8 @@ static void radeonsi_launch_grid( /* Global buffers */ for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) { - struct si_resource *buffer = - (struct si_resource*)program->global_buffers[i]; + struct r600_resource *buffer = + (struct r600_resource*)program->global_buffers[i]; if (!buffer) { continue; } @@ -250,13 +251,13 @@ static void si_bind_compute_sampler_states( void **samplers_) { } void si_init_compute_functions(struct r600_context *rctx) { - rctx->context.create_compute_state = radeonsi_create_compute_state; - rctx->context.delete_compute_state = si_delete_compute_state; - rctx->context.bind_compute_state = radeonsi_bind_compute_state; + rctx->b.b.create_compute_state = radeonsi_create_compute_state; + rctx->b.b.delete_compute_state = si_delete_compute_state; + rctx->b.b.bind_compute_state = radeonsi_bind_compute_state; /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */ - rctx->context.set_compute_resources = si_set_compute_resources; - rctx->context.set_compute_sampler_views = si_set_cs_sampler_view; - rctx->context.bind_compute_sampler_states = si_bind_compute_sampler_states; - rctx->context.set_global_binding = radeonsi_set_global_binding; - rctx->context.launch_grid = radeonsi_launch_grid; + rctx->b.b.set_compute_resources = si_set_compute_resources; + rctx->b.b.set_compute_sampler_views = si_set_cs_sampler_view; + rctx->b.b.bind_compute_sampler_states = si_bind_compute_sampler_states; + rctx->b.b.set_global_binding = radeonsi_set_global_binding; + rctx->b.b.launch_grid = radeonsi_launch_grid; } diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c index 8a5d7016d10..bb44cccce7e 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c @@ -49,8 +49,8 @@ #include "sid.h" #include "r600_resource.h" #include "radeonsi_pipe.h" -#include "r600_hw_context_priv.h" #include "si_state.h" +#include "../radeon/r600_cs.h" /* * pipe_context @@ -64,15 +64,15 @@ static struct r600_fence *r600_create_fence(struct r600_context *rctx) if (!rscreen->fences.bo) { /* Create the shared buffer object */ - rscreen->fences.bo = si_resource_create_custom(&rscreen->screen, + rscreen->fences.bo = r600_resource_create_custom(&rscreen->b.b, PIPE_USAGE_STAGING, 4096); if (!rscreen->fences.bo) { R600_ERR("r600: failed to create bo for fence objects\n"); goto out; } - rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf, - rctx->cs, + rscreen->fences.data = rctx->b.ws->buffer_map(rscreen->fences.bo->cs_buf, + rctx->b.rings.gfx.cs, PIPE_TRANSFER_READ_WRITE); } @@ -122,10 +122,10 @@ static struct r600_fence *r600_create_fence(struct r600_context *rctx) si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1); /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */ - fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1); + fence->sleep_bo = r600_resource_create_custom(&rctx->screen->b.b, PIPE_USAGE_STAGING, 1); /* Add the fence as a dummy relocation. */ - r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE); + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, fence->sleep_bo, RADEON_USAGE_READWRITE); out: pipe_mutex_unlock(rscreen->fences.mutex); @@ -180,19 +180,19 @@ static void r600_destroy_context(struct pipe_context *context) si_release_all_descriptors(rctx); - si_resource_reference(&rctx->border_color_table, NULL); + r600_resource_reference(&rctx->border_color_table, NULL); if (rctx->dummy_pixel_shader) { - rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader); + rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader); } for (int i = 0; i < 8; i++) { - rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth_stencil[i]); - rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth[i]); - rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_stencil[i]); + rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_depth_stencil[i]); + rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_depth[i]); + rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_stencil[i]); } - rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_inplace); - rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve); - rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress); + rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_inplace); + rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve); + rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress); util_unreference_framebuffer_state(&rctx->framebuffer); util_blitter_destroy(rctx->blitter); @@ -201,6 +201,8 @@ static void r600_destroy_context(struct pipe_context *context) u_upload_destroy(rctx->uploader); } util_slab_destroy(&rctx->pool_transfers); + + r600_common_context_cleanup(&rctx->b); FREE(rctx); } @@ -212,16 +214,16 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void if (rctx == NULL) return NULL; - rctx->context.screen = screen; - rctx->context.priv = priv; - rctx->context.destroy = r600_destroy_context; - rctx->context.flush = r600_flush_from_st; + if (!r600_common_context_init(&rctx->b, &rscreen->b)) + goto fail; + + rctx->b.b.screen = screen; + rctx->b.b.priv = priv; + rctx->b.b.destroy = r600_destroy_context; + rctx->b.b.flush = r600_flush_from_st; /* Easy accessing of screen/winsys. */ rctx->screen = rscreen; - rctx->ws = rscreen->ws; - rctx->family = rscreen->family; - rctx->chip_class = rscreen->chip_class; si_init_blit_functions(rctx); r600_init_query_functions(rctx); @@ -229,19 +231,20 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void si_init_surface_functions(rctx); si_init_compute_functions(rctx); - if (rscreen->info.has_uvd) { - rctx->context.create_video_codec = radeonsi_uvd_create_decoder; - rctx->context.create_video_buffer = radeonsi_video_buffer_create; + if (rscreen->b.info.has_uvd) { + rctx->b.b.create_video_codec = radeonsi_uvd_create_decoder; + rctx->b.b.create_video_buffer = radeonsi_video_buffer_create; } else { - rctx->context.create_video_codec = vl_create_decoder; - rctx->context.create_video_buffer = vl_video_buffer_create; + rctx->b.b.create_video_codec = vl_create_decoder; + rctx->b.b.create_video_buffer = vl_video_buffer_create; } - rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL); + rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL); + rctx->b.rings.gfx.flush = r600_flush_from_winsys; si_init_all_descriptors(rctx); - switch (rctx->chip_class) { + switch (rctx->b.chip_class) { case SI: case CIK: si_init_state_functions(rctx); @@ -250,40 +253,38 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void si_init_config(rctx); break; default: - R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); - r600_destroy_context(&rctx->context); - return NULL; + R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class); + goto fail; } - rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); + rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx); util_slab_create(&rctx->pool_transfers, sizeof(struct pipe_transfer), 64, UTIL_SLAB_SINGLETHREADED); - rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256, + rctx->uploader = u_upload_create(&rctx->b.b, 1024 * 1024, 256, PIPE_BIND_INDEX_BUFFER | PIPE_BIND_CONSTANT_BUFFER); - if (!rctx->uploader) { - r600_destroy_context(&rctx->context); - return NULL; - } + if (!rctx->uploader) + goto fail; - rctx->blitter = util_blitter_create(&rctx->context); - if (rctx->blitter == NULL) { - r600_destroy_context(&rctx->context); - return NULL; - } + rctx->blitter = util_blitter_create(&rctx->b.b); + if (rctx->blitter == NULL) + goto fail; si_get_backend_mask(rctx); /* this emits commands and must be last */ rctx->dummy_pixel_shader = - util_make_fragment_cloneinput_shader(&rctx->context, 0, + util_make_fragment_cloneinput_shader(&rctx->b.b, 0, TGSI_SEMANTIC_GENERIC, TGSI_INTERPOLATE_CONSTANT); - rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader); + rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader); - return &rctx->context; + return &rctx->b.b; +fail: + r600_destroy_context(&rctx->b.b); + return NULL; } /* @@ -328,7 +329,7 @@ static const char* r600_get_name(struct pipe_screen* pscreen) { struct r600_screen *rscreen = (struct r600_screen *)pscreen; - return r600_get_family_name(rscreen->family); + return r600_get_family_name(rscreen->b.family); } static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) @@ -374,7 +375,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return 1; case PIPE_CAP_TEXTURE_MULTISAMPLE: - return HAVE_LLVM >= 0x0304 && rscreen->chip_class == SI; + return HAVE_LLVM >= 0x0304 && rscreen->b.chip_class == SI; case PIPE_CAP_TGSI_TEXCOORD: return 0; @@ -439,7 +440,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) /* Timer queries, present when the clock frequency is non zero. */ case PIPE_CAP_QUERY_TIMESTAMP: case PIPE_CAP_QUERY_TIME_ELAPSED: - return rscreen->info.r600_clock_crystal_freq != 0; + return rscreen->b.info.r600_clock_crystal_freq != 0; case PIPE_CAP_MIN_TEXEL_OFFSET: return -8; @@ -568,7 +569,7 @@ static int r600_get_compute_param(struct pipe_screen *screen, //TODO: select these params by asic switch (param) { case PIPE_COMPUTE_CAP_IR_TARGET: { - const char *gpu = r600_get_llvm_processor_name(rscreen->family); + const char *gpu = r600_get_llvm_processor_name(rscreen->b.family); if (ret) { sprintf(ret, "%s-r600--", gpu); } @@ -654,8 +655,8 @@ static void r600_destroy_screen(struct pipe_screen* pscreen) FREE(entry); } - rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf); - si_resource_reference(&rscreen->fences.bo, NULL); + rscreen->b.ws->buffer_unmap(rscreen->fences.bo->cs_buf); + r600_resource_reference(&rscreen->fences.bo, NULL); } #if R600_TRACE_CS @@ -667,7 +668,7 @@ static void r600_destroy_screen(struct pipe_screen* pscreen) pipe_mutex_destroy(rscreen->fences.mutex); - rscreen->ws->destroy(rscreen->ws); + rscreen->b.ws->destroy(rscreen->b.ws); FREE(rscreen); } @@ -681,7 +682,7 @@ static void r600_fence_reference(struct pipe_screen *pscreen, if (pipe_reference(&(*oldf)->reference, &newf->reference)) { struct r600_screen *rscreen = (struct r600_screen *)pscreen; pipe_mutex_lock(rscreen->fences.mutex); - si_resource_reference(&(*oldf)->sleep_bo, NULL); + r600_resource_reference(&(*oldf)->sleep_bo, NULL); LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); pipe_mutex_unlock(rscreen->fences.mutex); } @@ -717,13 +718,13 @@ static boolean r600_fence_finish(struct pipe_screen *pscreen, while (rscreen->fences.data[rfence->index] == 0) { /* Special-case infinite timeout - wait for the dummy BO to become idle */ if (timeout == PIPE_TIMEOUT_INFINITE) { - rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE); + rscreen->b.ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE); break; } /* The dummy BO will be busy until the CS including the fence has completed, or * the GPU is reset. Don't bother continuing to spin when the BO is idle. */ - if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE)) + if (!rscreen->b.ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE)) break; if (++spins % 256) @@ -790,7 +791,7 @@ static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tili static int r600_init_tiling(struct r600_screen *rscreen) { - uint32_t tiling_config = rscreen->info.r600_tiling_config; + uint32_t tiling_config = rscreen->b.info.r600_tiling_config; /* set default group bytes, overridden by tiling info ioctl */ rscreen->tiling_info.group_bytes = 512; @@ -805,19 +806,8 @@ static uint64_t r600_get_timestamp(struct pipe_screen *screen) { struct r600_screen *rscreen = (struct r600_screen*)screen; - return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) / - rscreen->info.r600_clock_crystal_freq; -} - -static unsigned radeon_family_from_device(unsigned device) -{ - switch (device) { -#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; -#include "pci_ids/radeonsi_pci_ids.h" -#undef CHIPSET - default: - return CHIP_UNKNOWN; - } + return 1000000 * rscreen->b.ws->query_value(rscreen->b.ws, RADEON_TIMESTAMP) / + rscreen->b.info.r600_clock_crystal_freq; } struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws) @@ -827,53 +817,34 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws) return NULL; } - rscreen->ws = ws; - ws->query_info(ws, &rscreen->info); - - rscreen->family = radeon_family_from_device(rscreen->info.pci_id); - if (rscreen->family == CHIP_UNKNOWN) { - fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); - FREE(rscreen); - return NULL; - } - - /* setup class */ - if (rscreen->family >= CHIP_BONAIRE) { - rscreen->chip_class = CIK; - } else if (rscreen->family >= CHIP_TAHITI) { - rscreen->chip_class = SI; - } else { - fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family); - FREE(rscreen); - return NULL; - } + r600_common_screen_init(&rscreen->b, ws); if (r600_init_tiling(rscreen)) { FREE(rscreen); return NULL; } - rscreen->screen.destroy = r600_destroy_screen; - rscreen->screen.get_name = r600_get_name; - rscreen->screen.get_vendor = r600_get_vendor; - rscreen->screen.get_param = r600_get_param; - rscreen->screen.get_shader_param = r600_get_shader_param; - rscreen->screen.get_paramf = r600_get_paramf; - rscreen->screen.get_compute_param = r600_get_compute_param; - rscreen->screen.get_timestamp = r600_get_timestamp; - rscreen->screen.is_format_supported = si_is_format_supported; - rscreen->screen.context_create = r600_create_context; - rscreen->screen.fence_reference = r600_fence_reference; - rscreen->screen.fence_signalled = r600_fence_signalled; - rscreen->screen.fence_finish = r600_fence_finish; - r600_init_screen_resource_functions(&rscreen->screen); - - if (rscreen->info.has_uvd) { - rscreen->screen.get_video_param = ruvd_get_video_param; - rscreen->screen.is_video_format_supported = ruvd_is_format_supported; + rscreen->b.b.destroy = r600_destroy_screen; + rscreen->b.b.get_name = r600_get_name; + rscreen->b.b.get_vendor = r600_get_vendor; + rscreen->b.b.get_param = r600_get_param; + rscreen->b.b.get_shader_param = r600_get_shader_param; + rscreen->b.b.get_paramf = r600_get_paramf; + rscreen->b.b.get_compute_param = r600_get_compute_param; + rscreen->b.b.get_timestamp = r600_get_timestamp; + rscreen->b.b.is_format_supported = si_is_format_supported; + rscreen->b.b.context_create = r600_create_context; + rscreen->b.b.fence_reference = r600_fence_reference; + rscreen->b.b.fence_signalled = r600_fence_signalled; + rscreen->b.b.fence_finish = r600_fence_finish; + r600_init_screen_resource_functions(&rscreen->b.b); + + if (rscreen->b.info.has_uvd) { + rscreen->b.b.get_video_param = ruvd_get_video_param; + rscreen->b.b.is_video_format_supported = ruvd_is_format_supported; } else { - rscreen->screen.get_video_param = r600_get_video_param; - rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; + rscreen->b.b.get_video_param = r600_get_video_param; + rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported; } util_format_s3tc_init(); @@ -888,7 +859,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws) #if R600_TRACE_CS rscreen->cs_count = 0; if (rscreen->info.drm_minor >= 28) { - rscreen->trace_bo = (struct si_resource*)pipe_buffer_create(&rscreen->screen, + rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING, 4096); @@ -899,5 +870,5 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws) } #endif - return &rscreen->screen; + return &rscreen->b.b; } diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h index 8a9f1ff503d..517925d8650 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h @@ -26,9 +26,8 @@ #ifndef RADEONSI_PIPE_H #define RADEONSI_PIPE_H -#include "../../winsys/radeon/drm/radeon_winsys.h" +#include "../radeon/r600_pipe_common.h" -#include "pipe/p_state.h" #include "pipe/p_screen.h" #include "pipe/p_context.h" #include "util/u_format.h" @@ -50,10 +49,12 @@ #define R600_TRACE_CS 0 #define R600_TRACE_CS_DWORDS 6 +#define SI_MAX_DRAW_CS_DWORDS 18 + struct si_pipe_compute; struct r600_pipe_fences { - struct si_resource *bo; + struct r600_resource *bo; unsigned *data; unsigned next_index; /* linked list of preallocated blocks */ @@ -64,16 +65,12 @@ struct r600_pipe_fences { }; struct r600_screen { - struct pipe_screen screen; - struct radeon_winsys *ws; - unsigned family; - enum chip_class chip_class; - struct radeon_info info; + struct r600_common_screen b; struct r600_tiling_info tiling_info; struct util_slab_mempool pool_buffers; struct r600_pipe_fences fences; #if R600_TRACE_CS - struct si_resource *trace_bo; + struct r600_resource *trace_bo; uint32_t *trace_ptr; unsigned cs_count; #endif @@ -81,7 +78,7 @@ struct r600_screen { struct si_pipe_sampler_view { struct pipe_sampler_view base; - struct si_resource *resource; + struct r600_resource *resource; uint32_t state[8]; uint32_t fmask_state[8]; }; @@ -107,7 +104,7 @@ struct r600_textures_info { struct r600_fence { struct pipe_reference reference; unsigned index; /* in the shared bo */ - struct si_resource *sleep_bo; + struct r600_resource *sleep_bo; struct list_head head; }; @@ -129,10 +126,8 @@ struct r600_constbuf_state #define SI_NUM_SHADERS (PIPE_SHADER_FRAGMENT+1) struct r600_context { - struct pipe_context context; + struct r600_common_context b; struct blitter_context *blitter; - enum radeon_family family; - enum chip_class chip_class; void *custom_dsa_flush_depth_stencil[8]; void *custom_dsa_flush_depth[8]; void *custom_dsa_flush_stencil[8]; @@ -140,13 +135,12 @@ struct r600_context { void *custom_blend_resolve; void *custom_blend_decompress; struct r600_screen *screen; - struct radeon_winsys *ws; union { struct { - struct si_atom *sampler_views[SI_NUM_SHADERS]; + struct r600_atom *sampler_views[SI_NUM_SHADERS]; }; - struct si_atom *array[0]; + struct r600_atom *array[0]; } atoms; struct si_vertex_element *vertex_elements; @@ -172,7 +166,7 @@ struct r600_context { unsigned export_16bpc; struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES]; struct r600_textures_info samplers[SI_NUM_SHADERS]; - struct si_resource *border_color_table; + struct r600_resource *border_color_table; unsigned border_color_offset; struct u_upload_mgr *uploader; @@ -182,8 +176,6 @@ struct r600_context { /* Below are variables from the old r600_context. */ - struct radeon_winsys_cs *cs; - unsigned pm4_dirty_cdwords; /* The list of active queries. Only one query of each type can be active. */ @@ -235,7 +227,7 @@ void r600_decompress_color_textures(struct r600_context *rctx, /* r600_buffer.c */ bool si_init_resource(struct r600_screen *rscreen, - struct si_resource *res, + struct r600_resource *res, unsigned size, unsigned alignment, boolean use_reusable_pool, unsigned usage); struct pipe_resource *si_buffer_create(struct pipe_screen *screen, @@ -321,12 +313,4 @@ static INLINE unsigned r600_pack_float_12p4(float x) x >= 4096 ? 0xffff : x * 16; } -static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) -{ - struct r600_screen *rscreen = (struct r600_screen*)screen; - struct si_resource *rresource = (struct si_resource*)resource; - - return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); -} - #endif diff --git a/src/gallium/drivers/radeonsi/radeonsi_pm4.c b/src/gallium/drivers/radeonsi/radeonsi_pm4.c index bbc62d3b1aa..9d0a7c03b76 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pm4.c +++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.c @@ -24,11 +24,11 @@ * Christian König <[email protected]> */ +#include "../radeon/r600_cs.h" #include "util/u_memory.h" #include "radeonsi_pipe.h" #include "radeonsi_pm4.h" #include "sid.h" -#include "r600_hw_context_priv.h" #define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *)) @@ -92,13 +92,13 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val) } void si_pm4_add_bo(struct si_pm4_state *state, - struct si_resource *bo, + struct r600_resource *bo, enum radeon_bo_usage usage) { unsigned idx = state->nbo++; assert(idx < SI_PM4_MAX_BO); - si_resource_reference(&state->bo[idx], bo); + r600_resource_reference(&state->bo[idx], bo); state->bo_usage[idx] = usage; } @@ -168,7 +168,7 @@ void si_pm4_free_state(struct r600_context *rctx, } for (int i = 0; i < state->nbo; ++i) { - si_resource_reference(&state->bo[i], NULL); + r600_resource_reference(&state->bo[i], NULL); } FREE(state); } @@ -180,7 +180,7 @@ struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx) if (pm4 == NULL) return NULL; - pm4->chip_class = rctx->chip_class; + pm4->chip_class = rctx->b.chip_class; return pm4; } @@ -224,9 +224,9 @@ unsigned si_pm4_dirty_dw(struct r600_context *rctx) void si_pm4_emit(struct r600_context *rctx, struct si_pm4_state *state) { - struct radeon_winsys_cs *cs = rctx->cs; + struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; for (int i = 0; i < state->nbo; ++i) { - r600_context_bo_reloc(rctx, state->bo[i], + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, state->bo[i], state->bo_usage[i]); } diff --git a/src/gallium/drivers/radeonsi/radeonsi_pm4.h b/src/gallium/drivers/radeonsi/radeonsi_pm4.h index 68aa36a773f..b74db083949 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pm4.h +++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.h @@ -55,7 +55,7 @@ struct si_pm4_state /* BO's referenced by this state */ unsigned nbo; - struct si_resource *bo[SI_PM4_MAX_BO]; + struct r600_resource *bo[SI_PM4_MAX_BO]; enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO]; /* relocs for shader data */ @@ -71,7 +71,7 @@ void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate); void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val); void si_pm4_add_bo(struct si_pm4_state *state, - struct si_resource *bo, + struct r600_resource *bo, enum radeon_bo_usage usage); void si_pm4_sh_data_begin(struct si_pm4_state *state); diff --git a/src/gallium/drivers/radeonsi/radeonsi_resource.h b/src/gallium/drivers/radeonsi/radeonsi_resource.h index 9f4b4c136cf..7794beb9c57 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_resource.h +++ b/src/gallium/drivers/radeonsi/radeonsi_resource.h @@ -27,40 +27,16 @@ #ifndef RADEONSI_RESOURCE_H #define RADEONSI_RESOURCE_H -#include "../../winsys/radeon/drm/radeon_winsys.h" +#include "../radeon/r600_pipe_common.h" #include "util/u_transfer.h" #include "util/u_inlines.h" -struct si_resource { - struct u_resource b; - - /* Winsys objects. */ - struct pb_buffer *buf; - struct radeon_winsys_cs_handle *cs_buf; - - /* Resource state. */ - unsigned domains; -}; - -static INLINE void -si_resource_reference(struct si_resource **ptr, struct si_resource *res) -{ - pipe_resource_reference((struct pipe_resource **)ptr, - (struct pipe_resource *)res); -} - -static INLINE struct si_resource * -si_resource(struct pipe_resource *r) -{ - return (struct si_resource*)r; -} - -static INLINE struct si_resource * -si_resource_create_custom(struct pipe_screen *screen, - unsigned usage, unsigned size) +static INLINE struct r600_resource * +r600_resource_create_custom(struct pipe_screen *screen, + unsigned usage, unsigned size) { assert(size); - return si_resource(pipe_buffer_create(screen, + return r600_resource(pipe_buffer_create(screen, PIPE_BIND_CUSTOM, usage, size)); } diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c index 13bc92c509d..77915aefee7 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_shader.c +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c @@ -1503,7 +1503,7 @@ int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader, memset(&binary, 0, sizeof(binary)); radeon_llvm_compile(mod, &binary, - r600_get_llvm_processor_name(rctx->screen->family), dump); + r600_get_llvm_processor_name(rctx->screen->b.family), dump); if (dump) { fprintf(stderr, "SI CODE:\n"); for (i = 0; i < binary.code_size; i+=4 ) { @@ -1544,14 +1544,14 @@ int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader, } /* copy new shader */ - si_resource_reference(&shader->bo, NULL); - shader->bo = si_resource_create_custom(rctx->context.screen, PIPE_USAGE_IMMUTABLE, + r600_resource_reference(&shader->bo, NULL); + shader->bo = r600_resource_create_custom(rctx->b.b.screen, PIPE_USAGE_IMMUTABLE, binary.code_size); if (shader->bo == NULL) { return -ENOMEM; } - ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE); + ptr = (uint32_t*)rctx->b.ws->buffer_map(shader->bo->cs_buf, rctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE); if (0 /*R600_BIG_ENDIAN*/) { for (i = 0; i < binary.code_size / 4; ++i) { ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4)); @@ -1559,7 +1559,7 @@ int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader, } else { memcpy(ptr, binary.code, binary.code_size); } - rctx->ws->buffer_unmap(shader->bo->cs_buf); + rctx->b.ws->buffer_unmap(shader->bo->cs_buf); free(binary.code); free(binary.config); @@ -1658,5 +1658,5 @@ int si_pipe_shader_create( void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader) { - si_resource_reference(&shader->bo, NULL); + r600_resource_reference(&shader->bo, NULL); } diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h index 6c6b96e033a..1e8d0e94e62 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_shader.h +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h @@ -138,7 +138,7 @@ struct si_pipe_shader { struct si_pipe_shader *next_variant; struct si_shader shader; struct si_pm4_state *pm4; - struct si_resource *bo; + struct r600_resource *bo; unsigned num_sgprs; unsigned num_vgprs; unsigned lds_size; diff --git a/src/gallium/drivers/radeonsi/radeonsi_uvd.c b/src/gallium/drivers/radeonsi/radeonsi_uvd.c index 4d48b4e6f9c..de6cc12e45b 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_uvd.c +++ b/src/gallium/drivers/radeonsi/radeonsi_uvd.c @@ -109,14 +109,14 @@ struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe pbs[i] = &resources[i]->resource.buf; } - ruvd_join_surfaces(ctx->ws, templ.bind, pbs, surfaces); + ruvd_join_surfaces(ctx->b.ws, templ.bind, pbs, surfaces); for (i = 0; i < VL_NUM_COMPONENTS; ++i) { if (!resources[i]) continue; /* recreate the CS handle */ - resources[i]->resource.cs_buf = ctx->ws->buffer_get_cs_handle( + resources[i]->resource.cs_buf = ctx->b.ws->buffer_get_cs_handle( resources[i]->resource.buf); } @@ -151,5 +151,5 @@ struct pipe_video_codec *radeonsi_uvd_create_decoder(struct pipe_context *contex { struct r600_context *ctx = (struct r600_context *)context; - return ruvd_create_decoder(context, templ, ctx->ws, radeonsi_uvd_set_dtb); + return ruvd_create_decoder(context, templ, ctx->b.ws, radeonsi_uvd_set_dtb); } diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index e171f8af9ad..db0da754036 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -23,11 +23,10 @@ * Authors: * Marek Olšák <[email protected]> */ - +#include "../radeon/r600_cs.h" #include "radeonsi_pipe.h" #include "radeonsi_resource.h" #include "radeonsi_shader.h" -#include "r600_hw_context_priv.h" #include "util/u_memory.h" @@ -51,14 +50,14 @@ static void si_emit_cp_dma_copy_buffer(struct r600_context *rctx, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags) { - struct radeon_winsys_cs *cs = rctx->cs; + struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0; uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0; assert(size); assert((size & ((1<<21)-1)) == size); - if (rctx->chip_class >= CIK) { + if (rctx->b.chip_class >= CIK) { radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0)); radeon_emit(cs, sync_flag); /* CP_SYNC [31] */ radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ @@ -81,14 +80,14 @@ static void si_emit_cp_dma_clear_buffer(struct r600_context *rctx, uint64_t dst_va, unsigned size, uint32_t clear_value, unsigned flags) { - struct radeon_winsys_cs *cs = rctx->cs; + struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0; uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0; assert(size); assert((size & ((1<<21)-1)) == size); - if (rctx->chip_class >= CIK) { + if (rctx->b.chip_class >= CIK) { radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0)); radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */ radeon_emit(cs, clear_value); /* DATA [31:0] */ @@ -111,26 +110,26 @@ static void si_init_descriptors(struct r600_context *rctx, unsigned shader_userdata_reg, unsigned element_dw_size, unsigned num_elements, - void (*emit_func)(struct r600_context *ctx, struct si_atom *state)) + void (*emit_func)(struct r600_context *ctx, struct r600_atom *state)) { uint64_t va; assert(num_elements <= sizeof(desc->enabled_mask)*8); assert(num_elements <= sizeof(desc->dirty_mask)*8); - desc->atom.emit = emit_func; + desc->atom.emit = (void*)emit_func; desc->shader_userdata_reg = shader_userdata_reg; desc->element_dw_size = element_dw_size; desc->num_elements = num_elements; desc->context_size = num_elements * element_dw_size * 4; - desc->buffer = (struct si_resource*) - pipe_buffer_create(rctx->context.screen, PIPE_BIND_CUSTOM, + desc->buffer = (struct r600_resource*) + pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, SI_NUM_CONTEXTS * desc->context_size); - r600_context_bo_reloc(rctx, desc->buffer, RADEON_USAGE_READWRITE); - va = r600_resource_va(rctx->context.screen, &desc->buffer->b.b); + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READWRITE); + va = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b); /* We don't check for CS space here, because this should be called * only once at context initialization. */ @@ -159,8 +158,8 @@ static void si_update_descriptors(struct si_descriptors *desc) static void si_emit_shader_pointer(struct r600_context *rctx, struct si_descriptors *desc) { - struct radeon_winsys_cs *cs = rctx->cs; - uint64_t va = r600_resource_va(rctx->context.screen, &desc->buffer->b.b) + + struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; + uint64_t va = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b) + desc->current_context_id * desc->context_size; radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0)); @@ -173,7 +172,7 @@ static void si_emit_descriptors(struct r600_context *rctx, struct si_descriptors *desc, const uint32_t **descriptors) { - struct radeon_winsys_cs *cs = rctx->cs; + struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; uint64_t va_base; int packet_start; int packet_size = 0; @@ -183,7 +182,7 @@ static void si_emit_descriptors(struct r600_context *rctx, assert(dirty_mask); - va_base = r600_resource_va(rctx->context.screen, &desc->buffer->b.b); + va_base = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b); /* Copy the descriptors to a new context slot. */ si_emit_cp_dma_copy_buffer(rctx, @@ -252,7 +251,7 @@ static unsigned si_get_shader_user_data_base(unsigned shader) /* SAMPLER VIEWS */ -static void si_emit_sampler_views(struct r600_context *rctx, struct si_atom *atom) +static void si_emit_sampler_views(struct r600_context *rctx, struct r600_atom *atom) { struct si_sampler_views *views = (struct si_sampler_views*)atom; @@ -290,10 +289,10 @@ static void si_sampler_views_begin_new_cs(struct r600_context *rctx, struct si_pipe_sampler_view *rview = (struct si_pipe_sampler_view*)views->views[i]; - r600_context_bo_reloc(rctx, rview->resource, RADEON_USAGE_READ); + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ); } - r600_context_bo_reloc(rctx, views->desc.buffer, RADEON_USAGE_READWRITE); + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, views->desc.buffer, RADEON_USAGE_READWRITE); si_emit_shader_pointer(rctx, &views->desc); } @@ -311,7 +310,7 @@ void si_set_sampler_view(struct r600_context *rctx, unsigned shader, struct si_pipe_sampler_view *rview = (struct si_pipe_sampler_view*)view; - r600_context_bo_reloc(rctx, rview->resource, RADEON_USAGE_READ); + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ); pipe_sampler_view_reference(&views->views[slot], view); views->desc_data[slot] = view_desc; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 6410e45a5cd..b4370dad1f8 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -36,6 +36,7 @@ #include "radeonsi_pipe.h" #include "radeonsi_shader.h" #include "si_state.h" +#include "../radeon/r600_cs.h" #include "sid.h" static uint32_t cik_num_banks(uint32_t nbanks) @@ -795,7 +796,7 @@ static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth, memset(&dsa, 0, sizeof(dsa)); - state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); + state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa); if (copy_depth || copy_stencil) { si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, S_028000_DEPTH_COPY(copy_depth) | @@ -1302,7 +1303,7 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, int first_non_void) { struct r600_screen *rscreen = (struct r600_screen*)screen; - bool enable_s3tc = rscreen->info.drm_minor >= 31; + bool enable_s3tc = rscreen->b.info.drm_minor >= 31; boolean uniform = TRUE; int i; @@ -1689,7 +1690,7 @@ boolean si_is_format_supported(struct pipe_screen *screen, return FALSE; if (sample_count > 1) { - if (HAVE_LLVM < 0x0304 || rscreen->chip_class != SI) + if (HAVE_LLVM < 0x0304 || rscreen->b.chip_class != SI) return FALSE; switch (sample_count) { @@ -1871,7 +1872,7 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, color_info |= S_028C70_FAST_CLEAR(1); } - offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); + offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture); offset >>= 8; /* FIXME handle enabling of CB beyond BASE8 which has different offset */ @@ -1950,7 +1951,7 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, } assert(format != V_028040_Z_INVALID); - s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture); + s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture); z_offs += rtex->surface.level[level].offset; s_offs += rtex->surface.stencil_level[level].offset; @@ -1975,7 +1976,7 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, else s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); - if (rctx->chip_class >= CIK) { + if (rctx->b.chip_class >= CIK) { switch (rtex->surface.level[level].mode) { case RADEON_SURF_MODE_2D: array_mode = V_02803C_ARRAY_2D_TILED_THIN1; @@ -1998,8 +1999,8 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, bankw = cik_bank_wh(bankw); bankh = cik_bank_wh(bankh); nbanks = cik_num_banks(rscreen->tiling_info.num_banks); - pipe_config = cik_db_pipe_config(rscreen->info.r600_num_tile_pipes, - rscreen->info.r600_num_backends); + pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes, + rscreen->b.info.r600_num_backends); db_depth_info |= S_02803C_ARRAY_MODE(array_mode) | S_02803C_PIPE_CONFIG(pipe_config) | @@ -2924,19 +2925,19 @@ static struct si_pm4_state *si_bind_sampler_states(struct r600_context *rctx, un if (!rctx->border_color_table || ((rctx->border_color_offset + count - i) & C_008F3C_BORDER_COLOR_PTR)) { - si_resource_reference(&rctx->border_color_table, NULL); + r600_resource_reference(&rctx->border_color_table, NULL); rctx->border_color_offset = 0; rctx->border_color_table = - si_resource_create_custom(&rctx->screen->screen, + r600_resource_create_custom(&rctx->screen->b.b, PIPE_USAGE_STAGING, 4096 * 4 * 4); } if (!border_color_table) { border_color_table = - rctx->ws->buffer_map(rctx->border_color_table->cs_buf, - rctx->cs, + rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf, + rctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED); } @@ -2958,13 +2959,13 @@ static struct si_pm4_state *si_bind_sampler_states(struct r600_context *rctx, un if (border_color_table) { uint64_t va_offset = - r600_resource_va(&rctx->screen->screen, + r600_resource_va(&rctx->screen->b.b, (void*)rctx->border_color_table); si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); - if (rctx->chip_class >= CIK) + if (rctx->b.chip_class >= CIK) si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40); - rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf); + rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf); si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ); } @@ -3043,7 +3044,7 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint i if (ptr) { r600_upload_const_buffer(rctx, - (struct si_resource**)&cb->buffer, ptr, + (struct r600_resource**)&cb->buffer, ptr, cb->buffer_size, &cb->buffer_offset); } else { /* Setup the hw buffer. */ @@ -3184,25 +3185,25 @@ static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode) memset(&blend, 0, sizeof(blend)); blend.independent_blend_enable = true; blend.rt[0].colormask = 0xf; - return si_create_blend_state_mode(&rctx->context, &blend, mode); + return si_create_blend_state_mode(&rctx->b.b, &blend, mode); } void si_init_state_functions(struct r600_context *rctx) { int i; - rctx->context.create_blend_state = si_create_blend_state; - rctx->context.bind_blend_state = si_bind_blend_state; - rctx->context.delete_blend_state = si_delete_blend_state; - rctx->context.set_blend_color = si_set_blend_color; + rctx->b.b.create_blend_state = si_create_blend_state; + rctx->b.b.bind_blend_state = si_bind_blend_state; + rctx->b.b.delete_blend_state = si_delete_blend_state; + rctx->b.b.set_blend_color = si_set_blend_color; - rctx->context.create_rasterizer_state = si_create_rs_state; - rctx->context.bind_rasterizer_state = si_bind_rs_state; - rctx->context.delete_rasterizer_state = si_delete_rs_state; + rctx->b.b.create_rasterizer_state = si_create_rs_state; + rctx->b.b.bind_rasterizer_state = si_bind_rs_state; + rctx->b.b.delete_rasterizer_state = si_delete_rs_state; - rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state; - rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state; - rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state; + rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state; + rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state; + rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state; for (i = 0; i < 8; i++) { rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i); @@ -3213,49 +3214,45 @@ void si_init_state_functions(struct r600_context *rctx) rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE); rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS); - rctx->context.set_clip_state = si_set_clip_state; - rctx->context.set_scissor_states = si_set_scissor_states; - rctx->context.set_viewport_states = si_set_viewport_states; - rctx->context.set_stencil_ref = si_set_pipe_stencil_ref; + rctx->b.b.set_clip_state = si_set_clip_state; + rctx->b.b.set_scissor_states = si_set_scissor_states; + rctx->b.b.set_viewport_states = si_set_viewport_states; + rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref; - rctx->context.set_framebuffer_state = si_set_framebuffer_state; - rctx->context.get_sample_position = si_get_sample_position; + rctx->b.b.set_framebuffer_state = si_set_framebuffer_state; + rctx->b.b.get_sample_position = si_get_sample_position; - rctx->context.create_vs_state = si_create_vs_state; - rctx->context.create_fs_state = si_create_fs_state; - rctx->context.bind_vs_state = si_bind_vs_shader; - rctx->context.bind_fs_state = si_bind_ps_shader; - rctx->context.delete_vs_state = si_delete_vs_shader; - rctx->context.delete_fs_state = si_delete_ps_shader; + rctx->b.b.create_vs_state = si_create_vs_state; + rctx->b.b.create_fs_state = si_create_fs_state; + rctx->b.b.bind_vs_state = si_bind_vs_shader; + rctx->b.b.bind_fs_state = si_bind_ps_shader; + rctx->b.b.delete_vs_state = si_delete_vs_shader; + rctx->b.b.delete_fs_state = si_delete_ps_shader; - rctx->context.create_sampler_state = si_create_sampler_state; - rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler_states; - rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler_states; - rctx->context.delete_sampler_state = si_delete_sampler_state; + rctx->b.b.create_sampler_state = si_create_sampler_state; + rctx->b.b.bind_vertex_sampler_states = si_bind_vs_sampler_states; + rctx->b.b.bind_fragment_sampler_states = si_bind_ps_sampler_states; + rctx->b.b.delete_sampler_state = si_delete_sampler_state; - rctx->context.create_sampler_view = si_create_sampler_view; - rctx->context.set_vertex_sampler_views = si_set_vs_sampler_views; - rctx->context.set_fragment_sampler_views = si_set_ps_sampler_views; - rctx->context.sampler_view_destroy = si_sampler_view_destroy; + rctx->b.b.create_sampler_view = si_create_sampler_view; + rctx->b.b.set_vertex_sampler_views = si_set_vs_sampler_views; + rctx->b.b.set_fragment_sampler_views = si_set_ps_sampler_views; + rctx->b.b.sampler_view_destroy = si_sampler_view_destroy; - rctx->context.set_sample_mask = si_set_sample_mask; + rctx->b.b.set_sample_mask = si_set_sample_mask; - rctx->context.set_constant_buffer = si_set_constant_buffer; + rctx->b.b.set_constant_buffer = si_set_constant_buffer; - rctx->context.create_vertex_elements_state = si_create_vertex_elements; - rctx->context.bind_vertex_elements_state = si_bind_vertex_elements; - rctx->context.delete_vertex_elements_state = si_delete_vertex_element; - rctx->context.set_vertex_buffers = si_set_vertex_buffers; - rctx->context.set_index_buffer = si_set_index_buffer; + rctx->b.b.create_vertex_elements_state = si_create_vertex_elements; + rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements; + rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element; + rctx->b.b.set_vertex_buffers = si_set_vertex_buffers; + rctx->b.b.set_index_buffer = si_set_index_buffer; - rctx->context.create_stream_output_target = si_create_so_target; - rctx->context.stream_output_target_destroy = si_so_target_destroy; - rctx->context.set_stream_output_targets = si_set_so_targets; + rctx->b.b.texture_barrier = si_texture_barrier; + rctx->b.b.set_polygon_stipple = si_set_polygon_stipple; - rctx->context.texture_barrier = si_texture_barrier; - rctx->context.set_polygon_stipple = si_set_polygon_stipple; - - rctx->context.draw_vbo = si_draw_vbo; + rctx->b.b.draw_vbo = si_draw_vbo; } void si_init_config(struct r600_context *rctx) @@ -3292,7 +3289,7 @@ void si_init_config(struct r600_context *rctx) S_028AA8_PRIMGROUP_SIZE(63)); si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); - if (rctx->chip_class < CIK) + if (rctx->b.chip_class < CIK) si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1)); @@ -3302,8 +3299,8 @@ void si_init_config(struct r600_context *rctx) si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); - if (rctx->chip_class >= CIK) { - switch (rctx->screen->family) { + if (rctx->b.chip_class >= CIK) { + switch (rctx->screen->b.family) { case CHIP_BONAIRE: si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012); si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); @@ -3318,7 +3315,7 @@ void si_init_config(struct r600_context *rctx) break; } } else { - switch (rctx->screen->family) { + switch (rctx->screen->b.family) { case CHIP_TAHITI: case CHIP_PITCAIRN: si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a); diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index abc2512a532..20ae4332c4c 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -29,14 +29,6 @@ #include "radeonsi_pm4.h" -/* This encapsulates a state or an operation which can emitted into the GPU - * command stream. */ -struct si_atom { - void (*emit)(struct r600_context *ctx, struct si_atom *state); - unsigned num_dw; - bool dirty; -}; - struct si_state_blend { struct si_pm4_state pm4; uint32_t cb_target_mask; @@ -126,7 +118,7 @@ union si_state { * image resources, and sampler states. */ struct si_descriptors { - struct si_atom atom; + struct r600_atom atom; /* The size of one resource descriptor. */ unsigned element_dw_size; @@ -134,7 +126,7 @@ struct si_descriptors { unsigned num_elements; /* The buffer where resource descriptors are stored. */ - struct si_resource *buffer; + struct r600_resource *buffer; /* The i-th bit is set if that element is dirty (changed but not emitted). */ unsigned dirty_mask; @@ -212,19 +204,6 @@ int si_shader_select(struct pipe_context *ctx, void si_init_state_functions(struct r600_context *rctx); void si_init_config(struct r600_context *rctx); -/* si_state_streamout.c */ -struct pipe_stream_output_target * -si_create_so_target(struct pipe_context *ctx, - struct pipe_resource *buffer, - unsigned buffer_offset, - unsigned buffer_size); -void si_so_target_destroy(struct pipe_context *ctx, - struct pipe_stream_output_target *target); -void si_set_so_targets(struct pipe_context *ctx, - unsigned num_targets, - struct pipe_stream_output_target **targets, - unsigned append_bitmask); - /* si_state_draw.c */ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo); diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 44ec735d567..1f740ba6f93 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -31,6 +31,7 @@ #include "radeonsi_pipe.h" #include "radeonsi_shader.h" #include "si_state.h" +#include "../radeon/r600_cs.h" #include "sid.h" /* @@ -107,7 +108,7 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, S_00B12C_USER_SGPR(num_user_sgprs)); - if (rctx->chip_class >= CIK) { + if (rctx->b.chip_class >= CIK) { si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff)); si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, @@ -233,7 +234,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS, S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) | S_00B02C_USER_SGPR(num_user_sgprs)); - if (rctx->chip_class >= CIK) { + if (rctx->b.chip_class >= CIK) { si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff)); } @@ -290,7 +291,7 @@ static bool si_update_draw_info_state(struct r600_context *rctx, return false; } - if (rctx->chip_class >= CIK) + if (rctx->b.chip_class >= CIK) si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim); else si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim); @@ -454,7 +455,7 @@ static void si_update_derived_state(struct r600_context *rctx) static void si_constant_buffer_update(struct r600_context *rctx) { - struct pipe_context *ctx = &rctx->context; + struct pipe_context *ctx = &rctx->b.b; struct si_pm4_state *pm4; unsigned shader, i; uint64_t va; @@ -476,7 +477,7 @@ static void si_constant_buffer_update(struct r600_context *rctx) for (i = 0; i < 2; i++) { if (state->enabled_mask & (1 << i)) { struct pipe_constant_buffer *cb = &state->cb[i]; - struct si_resource *rbuffer = si_resource(cb->buffer); + struct r600_resource *rbuffer = r600_resource(cb->buffer); va = r600_resource_va(ctx->screen, (void*)rbuffer); va += cb->buffer_offset; @@ -526,7 +527,7 @@ static void si_constant_buffer_update(struct r600_context *rctx) static void si_vertex_buffer_update(struct r600_context *rctx) { - struct pipe_context *ctx = &rctx->context; + struct pipe_context *ctx = &rctx->b.b; struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); bool bound[PIPE_MAX_ATTRIBS] = {}; unsigned i, count; @@ -542,14 +543,14 @@ static void si_vertex_buffer_update(struct r600_context *rctx) for (i = 0 ; i < count; i++) { struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i]; struct pipe_vertex_buffer *vb; - struct si_resource *rbuffer; + struct r600_resource *rbuffer; unsigned offset; if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers) continue; vb = &rctx->vertex_buffer[ve->vertex_buffer_index]; - rbuffer = (struct si_resource*)vb->buffer; + rbuffer = (struct r600_resource*)vb->buffer; if (rbuffer == NULL) continue; @@ -624,10 +625,10 @@ static void si_state_draw(struct r600_context *rctx, uint32_t max_size = (ib->buffer->width0 - ib->offset) / rctx->index_buffer.index_size; uint64_t va; - va = r600_resource_va(&rctx->screen->screen, ib->buffer); + va = r600_resource_va(&rctx->screen->b.b, ib->buffer); va += ib->offset; - si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ); + si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ); si_cmd_draw_index_2(pm4, max_size, va, info->count, V_0287F0_DI_SRC_SEL_DMA, rctx->predicate_drawing); @@ -668,9 +669,6 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) if (ib.user_buffer && !ib.buffer) { r600_upload_index_buffer(rctx, &ib, info->count); } - - } else if (info->count_from_stream_output) { - r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output); } rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides; @@ -709,7 +707,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) for (i = 0; i < SI_NUM_ATOMS(rctx); i++) { if (rctx->atoms.array[i]->dirty) { - rctx->atoms.array[i]->emit(rctx, rctx->atoms.array[i]); + rctx->atoms.array[i]->emit(&rctx->b, rctx->atoms.array[i]); rctx->atoms.array[i]->dirty = false; } } diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c deleted file mode 100644 index 2e17d90494e..00000000000 --- a/src/gallium/drivers/radeonsi/si_state_streamout.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Copyright 2012 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Christian König <[email protected]> - */ - -#include "radeonsi_pipe.h" -#include "si_state.h" - -/* - * Stream out - */ - -#if 0 -void si_context_streamout_begin(struct r600_context *ctx) -{ - struct radeon_winsys_cs *cs = ctx->cs; - struct si_so_target **t = ctx->so_targets; - unsigned *strides = ctx->vs_shader_so_strides; - unsigned buffer_en, i; - - buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) | - (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) | - (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) | - (ctx->num_so_targets >= 4 && t[3] ? 8 : 0); - - ctx->num_cs_dw_streamout_end = - 12 + /* flush_vgt_streamout */ - util_bitcount(buffer_en) * 8 + - 3; - - si_need_cs_space(ctx, - 12 + /* flush_vgt_streamout */ - 6 + /* enables */ - util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + - util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + - ctx->num_cs_dw_streamout_end, TRUE); - - evergreen_flush_vgt_streamout(ctx); - evergreen_set_streamout_enable(ctx, buffer_en); - - for (i = 0; i < ctx->num_so_targets; i++) { -#if 0 - if (t[i]) { - t[i]->stride = strides[i]; - t[i]->so_index = i; - - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0); - cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + - 16*i - SI_CONTEXT_REG_OFFSET) >> 2; - cs->buf[cs->cdw++] = (t[i]->b.buffer_offset + - t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */ - cs->buf[cs->cdw++] = strides[i] >> 2; /* VTX_STRIDE (in DW) */ - cs->buf[cs->cdw++] = 0; /* BUFFER_BASE */ - - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = - si_context_bo_reloc(ctx, si_resource(t[i]->b.buffer), - RADEON_USAGE_WRITE); - - if (ctx->streamout_append_bitmask & (1 << i)) { - /* Append. */ - cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); - cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | - STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */ - cs->buf[cs->cdw++] = 0; /* unused */ - cs->buf[cs->cdw++] = 0; /* unused */ - cs->buf[cs->cdw++] = 0; /* src address lo */ - cs->buf[cs->cdw++] = 0; /* src address hi */ - - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = - si_context_bo_reloc(ctx, t[i]->filled_size, - RADEON_USAGE_READ); - } else { - /* Start from the beginning. */ - cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); - cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | - STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */ - cs->buf[cs->cdw++] = 0; /* unused */ - cs->buf[cs->cdw++] = 0; /* unused */ - cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */ - cs->buf[cs->cdw++] = 0; /* unused */ - } - } -#endif - } -} - -void si_context_streamout_end(struct r600_context *ctx) -{ - struct radeon_winsys_cs *cs = ctx->cs; - struct si_so_target **t = ctx->so_targets; - unsigned i, flush_flags = 0; - - evergreen_flush_vgt_streamout(ctx); - - for (i = 0; i < ctx->num_so_targets; i++) { -#if 0 - if (t[i]) { - cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); - cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | - STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) | - STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */ - cs->buf[cs->cdw++] = 0; /* dst address lo */ - cs->buf[cs->cdw++] = 0; /* dst address hi */ - cs->buf[cs->cdw++] = 0; /* unused */ - cs->buf[cs->cdw++] = 0; /* unused */ - - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = - si_context_bo_reloc(ctx, t[i]->filled_size, - RADEON_USAGE_WRITE); - - flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i; - } -#endif - } - - evergreen_set_streamout_enable(ctx, 0); - - ctx->atom_surface_sync.flush_flags |= flush_flags; - si_atom_dirty(ctx, &ctx->atom_surface_sync.atom); - - ctx->num_cs_dw_streamout_end = 0; - - /* XXX print some debug info */ - for (i = 0; i < ctx->num_so_targets; i++) { - if (!t[i]) - continue; - - uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->cs_buf, ctx->cs, RADEON_USAGE_READ); - printf("FILLED_SIZE%i: %u\n", i, *ptr); - ctx->ws->buffer_unmap(t[i]->filled_size->cs_buf); - } -} - -void evergreen_flush_vgt_streamout(struct si_context *ctx) -{ - struct radeon_winsys_cs *cs = ctx->cs; - - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0); - cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2; - cs->buf[cs->cdw++] = 0; - - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0); - - cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0); - cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */ - cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */ - cs->buf[cs->cdw++] = 0; - cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */ - cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */ - cs->buf[cs->cdw++] = 4; /* poll interval */ -} - -void evergreen_set_streamout_enable(struct si_context *ctx, unsigned buffer_enable_bit) -{ - struct radeon_winsys_cs *cs = ctx->cs; - - if (buffer_enable_bit) { - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2; - cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1); - - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2; - cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit); - } else { - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2; - cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0); - } -} - -#endif - -struct pipe_stream_output_target * -si_create_so_target(struct pipe_context *ctx, - struct pipe_resource *buffer, - unsigned buffer_offset, - unsigned buffer_size) -{ -#if 0 - struct si_context *rctx = (struct r600_context *)ctx; - struct si_so_target *t; - void *ptr; - - t = CALLOC_STRUCT(si_so_target); - if (!t) { - return NULL; - } - - t->b.reference.count = 1; - t->b.context = ctx; - pipe_resource_reference(&t->b.buffer, buffer); - t->b.buffer_offset = buffer_offset; - t->b.buffer_size = buffer_size; - - t->filled_size = si_resource_create_custom(ctx->screen, PIPE_USAGE_STATIC, 4); - ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE); - memset(ptr, 0, t->filled_size->buf->size); - rctx->ws->buffer_unmap(t->filled_size->cs_buf); - - return &t->b; -#endif - return NULL; -} - -void si_so_target_destroy(struct pipe_context *ctx, - struct pipe_stream_output_target *target) -{ -#if 0 - struct si_so_target *t = (struct r600_so_target*)target; - pipe_resource_reference(&t->b.buffer, NULL); - si_resource_reference(&t->filled_size, NULL); - FREE(t); -#endif -} - -void si_set_so_targets(struct pipe_context *ctx, - unsigned num_targets, - struct pipe_stream_output_target **targets, - unsigned append_bitmask) -{ - assert(num_targets == 0); -#if 0 - struct si_context *rctx = (struct r600_context *)ctx; - unsigned i; - - /* Stop streamout. */ - if (rctx->num_so_targets) { - si_context_streamout_end(rctx); - } - - /* Set the new targets. */ - for (i = 0; i < num_targets; i++) { - pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]); - } - for (; i < rctx->num_so_targets; i++) { - pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL); - } - - rctx->num_so_targets = num_targets; - rctx->streamout_start = num_targets != 0; - rctx->streamout_append_bitmask = append_bitmask; -#endif -} diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h index f20d0513a38..7f3329ca024 100644 --- a/src/gallium/drivers/radeonsi/sid.h +++ b/src/gallium/drivers/radeonsi/sid.h @@ -132,7 +132,7 @@ #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) #define PKT3_SHADER_TYPE_S(x) (((x) & 0x1) << 1) #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) -#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate)) +#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) #define PKT3_CP_DMA 0x41 /* 1. header |