diff options
| author | Eric Anholt <[email protected]> | 2016-11-11 14:04:42 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2016-11-12 18:46:35 -0800 |
| commit | 977d8b526b983c8d19df00af224033389f8ab7c8 (patch) | |
| tree | ef8e6dfdfb79b39fafa7be6a0705f303481ae100 /src | |
| parent | 9b121512ac0f78d0996613664b456005d88370d2 (diff) | |
vc4: Fix register class handling of DDX/DDY arguments.
I had this exactly backwards, but apparently the piglit tests were all
landing in r0-r3 anyway.
Cc: "13.0" <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/vc4/vc4_register_allocate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/vc4/vc4_register_allocate.c b/src/gallium/drivers/vc4/vc4_register_allocate.c index 6c99b054e9f..ab343ee3134 100644 --- a/src/gallium/drivers/vc4/vc4_register_allocate.c +++ b/src/gallium/drivers/vc4/vc4_register_allocate.c @@ -247,7 +247,7 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c) case QOP_ROT_MUL: assert(inst->src[0].file == QFILE_TEMP); - class_bits[inst->src[0].index] &= ~CLASS_BIT_R0_R3; + class_bits[inst->src[0].index] &= CLASS_BIT_R0_R3; break; default: |