diff options
| author | Plamena Manolova <[email protected]> | 2016-12-06 21:37:01 +0200 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2016-12-07 11:01:50 +0000 |
| commit | 0ff74a8990d9fe37365beb35ed8abacfbf3ed567 (patch) | |
| tree | 080096f24662f203d483fc88acc447c4f054061f /src | |
| parent | 848138689298c11e7825029484cbaa825cd36b36 (diff) | |
i965: Add i965 plumbing for ARB_post_depth_coverage for i965 (gen9+).
This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.
Signed-off-by: Plamena Manolova <[email protected]>
Reviewed-by: Chris Forbes <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_compiler.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_ps_state.c | 13 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_extensions.c | 1 |
4 files changed, 13 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h index 65a74784642..410641f5d94 100644 --- a/src/mesa/drivers/dri/i965/brw_compiler.h +++ b/src/mesa/drivers/dri/i965/brw_compiler.h @@ -397,6 +397,7 @@ struct brw_wm_prog_data { bool computed_stencil; bool early_fragment_tests; + bool post_depth_coverage; bool dispatch_8; bool dispatch_16; bool dual_src_blend; diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index c218f56684d..ce0c07e124f 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -6454,6 +6454,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, shader->info->outputs_read); prog_data->early_fragment_tests = shader->info->fs.early_fragment_tests; + prog_data->post_depth_coverage = shader->info->fs.post_depth_coverage; prog_data->barycentric_interp_modes = brw_compute_barycentric_interp_modes(compiler->devinfo, shader); diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index a4eb962a2cb..33ef0231557 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -53,10 +53,17 @@ gen8_upload_ps_extra(struct brw_context *brw, dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE; if (prog_data->uses_sample_mask) { - if (brw->gen >= 9) - dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; - else + if (brw->gen >= 9) { + if (prog_data->post_depth_coverage) { + dw1 |= BRW_PCICMS_DEPTH << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; + } + else { + dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; + } + } + else { dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK; + } } if (prog_data->uses_omask) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 66079b5fdd8..19f4684a188 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -415,6 +415,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.KHR_texture_compression_astc_ldr = true; ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true; ctx->Extensions.MESA_shader_framebuffer_fetch = true; + ctx->Extensions.ARB_post_depth_coverage = true; } if (ctx->API == API_OPENGL_CORE) |