gallium/radeon: move ring_type into winsyses

Not used by drivers.

Reviewed-by: Bas Nieuwenhuizen <[email protected]>

5 files changed, 11 insertions, 10 deletions

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 0c03652081c..aa94df69362 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -229,7 +229,6 @@ struct radeon_winsys_cs {
     unsigned                    cdw;  /* Number of used dwords. */
     unsigned                    max_dw; /* Maximum number of dwords. */
     uint32_t                    *buf; /* The command buffer. */
-    enum ring_type              ring_type;
 };
 
 struct radeon_info {
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a9fc55f4a5a..63c72fcf003 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -348,7 +348,7 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
    cs->ctx = ctx;
    cs->flush_cs = flush;
    cs->flush_data = flush_ctx;
-   cs->base.ring_type = ring_type;
+   cs->ring_type = ring_type;
 
    if (!amdgpu_init_cs_context(cs, ring_type)) {
       FREE(cs);
@@ -570,7 +570,7 @@ static void amdgpu_cs_do_submission(struct amdgpu_cs *cs,
    cs->request.fence_info.handle = NULL;
    if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE) {
 	cs->request.fence_info.handle = cs->ctx->user_fence_bo;
-	cs->request.fence_info.offset = cs->base.ring_type;
+	cs->request.fence_info.offset = cs->ring_type;
    }
 
    r = amdgpu_cs_submit(cs->ctx->ctx, 0, &cs->request, 1);
@@ -591,7 +591,7 @@ static void amdgpu_cs_do_submission(struct amdgpu_cs *cs,
       amdgpu_fence_submitted(fence, &cs->request, user_fence);
 
       for (i = 0; i < cs->num_buffers; i++)
-         amdgpu_fence_reference(&cs->buffers[i].bo->fence[cs->base.ring_type],
+         amdgpu_fence_reference(&cs->buffers[i].bo->fence[cs->ring_type],
                                 fence);
    }
    pipe_mutex_unlock(ws->bo_fence_lock);
@@ -613,7 +613,7 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
    struct amdgpu_cs *cs = amdgpu_cs(rcs);
    struct amdgpu_winsys *ws = cs->ctx->ws;
 
-   switch (cs->base.ring_type) {
+   switch (cs->ring_type) {
    case RING_DMA:
       /* pad DMA ring to 8 DWs */
       while (rcs->cdw & 7)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index a2fb44a4b0e..f4709e9c325 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -66,6 +66,7 @@ struct amdgpu_cs {
    unsigned used_ib_space;
 
    /* amdgpu_cs_submit parameters */
+   enum ring_type              ring_type;
    struct amdgpu_cs_request    request;
    struct amdgpu_cs_ib_info    ib;
 
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index b50e19c0381..6b2694c6938 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -197,8 +197,8 @@ radeon_drm_cs_create(struct radeon_winsys_ctx *ctx,
     cs->csc = &cs->csc1;
     cs->cst = &cs->csc2;
     cs->base.buf = cs->csc->buf;
-    cs->base.ring_type = ring_type;
     cs->base.max_dw = ARRAY_SIZE(cs->csc->buf);
+    cs->ring_type = ring_type;
 
     p_atomic_inc(&ws->num_cs);
     return &cs->base;
@@ -281,7 +281,7 @@ static unsigned radeon_add_buffer(struct radeon_drm_cs *cs,
          * This doesn't have to be done if virtual memory is enabled,
          * because there is no offset patching with virtual memory.
          */
-        if (cs->base.ring_type != RING_DMA || cs->ws->info.has_virtual_memory) {
+        if (cs->ring_type != RING_DMA || cs->ws->info.has_virtual_memory) {
             return i;
         }
     }
@@ -466,7 +466,7 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
     struct radeon_cs_context *tmp;
 
-    switch (cs->base.ring_type) {
+    switch (cs->ring_type) {
     case RING_DMA:
         /* pad DMA ring to 8 DWs */
         if (cs->ws->info.chip_class <= SI) {
@@ -526,7 +526,7 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
             p_atomic_inc(&cs->cst->relocs_bo[i].bo->num_active_ioctls);
         }
 
-        switch (cs->base.ring_type) {
+        switch (cs->ring_type) {
         case RING_DMA:
             cs->cst->flags[0] = 0;
             cs->cst->flags[1] = RADEON_CS_RING_DMA;
@@ -566,7 +566,7 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
                 cs->cst->flags[0] |= RADEON_CS_END_OF_FRAME;
                 cs->cst->cs.num_chunks = 3;
             }
-            if (cs->base.ring_type == RING_COMPUTE) {
+            if (cs->ring_type == RING_COMPUTE) {
                 cs->cst->flags[1] = RADEON_CS_RING_COMPUTE;
                 cs->cst->cs.num_chunks = 3;
             }
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
index 4ffa91ae8b2..c643b76a9cd 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -59,6 +59,7 @@ struct radeon_cs_context {
 
 struct radeon_drm_cs {
     struct radeon_winsys_cs base;
+    enum ring_type          ring_type;
 
     /* We flip between these two CS. While one is being consumed
      * by the kernel in another thread, the other one is being filled