diff options
| author | Kristian H. Kristensen <[email protected]> | 2019-06-11 11:27:36 -0700 |
|---|---|---|
| committer | Kristian H. Kristensen <[email protected]> | 2019-07-10 22:05:02 +0000 |
| commit | e03259974e2f2c8e8c0295f8dab56d88e7bd896c (patch) | |
| tree | 89db04acb586c0f9cba539c3bcfc2f5adfe54fe5 /src | |
| parent | 51e2124a4b31a656182c3d3fd6d239e94e7582e4 (diff) | |
freedreno: Generate headers from xml files
Reviewed-by: Eric Engestrom <[email protected]>
Acked-by: Rob Clark <[email protected]>
Diffstat (limited to 'src')
29 files changed, 14118 insertions, 23904 deletions
diff --git a/src/freedreno/Android.mk b/src/freedreno/Android.mk index e46e2199dc1..84d0c82c2cb 100644 --- a/src/freedreno/Android.mk +++ b/src/freedreno/Android.mk @@ -28,3 +28,4 @@ include $(LOCAL_PATH)/Makefile.sources include $(MESA_TOP)/src/gallium/drivers/freedreno/Android.gen.mk include $(LOCAL_PATH)/Android.drm.mk include $(LOCAL_PATH)/Android.ir3.mk +include $(LOCAL_PATH)/Android.registers.mk diff --git a/src/freedreno/Android.registers.mk b/src/freedreno/Android.registers.mk new file mode 100644 index 00000000000..e39e330186d --- /dev/null +++ b/src/freedreno/Android.registers.mk @@ -0,0 +1,58 @@ +# Mesa 3-D graphics library +# +# Copyright (C) +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included +# in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +# Android.mk for libfreedreno_registers.a + +# --------------------------------------- +# Build libfreedreno_registers +# --------------------------------------- + +include $(CLEAR_VARS) + +LOCAL_MODULE := libfreedreno_registers + +LOCAL_MODULE_CLASS := STATIC_LIBRARIES + +intermediates := $(call local-generated-sources-dir) + +# dummy.c source file is generated to meet the build system's rules. +LOCAL_GENERATED_SOURCES += $(intermediates)/dummy.c + +$(intermediates)/dummy.c: + @mkdir -p $(dir $@) + @echo "Gen Dummy: $(PRIVATE_MODULE) <= $(notdir $(@))" + $(hide) touch $@ + +# This is the list of auto-generated files headers +LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/registers/, \ + a2xx.xml.h a3xx.xml.h a4xx.xml.h a5xx.xml.h a6xx.xml.h adreno_common.xml.h adreno_pm4.xml.h) + +$(intermediates)/registers/%.xml.h: $(LOCAL_PATH)/registers/%.xml $(LOCAL_PATH)/registers/gen_header.py + @mkdir -p $(dir $@) + @echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))" + $(hide) $(MESA_PYTHON2) $(LOCAL_PATH)/registers/gen_header.py $< > $@ + +LOCAL_EXPORT_C_INCLUDE_DIRS := \ + $(intermediates) + +include $(MESA_COMMON_MK) +include $(BUILD_STATIC_LIBRARY) diff --git a/src/freedreno/Makefile.sources b/src/freedreno/Makefile.sources index d8aaf2caecc..5b983266a62 100644 --- a/src/freedreno/Makefile.sources +++ b/src/freedreno/Makefile.sources @@ -49,12 +49,3 @@ ir3_SOURCES := \ ir3_GENERATED_FILES := \ ir3/ir3_nir_trig.c - -registers_FILES := \ - registers/a2xx.xml.h \ - registers/a3xx.xml.h \ - registers/a4xx.xml.h \ - registers/a5xx.xml.h \ - registers/a6xx.xml.h \ - registers/adreno_common.xml.h \ - registers/adreno_pm4.xml.h diff --git a/src/freedreno/meson.build b/src/freedreno/meson.build index 3f77b1d933e..028ca9f1066 100644 --- a/src/freedreno/meson.build +++ b/src/freedreno/meson.build @@ -22,6 +22,7 @@ inc_freedreno = include_directories(['.', './registers']) subdir('drm') subdir('ir3') +subdir('registers') if with_freedreno_vk subdir('vulkan') diff --git a/src/freedreno/registers/a2xx.xml b/src/freedreno/registers/a2xx.xml new file mode 100644 index 00000000000..ff98e4d17dd --- /dev/null +++ b/src/freedreno/registers/a2xx.xml @@ -0,0 +1,1650 @@ +<?xml version="1.0" encoding="UTF-8"?> +<database xmlns="http://nouveau.freedesktop.org/" +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" +xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> +<import file="freedreno_copyright.xml"/> +<import file="adreno/adreno_common.xml"/> +<import file="adreno/adreno_pm4.xml"/> + + +<enum name="a2xx_rb_dither_type"> + <value name="DITHER_PIXEL" value="0"/> + <value name="DITHER_SUBPIXEL" value="1"/> +</enum> + +<enum name="a2xx_colorformatx"> + <value name="COLORX_4_4_4_4" value="0"/> + <value name="COLORX_1_5_5_5" value="1"/> + <value name="COLORX_5_6_5" value="2"/> + <value name="COLORX_8" value="3"/> + <value name="COLORX_8_8" value="4"/> + <value name="COLORX_8_8_8_8" value="5"/> + <value name="COLORX_S8_8_8_8" value="6"/> + <value name="COLORX_16_FLOAT" value="7"/> + <value name="COLORX_16_16_FLOAT" value="8"/> + <value name="COLORX_16_16_16_16_FLOAT" value="9"/> + <value name="COLORX_32_FLOAT" value="10"/> + <value name="COLORX_32_32_FLOAT" value="11"/> + <value name="COLORX_32_32_32_32_FLOAT" value="12"/> + <value name="COLORX_2_3_3" value="13"/> + <value name="COLORX_8_8_8" value="14"/> +</enum> + +<enum name="a2xx_sq_surfaceformat"> + <value name="FMT_1_REVERSE" value="0"/> + <value name="FMT_1" value="1"/> + <value name="FMT_8" value="2"/> + <value name="FMT_1_5_5_5" value="3"/> + <value name="FMT_5_6_5" value="4"/> + <value name="FMT_6_5_5" value="5"/> + <value name="FMT_8_8_8_8" value="6"/> + <value name="FMT_2_10_10_10" value="7"/> + <value name="FMT_8_A" value="8"/> + <value name="FMT_8_B" value="9"/> + <value name="FMT_8_8" value="10"/> + <value name="FMT_Cr_Y1_Cb_Y0" value="11"/> + <value name="FMT_Y1_Cr_Y0_Cb" value="12"/> + <value name="FMT_5_5_5_1" value="13"/> + <value name="FMT_8_8_8_8_A" value="14"/> + <value name="FMT_4_4_4_4" value="15"/> + <value name="FMT_8_8_8" value="16"/> + <value name="FMT_DXT1" value="18"/> + <value name="FMT_DXT2_3" value="19"/> + <value name="FMT_DXT4_5" value="20"/> + <value name="FMT_10_10_10_2" value="21"/> + <value name="FMT_24_8" value="22"/> + <value name="FMT_16" value="24"/> + <value name="FMT_16_16" value="25"/> + <value name="FMT_16_16_16_16" value="26"/> + <value name="FMT_16_EXPAND" value="27"/> + <value name="FMT_16_16_EXPAND" value="28"/> + <value name="FMT_16_16_16_16_EXPAND" value="29"/> + <value name="FMT_16_FLOAT" value="30"/> + <value name="FMT_16_16_FLOAT" value="31"/> + <value name="FMT_16_16_16_16_FLOAT" value="32"/> + <value name="FMT_32" value="33"/> + <value name="FMT_32_32" value="34"/> + <value name="FMT_32_32_32_32" value="35"/> + <value name="FMT_32_FLOAT" value="36"/> + <value name="FMT_32_32_FLOAT" value="37"/> + <value name="FMT_32_32_32_32_FLOAT" value="38"/> + <value name="FMT_ATI_TC_RGB" value="39"/> + <value name="FMT_ATI_TC_RGBA" value="40"/> + <value name="FMT_ATI_TC_555_565_RGB" value="41"/> + <value name="FMT_ATI_TC_555_565_RGBA" value="42"/> + <value name="FMT_ATI_TC_RGBA_INTERP" value="43"/> + <value name="FMT_ATI_TC_555_565_RGBA_INTERP" value="44"/> + <value name="FMT_ETC1_RGBA_INTERP" value="46"/> + <value name="FMT_ETC1_RGB" value="47"/> + <value name="FMT_ETC1_RGBA" value="48"/> + <value name="FMT_DXN" value="49"/> + <value name="FMT_2_3_3" value="51"/> + <value name="FMT_2_10_10_10_AS_16_16_16_16" value="54"/> + <value name="FMT_10_10_10_2_AS_16_16_16_16" value="55"/> + <value name="FMT_32_32_32_FLOAT" value="57"/> + <value name="FMT_DXT3A" value="58"/> + <value name="FMT_DXT5A" value="59"/> + <value name="FMT_CTX1" value="60"/> +</enum> + +<enum name="a2xx_sq_ps_vtx_mode"> + <value name="POSITION_1_VECTOR" value="0"/> + <value name="POSITION_2_VECTORS_UNUSED" value="1"/> + <value name="POSITION_2_VECTORS_SPRITE" value="2"/> + <value name="POSITION_2_VECTORS_EDGE" value="3"/> + <value name="POSITION_2_VECTORS_KILL" value="4"/> + <value name="POSITION_2_VECTORS_SPRITE_KILL" value="5"/> + <value name="POSITION_2_VECTORS_EDGE_KILL" value="6"/> + <value name="MULTIPASS" value="7"/> +</enum> + +<enum name="a2xx_sq_sample_cntl"> + <value name="CENTROIDS_ONLY" value="0"/> + <value name="CENTERS_ONLY" value="1"/> + <value name="CENTROIDS_AND_CENTERS" value="2"/> +</enum> + +<enum name="a2xx_dx_clip_space"> + <value name="DXCLIP_OPENGL" value="0"/> + <value name="DXCLIP_DIRECTX" value="1"/> +</enum> + +<enum name="a2xx_pa_su_sc_polymode"> + <value name="POLY_DISABLED" value="0"/> + <value name="POLY_DUALMODE" value="1"/> +</enum> + +<enum name="a2xx_rb_edram_mode"> + <value name="EDRAM_NOP" value="0"/> + <value name="COLOR_DEPTH" value="4"/> + <value name="DEPTH_ONLY" value="5"/> + <value name="EDRAM_COPY" value="6"/> +</enum> + +<enum name="a2xx_pa_sc_pattern_bit_order"> + <value name="LITTLE" value="0"/> + <value name="BIG" value="1"/> +</enum> + +<enum name="a2xx_pa_sc_auto_reset_cntl"> + <value name="NEVER" value="0"/> + <value name="EACH_PRIMITIVE" value="1"/> + <value name="EACH_PACKET" value="2"/> +</enum> + +<enum name="a2xx_pa_pixcenter"> + <value name="PIXCENTER_D3D" value="0"/> + <value name="PIXCENTER_OGL" value="1"/> +</enum> + +<enum name="a2xx_pa_roundmode"> + <value name="TRUNCATE" value="0"/> + <value name="ROUND" value="1"/> + <value name="ROUNDTOEVEN" value="2"/> + <value name="ROUNDTOODD" value="3"/> +</enum> + +<enum name="a2xx_pa_quantmode"> + <value name="ONE_SIXTEENTH" value="0"/> + <value name="ONE_EIGTH" value="1"/> + <value name="ONE_QUARTER" value="2"/> + <value name="ONE_HALF" value="3"/> + <value name="ONE" value="4"/> +</enum> + +<enum name="a2xx_rb_copy_sample_select"> + <value name="SAMPLE_0" value="0"/> + <value name="SAMPLE_1" value="1"/> + <value name="SAMPLE_2" value="2"/> + <value name="SAMPLE_3" value="3"/> + <value name="SAMPLE_01" value="4"/> + <value name="SAMPLE_23" value="5"/> + <value name="SAMPLE_0123" value="6"/> +</enum> + +<enum name="a2xx_rb_blend_opcode"> + <value name="BLEND2_DST_PLUS_SRC" value="0"/> + <value name="BLEND2_SRC_MINUS_DST" value="1"/> + <value name="BLEND2_MIN_DST_SRC" value="2"/> + <value name="BLEND2_MAX_DST_SRC" value="3"/> + <value name="BLEND2_DST_MINUS_SRC" value="4"/> + <value name="BLEND2_DST_PLUS_SRC_BIAS" value="5"/> +</enum> + +<enum name="a2xx_su_perfcnt_select"> + <value value="0" name="PERF_PAPC_PASX_REQ"/> + <value value="2" name="PERF_PAPC_PASX_FIRST_VECTOR"/> + <value value="3" name="PERF_PAPC_PASX_SECOND_VECTOR"/> + <value value="4" name="PERF_PAPC_PASX_FIRST_DEAD"/> + <value value="5" name="PERF_PAPC_PASX_SECOND_DEAD"/> + <value value="6" name="PERF_PAPC_PASX_VTX_KILL_DISCARD"/> + <value value="7" name="PERF_PAPC_PASX_VTX_NAN_DISCARD"/> + <value value="8" name="PERF_PAPC_PA_INPUT_PRIM"/> + <value value="9" name="PERF_PAPC_PA_INPUT_NULL_PRIM"/> + <value value="10" name="PERF_PAPC_PA_INPUT_EVENT_FLAG"/> + <value value="11" name="PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT"/> + <value value="12" name="PERF_PAPC_PA_INPUT_END_OF_PACKET"/> + <value value="13" name="PERF_PAPC_CLPR_CULL_PRIM"/> + <value value="15" name="PERF_PAPC_CLPR_VV_CULL_PRIM"/> + <value value="17" name="PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM"/> + <value value="18" name="PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM"/> + <value value="19" name="PERF_PAPC_CLPR_CULL_TO_NULL_PRIM"/> + <value value="21" name="PERF_PAPC_CLPR_VV_CLIP_PRIM"/> + <value value="23" name="PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE"/> + <value value="24" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_1"/> + <value value="25" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_2"/> + <value value="26" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_3"/> + <value value="27" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_4"/> + <value value="28" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_5"/> + <value value="29" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_6"/> + <value value="30" name="PERF_PAPC_CLPR_CLIP_PLANE_NEAR"/> + <value value="31" name="PERF_PAPC_CLPR_CLIP_PLANE_FAR"/> + <value value="32" name="PERF_PAPC_CLPR_CLIP_PLANE_LEFT"/> + <value value="33" name="PERF_PAPC_CLPR_CLIP_PLANE_RIGHT"/> + <value value="34" name="PERF_PAPC_CLPR_CLIP_PLANE_TOP"/> + <value value="35" name="PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM"/> + <value value="36" name="PERF_PAPC_CLSM_NULL_PRIM"/> + <value value="37" name="PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM"/> + <value value="38" name="PERF_PAPC_CLSM_CLIP_PRIM"/> + <value value="39" name="PERF_PAPC_CLSM_CULL_TO_NULL_PRIM"/> + <value value="40" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_1"/> + <value value="41" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_2"/> + <value value="42" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_3"/> + <value value="43" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_4"/> + <value value="44" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_5"/> + <value value="45" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7"/> + <value value="46" name="PERF_PAPC_CLSM_NON_TRIVIAL_CULL"/> + <value value="47" name="PERF_PAPC_SU_INPUT_PRIM"/> + <value value="48" name="PERF_PAPC_SU_INPUT_CLIP_PRIM"/> + <value value="49" name="PERF_PAPC_SU_INPUT_NULL_PRIM"/> + <value value="50" name="PERF_PAPC_SU_ZERO_AREA_CULL_PRIM"/> + <value value="51" name="PERF_PAPC_SU_BACK_FACE_CULL_PRIM"/> + <value value="52" name="PERF_PAPC_SU_FRONT_FACE_CULL_PRIM"/> + <value value="53" name="PERF_PAPC_SU_POLYMODE_FACE_CULL"/> + <value value="54" name="PERF_PAPC_SU_POLYMODE_BACK_CULL"/> + <value value="55" name="PERF_PAPC_SU_POLYMODE_FRONT_CULL"/> + <value value="56" name="PERF_PAPC_SU_POLYMODE_INVALID_FILL"/> + <value value="57" name="PERF_PAPC_SU_OUTPUT_PRIM"/> + <value value="58" name="PERF_PAPC_SU_OUTPUT_CLIP_PRIM"/> + <value value="59" name="PERF_PAPC_SU_OUTPUT_NULL_PRIM"/> + <value value="60" name="PERF_PAPC_SU_OUTPUT_EVENT_FLAG"/> + <value value="61" name="PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT"/> + <value value="62" name="PERF_PAPC_SU_OUTPUT_END_OF_PACKET"/> + <value value="63" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FACE"/> + <value value="64" name="PERF_PAPC_SU_OUTPUT_POLYMODE_BACK"/> + <value value="65" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT"/> + <value value="66" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE"/> + <value value="67" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK"/> + <value value="68" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT"/> + <value value="69" name="PERF_PAPC_PASX_REQ_IDLE"/> + <value value="70" name="PERF_PAPC_PASX_REQ_BUSY"/> + <value value="71" name="PERF_PAPC_PASX_REQ_STALLED"/> + <value value="72" name="PERF_PAPC_PASX_REC_IDLE"/> + <value value="73" name="PERF_PAPC_PASX_REC_BUSY"/> + <value value="74" name="PERF_PAPC_PASX_REC_STARVED_SX"/> + <value value="75" name="PERF_PAPC_PASX_REC_STALLED"/> + <value value="76" name="PERF_PAPC_PASX_REC_STALLED_POS_MEM"/> + <value value="77" name="PERF_PAPC_PASX_REC_STALLED_CCGSM_IN"/> + <value value="78" name="PERF_PAPC_CCGSM_IDLE"/> + <value value="79" name="PERF_PAPC_CCGSM_BUSY"/> + <value value="80" name="PERF_PAPC_CCGSM_STALLED"/> + <value value="81" name="PERF_PAPC_CLPRIM_IDLE"/> + <value value="82" name="PERF_PAPC_CLPRIM_BUSY"/> + <value value="83" name="PERF_PAPC_CLPRIM_STALLED"/> + <value value="84" name="PERF_PAPC_CLPRIM_STARVED_CCGSM"/> + <value value="85" name="PERF_PAPC_CLIPSM_IDLE"/> + <value value="86" name="PERF_PAPC_CLIPSM_BUSY"/> + <value value="87" name="PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH"/> + <value value="88" name="PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ"/> + <value value="89" name="PERF_PAPC_CLIPSM_WAIT_CLIPGA"/> + <value value="90" name="PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP"/> + <value value="91" name="PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM"/> + <value value="92" name="PERF_PAPC_CLIPGA_IDLE"/> + <value value="93" name="PERF_PAPC_CLIPGA_BUSY"/> + <value value="94" name="PERF_PAPC_CLIPGA_STARVED_VTE_CLIP"/> + <value value="95" name="PERF_PAPC_CLIPGA_STALLED"/> + <value value="96" name="PERF_PAPC_CLIP_IDLE"/> + <value value="97" name="PERF_PAPC_CLIP_BUSY"/> + <value value="98" name="PERF_PAPC_SU_IDLE"/> + <value value="99" name="PERF_PAPC_SU_BUSY"/> + <value value="100" name="PERF_PAPC_SU_STARVED_CLIP"/> + <value value="101" name="PERF_PAPC_SU_STALLED_SC"/> + <value value="102" name="PERF_PAPC_SU_FACENESS_CULL"/> +</enum> + +<enum name="a2xx_sc_perfcnt_select"> + <value value="0" name="SC_SR_WINDOW_VALID"/> + <value value="1" name="SC_CW_WINDOW_VALID"/> + <value value="2" name="SC_QM_WINDOW_VALID"/> + <value value="3" name="SC_FW_WINDOW_VALID"/> + <value value="4" name="SC_EZ_WINDOW_VALID"/> + <value value="5" name="SC_IT_WINDOW_VALID"/> + <value value="6" name="SC_STARVED_BY_PA"/> + <value value="7" name="SC_STALLED_BY_RB_TILE"/> + <value value="8" name="SC_STALLED_BY_RB_SAMP"/> + <value value="9" name="SC_STARVED_BY_RB_EZ"/> + <value value="10" name="SC_STALLED_BY_SAMPLE_FF"/> + <value value="11" name="SC_STALLED_BY_SQ"/> + <value value="12" name="SC_STALLED_BY_SP"/> + <value value="13" name="SC_TOTAL_NO_PRIMS"/> + <value value="14" name="SC_NON_EMPTY_PRIMS"/> + <value value="15" name="SC_NO_TILES_PASSING_QM"/> + <value value="16" name="SC_NO_PIXELS_PRE_EZ"/> + <value value="17" name="SC_NO_PIXELS_POST_EZ"/> +</enum> + +<enum name="a2xx_vgt_perfcount_select"> + <value value="0" name="VGT_SQ_EVENT_WINDOW_ACTIVE"/> + <value value="1" name="VGT_SQ_SEND"/> + <value value="2" name="VGT_SQ_STALLED"/> + <value value="3" name="VGT_SQ_STARVED_BUSY"/> + <value value="4" name="VGT_SQ_STARVED_IDLE"/> + <value value="5" name="VGT_SQ_STATIC"/> + <value value="6" name="VGT_PA_EVENT_WINDOW_ACTIVE"/> + <value value="7" name="VGT_PA_CLIP_V_SEND"/> + <value value="8" name="VGT_PA_CLIP_V_STALLED"/> + <value value="9" name="VGT_PA_CLIP_V_STARVED_BUSY"/> + <value value="10" name="VGT_PA_CLIP_V_STARVED_IDLE"/> + <value value="11" name="VGT_PA_CLIP_V_STATIC"/> + <value value="12" name="VGT_PA_CLIP_P_SEND"/> + <value value="13" name="VGT_PA_CLIP_P_STALLED"/> + <value value="14" name="VGT_PA_CLIP_P_STARVED_BUSY"/> + <value value="15" name="VGT_PA_CLIP_P_STARVED_IDLE"/> + <value value="16" name="VGT_PA_CLIP_P_STATIC"/> + <value value="17" name="VGT_PA_CLIP_S_SEND"/> + <value value="18" name="VGT_PA_CLIP_S_STALLED"/> + <value value="19" name="VGT_PA_CLIP_S_STARVED_BUSY"/> + <value value="20" name="VGT_PA_CLIP_S_STARVED_IDLE"/> + <value value="21" name="VGT_PA_CLIP_S_STATIC"/> + <value value="22" name="RBIU_FIFOS_EVENT_WINDOW_ACTIVE"/> + <value value="23" name="RBIU_IMMED_DATA_FIFO_STARVED"/> + <value value="24" name="RBIU_IMMED_DATA_FIFO_STALLED"/> + <value value="25" name="RBIU_DMA_REQUEST_FIFO_STARVED"/> + <value value="26" name="RBIU_DMA_REQUEST_FIFO_STALLED"/> + <value value="27" name="RBIU_DRAW_INITIATOR_FIFO_STARVED"/> + <value value="28" name="RBIU_DRAW_INITIATOR_FIFO_STALLED"/> + <value value="29" name="BIN_PRIM_NEAR_CULL"/> + <value value="30" name="BIN_PRIM_ZERO_CULL"/> + <value value="31" name="BIN_PRIM_FAR_CULL"/> + <value value="32" name="BIN_PRIM_BIN_CULL"/> + <value value="33" name="BIN_PRIM_FACE_CULL"/> + <value value="34" name="SPARE34"/> + <value value="35" name="SPARE35"/> + <value value="36" name="SPARE36"/> + <value value="37" name="SPARE37"/> + <value value="38" name="SPARE38"/> + <value value="39" name="SPARE39"/> + <value value="40" name="TE_SU_IN_VALID"/> + <value value="41" name="TE_SU_IN_READ"/> + <value value="42" name="TE_SU_IN_PRIM"/> + <value value="43" name="TE_SU_IN_EOP"/> + <value value="44" name="TE_SU_IN_NULL_PRIM"/> + <value value="45" name="TE_WK_IN_VALID"/> + <value value="46" name="TE_WK_IN_READ"/> + <value value="47" name="TE_OUT_PRIM_VALID"/> + <value value="48" name="TE_OUT_PRIM_READ"/> +</enum> + +<enum name="a2xx_tcr_perfcount_select"> + <value value="0" name="DGMMPD_IPMUX0_STALL"/> + <value value="4" name="DGMMPD_IPMUX_ALL_STALL"/> + <value value="5" name="OPMUX0_L2_WRITES"/> +</enum> + +<enum name="a2xx_tp_perfcount_select"> + <value value="0" name="POINT_QUADS"/> + <value value="1" name="BILIN_QUADS"/> + <value value="2" name="ANISO_QUADS"/> + <value value="3" name="MIP_QUADS"/> + <value value="4" name="VOL_QUADS"/> + <value value="5" name="MIP_VOL_QUADS"/> + <value value="6" name="MIP_ANISO_QUADS"/> + <value value="7" name="VOL_ANISO_QUADS"/> + <value value="8" name="ANISO_2_1_QUADS"/> + <value value="9" name="ANISO_4_1_QUADS"/> + <value value="10" name="ANISO_6_1_QUADS"/> + <value value="11" name="ANISO_8_1_QUADS"/> + <value value="12" name="ANISO_10_1_QUADS"/> + <value value="13" name="ANISO_12_1_QUADS"/> + <value value="14" name="ANISO_14_1_QUADS"/> + <value value="15" name="ANISO_16_1_QUADS"/> + <value value="16" name="MIP_VOL_ANISO_QUADS"/> + <value value="17" name="ALIGN_2_QUADS"/> + <value value="18" name="ALIGN_4_QUADS"/> + <value value="19" name="PIX_0_QUAD"/> + <value value="20" name="PIX_1_QUAD"/> + <value value="21" name="PIX_2_QUAD"/> + <value value="22" name="PIX_3_QUAD"/> + <value value="23" name="PIX_4_QUAD"/> + <value value="24" name="TP_MIPMAP_LOD0"/> + <value value="25" name="TP_MIPMAP_LOD1"/> + <value value="26" name="TP_MIPMAP_LOD2"/> + <value value="27" name="TP_MIPMAP_LOD3"/> + <value value="28" name="TP_MIPMAP_LOD4"/> + <value value="29" name="TP_MIPMAP_LOD5"/> + <value value="30" name="TP_MIPMAP_LOD6"/> + <value value="31" name="TP_MIPMAP_LOD7"/> + <value value="32" name="TP_MIPMAP_LOD8"/> + <value value="33" name="TP_MIPMAP_LOD9"/> + <value value="34" name="TP_MIPMAP_LOD10"/> + <value value="35" name="TP_MIPMAP_LOD11"/> + <value value="36" name="TP_MIPMAP_LOD12"/> + <value value="37" name="TP_MIPMAP_LOD13"/> + <value value="38" name="TP_MIPMAP_LOD14"/> +</enum> + +<enum name="a2xx_tcm_perfcount_select"> + <value value="0" name="QUAD0_RD_LAT_FIFO_EMPTY"/> + <value value="3" name="QUAD0_RD_LAT_FIFO_4TH_FULL"/> + <value value="4" name="QUAD0_RD_LAT_FIFO_HALF_FULL"/> + <value value="5" name="QUAD0_RD_LAT_FIFO_FULL"/> + <value value="6" name="QUAD0_RD_LAT_FIFO_LT_4TH_FULL"/> + <value value="28" name="READ_STARVED_QUAD0"/> + <value value="32" name="READ_STARVED"/> + <value value="33" name="READ_STALLED_QUAD0"/> + <value value="37" name="READ_STALLED"/> + <value value="38" name="VALID_READ_QUAD0"/> + <value value="42" name="TC_TP_STARVED_QUAD0"/> + <value value="46" name="TC_TP_STARVED"/> +</enum> + +<enum name="a2xx_tcf_perfcount_select"> + <value value="0" name="VALID_CYCLES"/> + <value value="1" name="SINGLE_PHASES"/> + <value value="2" name="ANISO_PHASES"/> + <value value="3" name="MIP_PHASES"/> + <value value="4" name="VOL_PHASES"/> + <value value="5" name="MIP_VOL_PHASES"/> + <value value="6" name="MIP_ANISO_PHASES"/> + <value value="7" name="VOL_ANISO_PHASES"/> + <value value="8" name="ANISO_2_1_PHASES"/> + <value value="9" name="ANISO_4_1_PHASES"/> + <value value="10" name="ANISO_6_1_PHASES"/> + <value value="11" name="ANISO_8_1_PHASES"/> + <value value="12" name="ANISO_10_1_PHASES"/> + <value value="13" name="ANISO_12_1_PHASES"/> + <value value="14" name="ANISO_14_1_PHASES"/> + <value value="15" name="ANISO_16_1_PHASES"/> + <value value="16" name="MIP_VOL_ANISO_PHASES"/> + <value value="17" name="ALIGN_2_PHASES"/> + <value value="18" name="ALIGN_4_PHASES"/> + <value value="19" name="TPC_BUSY"/> + <value value="20" name="TPC_STALLED"/> + <value value="21" name="TPC_STARVED"/> + <value value="22" name="TPC_WORKING"/> + <value value="23" name="TPC_WALKER_BUSY"/> + <value value="24" name="TPC_WALKER_STALLED"/> + <value value="25" name="TPC_WALKER_WORKING"/> + <value value="26" name="TPC_ALIGNER_BUSY"/> + <value value="27" name="TPC_ALIGNER_STALLED"/> + <value value="28" name="TPC_ALIGNER_STALLED_BY_BLEND"/> + <value value="29" name="TPC_ALIGNER_STALLED_BY_CACHE"/> + <value value="30" name="TPC_ALIGNER_WORKING"/> + <value value="31" name="TPC_BLEND_BUSY"/> + <value value="32" name="TPC_BLEND_SYNC"/> + <value value="33" name="TPC_BLEND_STARVED"/> + <value value="34" name="TPC_BLEND_WORKING"/> + <value value="35" name="OPCODE_0x00"/> + <value value="36" name="OPCODE_0x01"/> + <value value="37" name="OPCODE_0x04"/> + <value value="38" name="OPCODE_0x10"/> + <value value="39" name="OPCODE_0x11"/> + <value value="40" name="OPCODE_0x12"/> + <value value="41" name="OPCODE_0x13"/> + <value value="42" name="OPCODE_0x18"/> + <value value="43" name="OPCODE_0x19"/> + <value value="44" name="OPCODE_0x1A"/> + <value value="45" name="OPCODE_OTHER"/> + <value value="56" name="IN_FIFO_0_EMPTY"/> + <value value="57" name="IN_FIFO_0_LT_HALF_FULL"/> + <value value="58" name="IN_FIFO_0_HALF_FULL"/> + <value value="59" name="IN_FIFO_0_FULL"/> + <value value="72" name="IN_FIFO_TPC_EMPTY"/> + <value value="73" name="IN_FIFO_TPC_LT_HALF_FULL"/> + <value value="74" name="IN_FIFO_TPC_HALF_FULL"/> + <value value="75" name="IN_FIFO_TPC_FULL"/> + <value value="76" name="TPC_TC_XFC"/> + <value value="77" name="TPC_TC_STATE"/> + <value value="78" name="TC_STALL"/> + <value value="79" name="QUAD0_TAPS"/> + <value value="83" name="QUADS"/> + <value value="84" name="TCA_SYNC_STALL"/> + <value value="85" name="TAG_STALL"/> + <value value="88" name="TCB_SYNC_STALL"/> + <value value="89" name="TCA_VALID"/> + <value value="90" name="PROBES_VALID"/> + <value value="91" name="MISS_STALL"/> + <value value="92" name="FETCH_FIFO_STALL"/> + <value value="93" name="TCO_STALL"/> + <value value="94" name="ANY_STALL"/> + <value value="95" name="TAG_MISSES"/> + <value value="96" name="TAG_HITS"/> + <value value="97" name="SUB_TAG_MISSES"/> + <value value="98" name="SET0_INVALIDATES"/> + <value value="99" name="SET1_INVALIDATES"/> + <value value="100" name="SET2_INVALIDATES"/> + <value value="101" name="SET3_INVALIDATES"/> + <value value="102" name="SET0_TAG_MISSES"/> + <value value="103" name="SET1_TAG_MISSES"/> + <value value="104" name="SET2_TAG_MISSES"/> + <value value="105" name="SET3_TAG_MISSES"/> + <value value="106" name="SET0_TAG_HITS"/> + <value value="107" name="SET1_TAG_HITS"/> + <value value="108" name="SET2_TAG_HITS"/> + <value value="109" name="SET3_TAG_HITS"/> + <value value="110" name="SET0_SUB_TAG_MISSES"/> + <value value="111" name="SET1_SUB_TAG_MISSES"/> + <value value="112" name="SET2_SUB_TAG_MISSES"/> + <value value="113" name="SET3_SUB_TAG_MISSES"/> + <value value="114" name="SET0_EVICT1"/> + <value value="115" name="SET0_EVICT2"/> + <value value="116" name="SET0_EVICT3"/> + <value value="117" name="SET0_EVICT4"/> + <value value="118" name="SET0_EVICT5"/> + <value value="119" name="SET0_EVICT6"/> + <value value="120" name="SET0_EVICT7"/> + <value value="121" name="SET0_EVICT8"/> + <value value="130" name="SET1_EVICT1"/> + <value value="131" name="SET1_EVICT2"/> + <value value="132" name="SET1_EVICT3"/> + <value value="133" name="SET1_EVICT4"/> + <value value="134" name="SET1_EVICT5"/> + <value value="135" name="SET1_EVICT6"/> + <value value="136" name="SET1_EVICT7"/> + <value value="137" name="SET1_EVICT8"/> + <value value="146" name="SET2_EVICT1"/> + <value value="147" name="SET2_EVICT2"/> + <value value="148" name="SET2_EVICT3"/> + <value value="149" name="SET2_EVICT4"/> + <value value="150" name="SET2_EVICT5"/> + <value value="151" name="SET2_EVICT6"/> + <value value="152" name="SET2_EVICT7"/> + <value value="153" name="SET2_EVICT8"/> + <value value="162" name="SET3_EVICT1"/> + <value value="163" name="SET3_EVICT2"/> + <value value="164" name="SET3_EVICT3"/> + <value value="165" name="SET3_EVICT4"/> + <value value="166" name="SET3_EVICT5"/> + <value value="167" name="SET3_EVICT6"/> + <value value="168" name="SET3_EVICT7"/> + <value value="169" name="SET3_EVICT8"/> + <value value="178" name="FF_EMPTY"/> + <value value="179" name="FF_LT_HALF_FULL"/> + <value value="180" name="FF_HALF_FULL"/> + <value value="181" name="FF_FULL"/> + <value value="182" name="FF_XFC"/> + <value value="183" name="FF_STALLED"/> + <value value="184" name="FG_MASKS"/> + <value value="185" name="FG_LEFT_MASKS"/> + <value value="186" name="FG_LEFT_MASK_STALLED"/> + <value value="187" name="FG_LEFT_NOT_DONE_STALL"/> + <value value="188" name="FG_LEFT_FG_STALL"/> + <value value="189" name="FG_LEFT_SECTORS"/> + <value value="195" name="FG0_REQUESTS"/> + <value value="196" name="FG0_STALLED"/> + <value value="199" name="MEM_REQ512"/> + <value value="200" name="MEM_REQ_SENT"/> + <value value="202" name="MEM_LOCAL_READ_REQ"/> + <value value="203" name="TC0_MH_STALLED"/> +</enum> + +<enum name="a2xx_sq_perfcnt_select"> + <value value="0" name="SQ_PIXEL_VECTORS_SUB"/> + <value value="1" name="SQ_VERTEX_VECTORS_SUB"/> + <value value="2" name="SQ_ALU0_ACTIVE_VTX_SIMD0"/> + <value value="3" name="SQ_ALU1_ACTIVE_VTX_SIMD0"/> + <value value="4" name="SQ_ALU0_ACTIVE_PIX_SIMD0"/> + <value value="5" name="SQ_ALU1_ACTIVE_PIX_SIMD0"/> + <value value="6" name="SQ_ALU0_ACTIVE_VTX_SIMD1"/> + <value value="7" name="SQ_ALU1_ACTIVE_VTX_SIMD1"/> + <value value="8" name="SQ_ALU0_ACTIVE_PIX_SIMD1"/> + <value value="9" name="SQ_ALU1_ACTIVE_PIX_SIMD1"/> + <value value="10" name="SQ_EXPORT_CYCLES"/> + <value value="11" name="SQ_ALU_CST_WRITTEN"/> + <value value="12" name="SQ_TEX_CST_WRITTEN"/> + <value value="13" name="SQ_ALU_CST_STALL"/> + <value value="14" name="SQ_ALU_TEX_STALL"/> + <value value="15" name="SQ_INST_WRITTEN"/> + <value value="16" name="SQ_BOOLEAN_WRITTEN"/> + <value value="17" name="SQ_LOOPS_WRITTEN"/> + <value value="18" name="SQ_PIXEL_SWAP_IN"/> + <value value="19" name="SQ_PIXEL_SWAP_OUT"/> + <value value="20" name="SQ_VERTEX_SWAP_IN"/> + <value value="21" name="SQ_VERTEX_SWAP_OUT"/> + <value value="22" name="SQ_ALU_VTX_INST_ISSUED"/> + <value value="23" name="SQ_TEX_VTX_INST_ISSUED"/> + <value value="24" name="SQ_VC_VTX_INST_ISSUED"/> + <value value="25" name="SQ_CF_VTX_INST_ISSUED"/> + <value value="26" name="SQ_ALU_PIX_INST_ISSUED"/> + <value value="27" name="SQ_TEX_PIX_INST_ISSUED"/> + <value value="28" name="SQ_VC_PIX_INST_ISSUED"/> + <value value="29" name="SQ_CF_PIX_INST_ISSUED"/> + <value value="30" name="SQ_ALU0_FIFO_EMPTY_SIMD0"/> + <value value="31" name="SQ_ALU1_FIFO_EMPTY_SIMD0"/> + <value value="32" name="SQ_ALU0_FIFO_EMPTY_SIMD1"/> + <value value="33" name="SQ_ALU1_FIFO_EMPTY_SIMD1"/> + <value value="34" name="SQ_ALU_NOPS"/> + <value value="35" name="SQ_PRED_SKIP"/> + <value value="36" name="SQ_SYNC_ALU_STALL_SIMD0_VTX"/> + <value value="37" name="SQ_SYNC_ALU_STALL_SIMD1_VTX"/> + <value value="38" name="SQ_SYNC_TEX_STALL_VTX"/> + <value value="39" name="SQ_SYNC_VC_STALL_VTX"/> + <value value="40" name="SQ_CONSTANTS_USED_SIMD0"/> + <value value="41" name="SQ_CONSTANTS_SENT_SP_SIMD0"/> + <value value="42" name="SQ_GPR_STALL_VTX"/> + <value value="43" name="SQ_GPR_STALL_PIX"/> + <value value="44" name="SQ_VTX_RS_STALL"/> + <value value="45" name="SQ_PIX_RS_STALL"/> + <value value="46" name="SQ_SX_PC_FULL"/> + <value value="47" name="SQ_SX_EXP_BUFF_FULL"/> + <value value="48" name="SQ_SX_POS_BUFF_FULL"/> + <value value="49" name="SQ_INTERP_QUADS"/> + <value value="50" name="SQ_INTERP_ACTIVE"/> + <value value="51" name="SQ_IN_PIXEL_STALL"/> + <value value="52" name="SQ_IN_VTX_STALL"/> + <value value="53" name="SQ_VTX_CNT"/> + <value value="54" name="SQ_VTX_VECTOR2"/> + <value value="55" name="SQ_VTX_VECTOR3"/> + <value value="56" name="SQ_VTX_VECTOR4"/> + <value value="57" name="SQ_PIXEL_VECTOR1"/> + <value value="58" name="SQ_PIXEL_VECTOR23"/> + <value value="59" name="SQ_PIXEL_VECTOR4"/> + <value value="60" name="SQ_CONSTANTS_USED_SIMD1"/> + <value value="61" name="SQ_CONSTANTS_SENT_SP_SIMD1"/> + <value value="62" name="SQ_SX_MEM_EXP_FULL"/> + <value value="63" name="SQ_ALU0_ACTIVE_VTX_SIMD2"/> + <value value="64" name="SQ_ALU1_ACTIVE_VTX_SIMD2"/> + <value value="65" name="SQ_ALU0_ACTIVE_PIX_SIMD2"/> + <value value="66" name="SQ_ALU1_ACTIVE_PIX_SIMD2"/> + <value value="67" name="SQ_ALU0_ACTIVE_VTX_SIMD3"/> + <value value="68" name="SQ_PERFCOUNT_VTX_QUAL_TP_DONE"/> + <value value="69" name="SQ_ALU0_ACTIVE_PIX_SIMD3"/> + <value value="70" name="SQ_PERFCOUNT_PIX_QUAL_TP_DONE"/> + <value value="71" name="SQ_ALU0_FIFO_EMPTY_SIMD2"/> + <value value="72" name="SQ_ALU1_FIFO_EMPTY_SIMD2"/> + <value value="73" name="SQ_ALU0_FIFO_EMPTY_SIMD3"/> + <value value="74" name="SQ_ALU1_FIFO_EMPTY_SIMD3"/> + <value value="75" name="SQ_SYNC_ALU_STALL_SIMD2_VTX"/> + <value value="76" name="SQ_PERFCOUNT_VTX_POP_THREAD"/> + <value value="77" name="SQ_SYNC_ALU_STALL_SIMD0_PIX"/> + <value value="78" name="SQ_SYNC_ALU_STALL_SIMD1_PIX"/> + <value value="79" name="SQ_SYNC_ALU_STALL_SIMD2_PIX"/> + <value value="80" name="SQ_PERFCOUNT_PIX_POP_THREAD"/> + <value value="81" name="SQ_SYNC_TEX_STALL_PIX"/> + <value value="82" name="SQ_SYNC_VC_STALL_PIX"/> + <value value="83" name="SQ_CONSTANTS_USED_SIMD2"/> + <value value="84" name="SQ_CONSTANTS_SENT_SP_SIMD2"/> + <value value="85" name="SQ_PERFCOUNT_VTX_DEALLOC_ACK"/> + <value value="86" name="SQ_PERFCOUNT_PIX_DEALLOC_ACK"/> + <value value="87" name="SQ_ALU0_FIFO_FULL_SIMD0"/> + <value value="88" name="SQ_ALU1_FIFO_FULL_SIMD0"/> + <value value="89" name="SQ_ALU0_FIFO_FULL_SIMD1"/> + <value value="90" name="SQ_ALU1_FIFO_FULL_SIMD1"/> + <value value="91" name="SQ_ALU0_FIFO_FULL_SIMD2"/> + <value value="92" name="SQ_ALU1_FIFO_FULL_SIMD2"/> + <value value="93" name="SQ_ALU0_FIFO_FULL_SIMD3"/> + <value value="94" name="SQ_ALU1_FIFO_FULL_SIMD3"/> + <value value="95" name="VC_PERF_STATIC"/> + <value value="96" name="VC_PERF_STALLED"/> + <value value="97" name="VC_PERF_STARVED"/> + <value value="98" name="VC_PERF_SEND"/> + <value value="99" name="VC_PERF_ACTUAL_STARVED"/> + <value value="100" name="PIXEL_THREAD_0_ACTIVE"/> + <value value="101" name="VERTEX_THREAD_0_ACTIVE"/> + <value value="102" name="PIXEL_THREAD_0_NUMBER"/> + <value value="103" name="VERTEX_THREAD_0_NUMBER"/> + <value value="104" name="VERTEX_EVENT_NUMBER"/> + <value value="105" name="PIXEL_EVENT_NUMBER"/> + <value value="106" name="PTRBUFF_EF_PUSH"/> + <value value="107" name="PTRBUFF_EF_POP_EVENT"/> + <value value="108" name="PTRBUFF_EF_POP_NEW_VTX"/> + <value value="109" name="PTRBUFF_EF_POP_DEALLOC"/> + <value value="110" name="PTRBUFF_EF_POP_PVECTOR"/> + <value value="111" name="PTRBUFF_EF_POP_PVECTOR_X"/> + <value value="112" name="PTRBUFF_EF_POP_PVECTOR_VNZ"/> + <value value="113" name="PTRBUFF_PB_DEALLOC"/> + <value value="114" name="PTRBUFF_PI_STATE_PPB_POP"/> + <value value="115" name="PTRBUFF_PI_RTR"/> + <value value="116" name="PTRBUFF_PI_READ_EN"/> + <value value="117" name="PTRBUFF_PI_BUFF_SWAP"/> + <value value="118" name="PTRBUFF_SQ_FREE_BUFF"/> + <value value="119" name="PTRBUFF_SQ_DEC"/> + <value value="120" name="PTRBUFF_SC_VALID_CNTL_EVENT"/> + <value value="121" name="PTRBUFF_SC_VALID_IJ_XFER"/> + <value value="122" name="PTRBUFF_SC_NEW_VECTOR_1_Q"/> + <value value="123" name="PTRBUFF_QUAL_NEW_VECTOR"/> + <value value="124" name="PTRBUFF_QUAL_EVENT"/> + <value value="125" name="PTRBUFF_END_BUFFER"/> + <value value="126" name="PTRBUFF_FILL_QUAD"/> + <value value="127" name="VERTS_WRITTEN_SPI"/> + <value value="128" name="TP_FETCH_INSTR_EXEC"/> + <value value="129" name="TP_FETCH_INSTR_REQ"/> + <value value="130" name="TP_DATA_RETURN"/> + <value value="131" name="SPI_WRITE_CYCLES_SP"/> + <value value="132" name="SPI_WRITES_SP"/> + <value value="133" name="SP_ALU_INSTR_EXEC"/> + <value value="134" name="SP_CONST_ADDR_TO_SQ"/> + <value value="135" name="SP_PRED_KILLS_TO_SQ"/> + <value value="136" name="SP_EXPORT_CYCLES_TO_SX"/> + <value value="137" name="SP_EXPORTS_TO_SX"/> + <value value="138" name="SQ_CYCLES_ELAPSED"/> + <value value="139" name="SQ_TCFS_OPT_ALLOC_EXEC"/> + <value value="140" name="SQ_TCFS_NO_OPT_ALLOC"/> + <value value="141" name="SQ_ALU0_NO_OPT_ALLOC"/> + <value value="142" name="SQ_ALU1_NO_OPT_ALLOC"/> + <value value="143" name="SQ_TCFS_ARB_XFC_CNT"/> + <value value="144" name="SQ_ALU0_ARB_XFC_CNT"/> + <value value="145" name="SQ_ALU1_ARB_XFC_CNT"/> + <value value="146" name="SQ_TCFS_CFS_UPDATE_CNT"/> + <value value="147" name="SQ_ALU0_CFS_UPDATE_CNT"/> + <value value="148" name="SQ_ALU1_CFS_UPDATE_CNT"/> + <value value="149" name="SQ_VTX_PUSH_THREAD_CNT"/> + <value value="150" name="SQ_VTX_POP_THREAD_CNT"/> + <value value="151" name="SQ_PIX_PUSH_THREAD_CNT"/> + <value value="152" name="SQ_PIX_POP_THREAD_CNT"/> + <value value="153" name="SQ_PIX_TOTAL"/> + <value value="154" name="SQ_PIX_KILLED"/> +</enum> + +<enum name="a2xx_sx_perfcnt_select"> + <value value="0" name="SX_EXPORT_VECTORS"/> + <value value="1" name="SX_DUMMY_QUADS"/> + <value value="2" name="SX_ALPHA_FAIL"/> + <value value="3" name="SX_RB_QUAD_BUSY"/> + <value value="4" name="SX_RB_COLOR_BUSY"/> + <value value="5" name="SX_RB_QUAD_STALL"/> + <value value="6" name="SX_RB_COLOR_STALL"/> +</enum> + +<enum name="a2xx_rbbm_perfcount1_sel"> + <value value="0" name="RBBM1_COUNT"/> + <value value="1" name="RBBM1_NRT_BUSY"/> + <value value="2" name="RBBM1_RB_BUSY"/> + <value value="3" name="RBBM1_SQ_CNTX0_BUSY"/> + <value value="4" name="RBBM1_SQ_CNTX17_BUSY"/> + <value value="5" name="RBBM1_VGT_BUSY"/> + <value value="6" name="RBBM1_VGT_NODMA_BUSY"/> + <value value="7" name="RBBM1_PA_BUSY"/> + <value value="8" name="RBBM1_SC_CNTX_BUSY"/> + <value value="9" name="RBBM1_TPC_BUSY"/> + <value value="10" name="RBBM1_TC_BUSY"/> + <value value="11" name="RBBM1_SX_BUSY"/> + <value value="12" name="RBBM1_CP_COHER_BUSY"/> + <value value="13" name="RBBM1_CP_NRT_BUSY"/> + <value value="14" name="RBBM1_GFX_IDLE_STALL"/> + <value value="15" name="RBBM1_INTERRUPT"/> +</enum> + +<enum name="a2xx_cp_perfcount_sel"> + <value value="0" name="ALWAYS_COUNT"/> + <value value="1" name="TRANS_FIFO_FULL"/> + <value value="2" name="TRANS_FIFO_AF"/> + <value value="3" name="RCIU_PFPTRANS_WAIT"/> + <value value="6" name="RCIU_NRTTRANS_WAIT"/> + <value value="8" name="CSF_NRT_READ_WAIT"/> + <value value="9" name="CSF_I1_FIFO_FULL"/> + <value value="10" name="CSF_I2_FIFO_FULL"/> + <value value="11" name="CSF_ST_FIFO_FULL"/> + <value value="13" name="CSF_RING_ROQ_FULL"/> + <value value="14" name="CSF_I1_ROQ_FULL"/> + <value value="15" name="CSF_I2_ROQ_FULL"/> + <value value="16" name="CSF_ST_ROQ_FULL"/> + <value value="18" name="MIU_TAG_MEM_FULL"/> + <value value="19" name="MIU_WRITECLEAN"/> + <value value="22" name="MIU_NRT_WRITE_STALLED"/> + <value value="23" name="MIU_NRT_READ_STALLED"/> + <value value="24" name="ME_WRITE_CONFIRM_FIFO_FULL"/> + <value value="25" name="ME_VS_DEALLOC_FIFO_FULL"/> + <value value="26" name="ME_PS_DEALLOC_FIFO_FULL"/> + <value value="27" name="ME_REGS_VS_EVENT_FIFO_FULL"/> + <value value="28" name="ME_REGS_PS_EVENT_FIFO_FULL"/> + <value value="29" name="ME_REGS_CF_EVENT_FIFO_FULL"/> + <value value="30" name="ME_MICRO_RB_STARVED"/> + <value value="31" name="ME_MICRO_I1_STARVED"/> + <value value="32" name="ME_MICRO_I2_STARVED"/> + <value value="33" name="ME_MICRO_ST_STARVED"/> + <value value="40" name="RCIU_RBBM_DWORD_SENT"/> + <value value="41" name="ME_BUSY_CLOCKS"/> + <value value="42" name="ME_WAIT_CONTEXT_AVAIL"/> + <value value="43" name="PFP_TYPE0_PACKET"/> + <value value="44" name="PFP_TYPE3_PACKET"/> + <value value="45" name="CSF_RB_WPTR_NEQ_RPTR"/> + <value value="46" name="CSF_I1_SIZE_NEQ_ZERO"/> + <value value="47" name="CSF_I2_SIZE_NEQ_ZERO"/> + <value value="48" name="CSF_RBI1I2_FETCHING"/> +</enum> + +<enum name="a2xx_rb_perfcnt_select"> + <value value="0" name="RBPERF_CNTX_BUSY"/> + <value value="1" name="RBPERF_CNTX_BUSY_MAX"/> + <value value="2" name="RBPERF_SX_QUAD_STARVED"/> + <value value="3" name="RBPERF_SX_QUAD_STARVED_MAX"/> + <value value="4" name="RBPERF_GA_GC_CH0_SYS_REQ"/> + <value value="5" name="RBPERF_GA_GC_CH0_SYS_REQ_MAX"/> + <value value="6" name="RBPERF_GA_GC_CH1_SYS_REQ"/> + <value value="7" name="RBPERF_GA_GC_CH1_SYS_REQ_MAX"/> + <value value="8" name="RBPERF_MH_STARVED"/> + <value value="9" name="RBPERF_MH_STARVED_MAX"/> + <value value="10" name="RBPERF_AZ_BC_COLOR_BUSY"/> + <value value="11" name="RBPERF_AZ_BC_COLOR_BUSY_MAX"/> + <value value="12" name="RBPERF_AZ_BC_Z_BUSY"/> + <value value="13" name="RBPERF_AZ_BC_Z_BUSY_MAX"/> + <value value="14" name="RBPERF_RB_SC_TILE_RTR_N"/> + <value value="15" name="RBPERF_RB_SC_TILE_RTR_N_MAX"/> + <value value="16" name="RBPERF_RB_SC_SAMP_RTR_N"/> + <value value="17" name="RBPERF_RB_SC_SAMP_RTR_N_MAX"/> + <value value="18" name="RBPERF_RB_SX_QUAD_RTR_N"/> + <value value="19" name="RBPERF_RB_SX_QUAD_RTR_N_MAX"/> + <value value="20" name="RBPERF_RB_SX_COLOR_RTR_N"/> + <value value="21" name="RBPERF_RB_SX_COLOR_RTR_N_MAX"/> + <value value="22" name="RBPERF_RB_SC_SAMP_LZ_BUSY"/> + <value value="23" name="RBPERF_RB_SC_SAMP_LZ_BUSY_MAX"/> + <value value="24" name="RBPERF_ZXP_STALL"/> + <value value="25" name="RBPERF_ZXP_STALL_MAX"/> + <value value="26" name="RBPERF_EVENT_PENDING"/> + <value value="27" name="RBPERF_EVENT_PENDING_MAX"/> + <value value="28" name="RBPERF_RB_MH_VALID"/> + <value value="29" name="RBPERF_RB_MH_VALID_MAX"/> + <value value="30" name="RBPERF_SX_RB_QUAD_SEND"/> + <value value="31" name="RBPERF_SX_RB_COLOR_SEND"/> + <value value="32" name="RBPERF_SC_RB_TILE_SEND"/> + <value value="33" name="RBPERF_SC_RB_SAMPLE_SEND"/> + <value value="34" name="RBPERF_SX_RB_MEM_EXPORT"/> + <value value="35" name="RBPERF_SX_RB_QUAD_EVENT"/> + <value value="36" name="RBPERF_SC_RB_TILE_EVENT_FILTERED"/> + <value value="37" name="RBPERF_SC_RB_TILE_EVENT_ALL"/> + <value value="38" name="RBPERF_RB_SC_EZ_SEND"/> + <value value="39" name="RBPERF_RB_SX_INDEX_SEND"/> + <value value="40" name="RBPERF_GMEM_INTFO_RD"/> + <value value="41" name="RBPERF_GMEM_INTF1_RD"/> + <value value="42" name="RBPERF_GMEM_INTFO_WR"/> + <value value="43" name="RBPERF_GMEM_INTF1_WR"/> + <value value="44" name="RBPERF_RB_CP_CONTEXT_DONE"/> + <value value="45" name="RBPERF_RB_CP_CACHE_FLUSH"/> + <value value="46" name="RBPERF_ZPASS_DONE"/> + <value value="47" name="RBPERF_ZCMD_VALID"/> + <value value="48" name="RBPERF_CCMD_VALID"/> + <value value="49" name="RBPERF_ACCUM_GRANT"/> + <value value="50" name="RBPERF_ACCUM_C0_GRANT"/> + <value value="51" name="RBPERF_ACCUM_C1_GRANT"/> + <value value="52" name="RBPERF_ACCUM_FULL_BE_WR"/> + <value value="53" name="RBPERF_ACCUM_REQUEST_NO_GRANT"/> + <value value="54" name="RBPERF_ACCUM_TIMEOUT_PULSE"/> + <value value="55" name="RBPERF_ACCUM_LIN_TIMEOUT_PULSE"/> + <value value="56" name="RBPERF_ACCUM_CAM_HIT_FLUSHING"/> +</enum> + +<domain name="A2XX" width="32"> + + <bitset name="a2xx_vgt_current_bin_id_min_max" inline="yes"> + <bitfield name="COLUMN" low="0" high="2" type="uint"/> + <bitfield name="ROW" low="3" high="5" type="uint"/> + <bitfield name="GUARD_BAND_MASK" low="6" high="8" type="uint"/> + </bitset> + + <reg32 offset="0x0001" name="RBBM_PATCH_RELEASE"/> + <reg32 offset="0x003b" name="RBBM_CNTL"/> + <reg32 offset="0x003c" name="RBBM_SOFT_RESET"/> + <reg32 offset="0x00c0" name="CP_PFP_UCODE_ADDR"/> + <reg32 offset="0x00c1" name="CP_PFP_UCODE_DATA"/> + + <enum name="adreno_mmu_clnt_beh"> + <value name="BEH_NEVR" value="0"/> + <value name="BEH_TRAN_RNG" value="1"/> + <value name="BEH_TRAN_FLT" value="2"/> + </enum> + + <!-- + Note: these seem applicable only for a2xx devices with gpummu? At + any rate, MH_MMU_CONFIG shows up in places in a3xx firmware where + it doesn't make sense, so I think offset 0x40 must be a different + register on a3xx.. so moving this back into A2XX domain: + --> + <reg32 offset="0x0040" name="MH_MMU_CONFIG"> + <bitfield name="MMU_ENABLE" pos="0" type="boolean"/> + <bitfield name="SPLIT_MODE_ENABLE" pos="1" type="boolean"/> + <bitfield name="RB_W_CLNT_BEHAVIOR" low="4" high="5" type="adreno_mmu_clnt_beh"/> + <bitfield name="CP_W_CLNT_BEHAVIOR" low="6" high="7" type="adreno_mmu_clnt_beh"/> + <bitfield name="CP_R0_CLNT_BEHAVIOR" low="8" high="9" type="adreno_mmu_clnt_beh"/> + <bitfield name="CP_R1_CLNT_BEHAVIOR" low="10" high="11" type="adreno_mmu_clnt_beh"/> + <bitfield name="CP_R2_CLNT_BEHAVIOR" low="12" high="13" type="adreno_mmu_clnt_beh"/> + <bitfield name="CP_R3_CLNT_BEHAVIOR" low="14" high="15" type="adreno_mmu_clnt_beh"/> + <bitfield name="CP_R4_CLNT_BEHAVIOR" low="16" high="17" type="adreno_mmu_clnt_beh"/> + <bitfield name="VGT_R0_CLNT_BEHAVIOR" low="18" high="19" type="adreno_mmu_clnt_beh"/> + <bitfield name="VGT_R1_CLNT_BEHAVIOR" low="20" high="21" type="adreno_mmu_clnt_beh"/> + <bitfield name="TC_R_CLNT_BEHAVIOR" low="22" high="23" type="adreno_mmu_clnt_beh"/> + <bitfield name="PA_W_CLNT_BEHAVIOR" low="24" high="25" type="adreno_mmu_clnt_beh"/> + </reg32> + <reg32 offset="0x0041" name="MH_MMU_VA_RANGE"> + <bitfield name="NUM_64KB_REGIONS" low="0" high="11" type="uint"/> + <bitfield name="VA_BASE" low="12" high="31" type="uint"/> + </reg32> + <reg32 offset="0x0042" name="MH_MMU_PT_BASE"/> + <reg32 offset="0x0043" name="MH_MMU_PAGE_FAULT"/> + <reg32 offset="0x0044" name="MH_MMU_TRAN_ERROR"/> + <reg32 offset="0x0045" name="MH_MMU_INVALIDATE"> + <bitfield name="INVALIDATE_ALL" pos="0"/> + <bitfield name="INVALIDATE_TC" pos="1"/> + </reg32> + <reg32 offset="0x0046" name="MH_MMU_MPU_BASE"/> + <reg32 offset="0x0047" name="MH_MMU_MPU_END"/> + + <reg32 offset="0x0394" name="NQWAIT_UNTIL"/> + <reg32 offset="0x0395" name="RBBM_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0397" name="RBBM_PERFCOUNTER1_LO"/> + <reg32 offset="0x0398" name="RBBM_PERFCOUNTER1_HI"/> + <reg32 offset="0x039b" name="RBBM_DEBUG"/> + <reg32 offset="0x039c" name="RBBM_PM_OVERRIDE1"> + <bitfield name="RBBM_AHBCLK_PM_OVERRIDE" pos="0"/> + <bitfield name="SC_REG_SCLK_PM_OVERRIDE" pos="1"/> + <bitfield name="SC_SCLK_PM_OVERRIDE" pos="2"/> + <bitfield name="SP_TOP_SCLK_PM_OVERRIDE" pos="3"/> + <bitfield name="SP_V0_SCLK_PM_OVERRIDE" pos="4"/> + <bitfield name="SQ_REG_SCLK_PM_OVERRIDE" pos="5"/> + <bitfield name="SQ_REG_FIFOS_SCLK_PM_OVERRIDE" pos="6"/> + <bitfield name="SQ_CONST_MEM_SCLK_PM_OVERRIDE" pos="7"/> + <bitfield name="SQ_SQ_SCLK_PM_OVERRIDE" pos="8"/> + <bitfield name="SX_SCLK_PM_OVERRIDE" pos="9"/> + <bitfield name="SX_REG_SCLK_PM_OVERRIDE" pos="10"/> + <bitfield name="TCM_TCO_SCLK_PM_OVERRIDE" pos="11"/> + <bitfield name="TCM_TCM_SCLK_PM_OVERRIDE" pos="12"/> + <bitfield name="TCM_TCD_SCLK_PM_OVERRIDE" pos="13"/> + <bitfield name="TCM_REG_SCLK_PM_OVERRIDE" pos="14"/> + <bitfield name="TPC_TPC_SCLK_PM_OVERRIDE" pos="15"/> + <bitfield name="TPC_REG_SCLK_PM_OVERRIDE" pos="16"/> + <bitfield name="TCF_TCA_SCLK_PM_OVERRIDE" pos="17"/> + <bitfield name="TCF_TCB_SCLK_PM_OVERRIDE" pos="18"/> + <bitfield name="TCF_TCB_READ_SCLK_PM_OVERRIDE" pos="19"/> + <bitfield name="TP_TP_SCLK_PM_OVERRIDE" pos="20"/> + <bitfield name="TP_REG_SCLK_PM_OVERRIDE" pos="21"/> + <bitfield name="CP_G_SCLK_PM_OVERRIDE" pos="22"/> + <bitfield name="CP_REG_SCLK_PM_OVERRIDE" pos="23"/> + <bitfield name="CP_G_REG_SCLK_PM_OVERRIDE" pos="24"/> + <bitfield name="SPI_SCLK_PM_OVERRIDE" pos="25"/> + <bitfield name="RB_REG_SCLK_PM_OVERRIDE" pos="26"/> + <bitfield name="RB_SCLK_PM_OVERRIDE" pos="27"/> + <bitfield name="MH_MH_SCLK_PM_OVERRIDE" pos="28"/> + <bitfield name="MH_REG_SCLK_PM_OVERRIDE" pos="29"/> + <bitfield name="MH_MMU_SCLK_PM_OVERRIDE" pos="30"/> + <bitfield name="MH_TCROQ_SCLK_PM_OVERRIDE" pos="31"/> + </reg32> + <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/> + <reg32 offset="0x03a0" name="RBBM_DEBUG_OUT"/> + <reg32 offset="0x03a1" name="RBBM_DEBUG_CNTL"/> + <reg32 offset="0x03b3" name="RBBM_READ_ERROR"/> + <reg32 offset="0x03b4" name="RBBM_INT_CNTL"> + <bitfield name="RDERR_INT_MASK" pos="0" type="boolean"/> + <bitfield name="DISPLAY_UPDATE_INT_MASK" pos="1" type="boolean"/> + <bitfield name="GUI_IDLE_INT_MASK" pos="19" type="boolean"/> + </reg32> + <reg32 offset="0x03b5" name="RBBM_INT_STATUS"/> + <reg32 offset="0x03b6" name="RBBM_INT_ACK"/> + <reg32 offset="0x03b7" name="MASTER_INT_SIGNAL"> + <bitfield name="MH_INT_STAT" pos="5" type="boolean"/> + <bitfield name="SQ_INT_STAT" pos="26" type="boolean"/> + <bitfield name="CP_INT_STAT" pos="30" type="boolean"/> + <bitfield name="RBBM_INT_STAT" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x03f9" name="RBBM_PERIPHID1"/> + <reg32 offset="0x03fa" name="RBBM_PERIPHID2"/> + <reg32 offset="0x0444" name="CP_PERFMON_CNTL"/> + <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/> + <reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/> + <reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/> + <reg32 offset="0x05d0" name="RBBM_STATUS"> + <bitfield name="CMDFIFO_AVAIL" low="0" high="4" type="uint"/> + <bitfield name="TC_BUSY" pos="5" type="boolean"/> + <bitfield name="HIRQ_PENDING" pos="8" type="boolean"/> + <bitfield name="CPRQ_PENDING" pos="9" type="boolean"/> + <bitfield name="CFRQ_PENDING" pos="10" type="boolean"/> + <bitfield name="PFRQ_PENDING" pos="11" type="boolean"/> + <bitfield name="VGT_BUSY_NO_DMA" pos="12" type="boolean"/> + <bitfield name="RBBM_WU_BUSY" pos="14" type="boolean"/> + <bitfield name="CP_NRT_BUSY" pos="16" type="boolean"/> + <bitfield name="MH_BUSY" pos="18" type="boolean"/> + <bitfield name="MH_COHERENCY_BUSY" pos="19" type="boolean"/> + <bitfield name="SX_BUSY" pos="21" type="boolean"/> + <bitfield name="TPC_BUSY" pos="22" type="boolean"/> + <bitfield name="SC_CNTX_BUSY" pos="24" type="boolean"/> + <bitfield name="PA_BUSY" pos="25" type="boolean"/> + <bitfield name="VGT_BUSY" pos="26" type="boolean"/> + <bitfield name="SQ_CNTX17_BUSY" pos="27" type="boolean"/> + <bitfield name="SQ_CNTX0_BUSY" pos="28" type="boolean"/> + <bitfield name="RB_CNTX_BUSY" pos="30" type="boolean"/> + <bitfield name="GUI_ACTIVE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x0a40" name="MH_ARBITER_CONFIG"> + <bitfield name="SAME_PAGE_LIMIT" low="0" high="5" type="uint"/> + <bitfield name="SAME_PAGE_GRANULARITY" pos="6" type="boolean"/> + <bitfield name="L1_ARB_ENABLE" pos="7" type="boolean"/> + <bitfield name="L1_ARB_HOLD_ENABLE" pos="8" type="boolean"/> + <bitfield name="L2_ARB_CONTROL" pos="9" type="boolean"/> + <bitfield name="PAGE_SIZE" low="10" high="12" type="uint"/> + <bitfield name="TC_REORDER_ENABLE" pos="13" type="boolean"/> + <bitfield name="TC_ARB_HOLD_ENABLE" pos="14" type="boolean"/> + <bitfield name="IN_FLIGHT_LIMIT_ENABLE" pos="15" type="boolean"/> + <bitfield name="IN_FLIGHT_LIMIT" low="16" high="21" type="uint"/> + <bitfield name="CP_CLNT_ENABLE" pos="22" type="boolean"/> + <bitfield name="VGT_CLNT_ENABLE" pos="23" type="boolean"/> + <bitfield name="TC_CLNT_ENABLE" pos="24" type="boolean"/> + <bitfield name="RB_CLNT_ENABLE" pos="25" type="boolean"/> + <bitfield name="PA_CLNT_ENABLE" pos="26" type="boolean"/> + </reg32> + <reg32 offset="0x0a42" name="MH_INTERRUPT_MASK"> + <bitfield name="AXI_READ_ERROR" pos="0" type="boolean"/> + <bitfield name="AXI_WRITE_ERROR" pos="1" type="boolean"/> + <bitfield name="MMU_PAGE_FAULT" pos="2" type="boolean"/> + </reg32> + <reg32 offset="0x0a43" name="MH_INTERRUPT_STATUS"/> + <reg32 offset="0x0a44" name="MH_INTERRUPT_CLEAR"/> + <reg32 offset="0x0a54" name="MH_CLNT_INTF_CTRL_CONFIG1"/> + <reg32 offset="0x0a55" name="MH_CLNT_INTF_CTRL_CONFIG2"/> + <reg32 offset="0x0c01" name="A220_VSC_BIN_SIZE"> + <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/> + <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/> + </reg32> + <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8"> + <reg32 offset="0x0" name="CONFIG"/> + <reg32 offset="0x1" name="DATA_ADDRESS"/> + <reg32 offset="0x2" name="DATA_LENGTH"/> + </array> + <reg32 offset="0x0c38" name="PC_DEBUG_CNTL"/> + <reg32 offset="0x0c39" name="PC_DEBUG_DATA"/> + <reg32 offset="0x0c44" name="PA_SC_VIZ_QUERY_STATUS"/> + <reg32 offset="0x0c80" name="GRAS_DEBUG_CNTL"/> + <reg32 offset="0x0c80" name="PA_SU_DEBUG_CNTL"/> + <reg32 offset="0x0c81" name="GRAS_DEBUG_DATA"/> + <reg32 offset="0x0c81" name="PA_SU_DEBUG_DATA"/> + <reg32 offset="0x0c86" name="PA_SU_FACE_DATA"> + <bitfield name="BASE_ADDR" low="5" high="31" type="uint"/> + </reg32> + <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT"> + <bitfield name="REG_DYNAMIC" pos="0" type="boolean"/> + <bitfield name="REG_SIZE_PIX" low="4" high="11" type="uint"/> + <bitfield name="REG_SIZE_VTX" low="12" high="19" type="uint"/> + </reg32> + <reg32 offset="0x0d01" name="SQ_FLOW_CONTROL"/> + <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT"> + <bitfield name="INST_BASE_PIX" low="0" high="11" type="uint"/> + <bitfield name="INST_BASE_VTX" low="16" high="27" type="uint"/> + </reg32> + <reg32 offset="0x0d05" name="SQ_DEBUG_MISC"/> + <reg32 offset="0x0d34" name="SQ_INT_CNTL"/> + <reg32 offset="0x0d35" name="SQ_INT_STATUS"/> + <reg32 offset="0x0d36" name="SQ_INT_ACK"/> + <reg32 offset="0x0dae" name="SQ_DEBUG_INPUT_FSM"/> + <reg32 offset="0x0daf" name="SQ_DEBUG_CONST_MGR_FSM"/> + <reg32 offset="0x0db0" name="SQ_DEBUG_TP_FSM"/> + <reg32 offset="0x0db1" name="SQ_DEBUG_FSM_ALU_0"/> + <reg32 offset="0x0db2" name="SQ_DEBUG_FSM_ALU_1"/> + <reg32 offset="0x0db3" name="SQ_DEBUG_EXP_ALLOC"/> + <reg32 offset="0x0db4" name="SQ_DEBUG_PTR_BUFF"/> + <reg32 offset="0x0db5" name="SQ_DEBUG_GPR_VTX"/> + <reg32 offset="0x0db6" name="SQ_DEBUG_GPR_PIX"/> + <reg32 offset="0x0db7" name="SQ_DEBUG_TB_STATUS_SEL"/> + <reg32 offset="0x0db8" name="SQ_DEBUG_VTX_TB_0"/> + <reg32 offset="0x0db9" name="SQ_DEBUG_VTX_TB_1"/> + <reg32 offset="0x0dba" name="SQ_DEBUG_VTX_TB_STATUS_REG"/> + <reg32 offset="0x0dbb" name="SQ_DEBUG_VTX_TB_STATE_MEM"/> + <reg32 offset="0x0dbc" name="SQ_DEBUG_PIX_TB_0"/> + <reg32 offset="0x0dbd" name="SQ_DEBUG_PIX_TB_STATUS_REG_0"/> + <reg32 offset="0x0dbe" name="SQ_DEBUG_PIX_TB_STATUS_REG_1"/> + <reg32 offset="0x0dbf" name="SQ_DEBUG_PIX_TB_STATUS_REG_2"/> + <reg32 offset="0x0dc0" name="SQ_DEBUG_PIX_TB_STATUS_REG_3"/> + <reg32 offset="0x0dc1" name="SQ_DEBUG_PIX_TB_STATE_MEM"/> + <reg32 offset="0x0e00" name="TC_CNTL_STATUS"> + <bitfield name="L2_INVALIDATE" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x0e1e" name="TP0_CHICKEN"/> + <reg32 offset="0x0f01" name="RB_BC_CONTROL"> + <bitfield name="ACCUM_LINEAR_MODE_ENABLE" pos="0" type="boolean"/> + <bitfield name="ACCUM_TIMEOUT_SELECT" low="1" high="2" type="uint"/> + <bitfield name="DISABLE_EDRAM_CAM" pos="3" type="boolean"/> + <bitfield name="DISABLE_EZ_FAST_CONTEXT_SWITCH" pos="4" type="boolean"/> + <bitfield name="DISABLE_EZ_NULL_ZCMD_DROP" pos="5" type="boolean"/> + <bitfield name="DISABLE_LZ_NULL_ZCMD_DROP" pos="6" type="boolean"/> + <bitfield name="ENABLE_AZ_THROTTLE" pos="7" type="boolean"/> + <bitfield name="AZ_THROTTLE_COUNT" low="8" high="12" type="uint"/> + <bitfield name="ENABLE_CRC_UPDATE" pos="14" type="boolean"/> + <bitfield name="CRC_MODE" pos="15" type="boolean"/> + <bitfield name="DISABLE_SAMPLE_COUNTERS" pos="16" type="boolean"/> + <bitfield name="DISABLE_ACCUM" pos="17" type="boolean"/> + <bitfield name="ACCUM_ALLOC_MASK" low="18" high="21" type="uint"/> + <bitfield name="LINEAR_PERFORMANCE_ENABLE" pos="22" type="boolean"/> + <bitfield name="ACCUM_DATA_FIFO_LIMIT" low="23" high="26" type="uint"/> + <bitfield name="MEM_EXPORT_TIMEOUT_SELECT" low="27" high="28" type="uint"/> + <bitfield name="MEM_EXPORT_LINEAR_MODE_ENABLE" pos="29" type="boolean"/> + <bitfield name="CRC_SYSTEM" pos="30" type="boolean"/> + <bitfield name="RESERVED6" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x0f02" name="RB_EDRAM_INFO"/> + <reg32 offset="0x0f26" name="RB_DEBUG_CNTL"/> + <reg32 offset="0x0f27" name="RB_DEBUG_DATA"/> + <reg32 offset="0x2000" name="RB_SURFACE_INFO"> + <bitfield name="SURFACE_PITCH" low="0" high="13" type="uint"/> + <bitfield name="MSAA_SAMPLES" low="14" high="15" type="uint"/> + </reg32> + <reg32 offset="0x2001" name="RB_COLOR_INFO"> + <bitfield name="FORMAT" low="0" high="3" type="a2xx_colorformatx"/> + <bitfield name="ROUND_MODE" low="4" high="5" type="uint"/> + <bitfield name="LINEAR" pos="6" type="boolean"/> + <bitfield name="ENDIAN" low="7" high="8" type="uint"/> + <bitfield name="SWAP" low="9" high="10" type="uint"/> + <bitfield name="BASE" low="12" high="31" shr="12"/> + </reg32> + <reg32 offset="0x2002" name="RB_DEPTH_INFO"> + <bitfield name="DEPTH_FORMAT" pos="0" type="adreno_rb_depth_format"/> + <bitfield name="DEPTH_BASE" low="12" high="31" type="uint" shr="12"/> + </reg32> + <reg32 offset="0x2005" name="A225_RB_COLOR_INFO3"/> + <reg32 offset="0x2006" name="COHER_DEST_BASE_0"/> + <reg32 offset="0x200e" name="PA_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/> + <reg32 offset="0x200f" name="PA_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/> + <reg32 offset="0x2080" name="PA_SC_WINDOW_OFFSET"> + <bitfield name="X" low="0" high="14" type="int"/> + <bitfield name="Y" low="16" high="30" type="int"/> + <bitfield name="DISABLE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x2081" name="PA_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/> + <reg32 offset="0x2082" name="PA_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/> + <reg32 offset="0x2010" name="UNKNOWN_2010"/> + <reg32 offset="0x2100" name="VGT_MAX_VTX_INDX"/> + <reg32 offset="0x2101" name="VGT_MIN_VTX_INDX"/> + <reg32 offset="0x2102" name="VGT_INDX_OFFSET"/> + <reg32 offset="0x2103" name="A225_PC_MULTI_PRIM_IB_RESET_INDX"/> + <reg32 offset="0x2104" name="RB_COLOR_MASK"> + <bitfield name="WRITE_RED" pos="0" type="boolean"/> + <bitfield name="WRITE_GREEN" pos="1" type="boolean"/> + <bitfield name="WRITE_BLUE" pos="2" type="boolean"/> + <bitfield name="WRITE_ALPHA" pos="3" type="boolean"/> + </reg32> + <reg32 offset="0x2105" name="RB_BLEND_RED"/> + <reg32 offset="0x2106" name="RB_BLEND_GREEN"/> + <reg32 offset="0x2107" name="RB_BLEND_BLUE"/> + <reg32 offset="0x2108" name="RB_BLEND_ALPHA"/> + <reg32 offset="0x2109" name="RB_FOG_COLOR"> + <bitfield name="FOG_RED" low="0" high="7" type="uint"/> + <bitfield name="FOG_GREEN" low="8" high="15" type="uint"/> + <bitfield name="FOG_BLUE" low="16" high="23" type="uint"/> + </reg32> + <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/> + <reg32 offset="0x210d" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/> + <reg32 offset="0x210e" name="RB_ALPHA_REF"/> + <reg32 offset="0x210f" name="PA_CL_VPORT_XSCALE" type="float"/> + <reg32 offset="0x2110" name="PA_CL_VPORT_XOFFSET" type="float"/> + <reg32 offset="0x2111" name="PA_CL_VPORT_YSCALE" type="float"/> + <reg32 offset="0x2112" name="PA_CL_VPORT_YOFFSET" type="float"/> + <reg32 offset="0x2113" name="PA_CL_VPORT_ZSCALE" type="float"/> + <reg32 offset="0x2114" name="PA_CL_VPORT_ZOFFSET" type="float"/> + <reg32 offset="0x2180" name="SQ_PROGRAM_CNTL"> + <doc> + note: only 0x3f worth of valid register values for VS_REGS and + PS_REGS, but high bit is set to indicate '0 registers used': + </doc> + <bitfield name="VS_REGS" low="0" high="7" type="uint"/> + <bitfield name="PS_REGS" low="8" high="15" type="uint"/> + <bitfield name="VS_RESOURCE" pos="16" type="boolean"/> + <bitfield name="PS_RESOURCE" pos="17" type="boolean"/> + <bitfield name="PARAM_GEN" pos="18" type="boolean"/> + <bitfield name="GEN_INDEX_PIX" pos="19" type="boolean"/> + <bitfield name="VS_EXPORT_COUNT" low="20" high="23" type="uint"/> + <bitfield name="VS_EXPORT_MODE" low="24" high="26" type="a2xx_sq_ps_vtx_mode"/> + <bitfield name="PS_EXPORT_MODE" low="27" high="30" type="uint"/> + <bitfield name="GEN_INDEX_VTX" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x2181" name="SQ_CONTEXT_MISC"> + <bitfield name="INST_PRED_OPTIMIZE" pos="0" type="boolean"/> + <bitfield name="SC_OUTPUT_SCREEN_XY" pos="1" type="boolean"/> + <bitfield name="SC_SAMPLE_CNTL" low="2" high="3" type="a2xx_sq_sample_cntl"/> + <bitfield name="PARAM_GEN_POS" low="8" high="15" type="uint"/> + <bitfield name="PERFCOUNTER_REF" pos="16" type="boolean"/> + <bitfield name="YEILD_OPTIMIZE" pos="17" type="boolean"/> + <bitfield name="TX_CACHE_SEL" pos="18" type="boolean"/> + </reg32> + <reg32 offset="0x2182" name="SQ_INTERPOLATOR_CNTL"> + <bitfield name="PARAM_SHADE" low="0" high="15" type="uint"/> + <bitfield name="SAMPLING_PATTERN" low="16" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2183" name="SQ_WRAPPING_0"> + <bitfield name="PARAM_WRAP_0" low="0" high="3" type="uint"/> + <bitfield name="PARAM_WRAP_1" low="4" high="7" type="uint"/> + <bitfield name="PARAM_WRAP_2" low="8" high="11" type="uint"/> + <bitfield name="PARAM_WRAP_3" low="12" high="15" type="uint"/> + <bitfield name="PARAM_WRAP_4" low="16" high="19" type="uint"/> + <bitfield name="PARAM_WRAP_5" low="20" high="23" type="uint"/> + <bitfield name="PARAM_WRAP_6" low="24" high="27" type="uint"/> + <bitfield name="PARAM_WRAP_7" low="28" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2184" name="SQ_WRAPPING_1"> + <bitfield name="PARAM_WRAP_8" low="0" high="3" type="uint"/> + <bitfield name="PARAM_WRAP_9" low="4" high="7" type="uint"/> + <bitfield name="PARAM_WRAP_10" low="8" high="11" type="uint"/> + <bitfield name="PARAM_WRAP_11" low="12" high="15" type="uint"/> + <bitfield name="PARAM_WRAP_12" low="16" high="19" type="uint"/> + <bitfield name="PARAM_WRAP_13" low="20" high="23" type="uint"/> + <bitfield name="PARAM_WRAP_14" low="24" high="27" type="uint"/> + <bitfield name="PARAM_WRAP_15" low="28" high="31" type="uint"/> + </reg32> + <reg32 offset="0x21f6" name="SQ_PS_PROGRAM"> + <bitfield name="BASE" low="0" high="11" type="uint"/> + <bitfield name="SIZE" low="12" high="23" type="uint"/> + </reg32> + <reg32 offset="0x21f7" name="SQ_VS_PROGRAM"> + <bitfield name="BASE" low="0" high="11" type="uint"/> + <bitfield name="SIZE" low="12" high="23" type="uint"/> + </reg32> + <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/> + <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/> + <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/> + <reg32 offset="0x2200" name="RB_DEPTHCONTROL"> + <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> + <bitfield name="Z_ENABLE" pos="1" type="boolean"/> + <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/> + <bitfield name="EARLY_Z_ENABLE" pos="3" type="boolean"/> + <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/> + <bitfield name="BACKFACE_ENABLE" pos="7" type="boolean"/> + <bitfield name="STENCILFUNC" low="8" high="10" type="adreno_compare_func"/> + <bitfield name="STENCILFAIL" low="11" high="13" type="adreno_stencil_op"/> + <bitfield name="STENCILZPASS" low="14" high="16" type="adreno_stencil_op"/> + <bitfield name="STENCILZFAIL" low="17" high="19" type="adreno_stencil_op"/> + <bitfield name="STENCILFUNC_BF" low="20" high="22" type="adreno_compare_func"/> + <bitfield name="STENCILFAIL_BF" low="23" high="25" type="adreno_stencil_op"/> + <bitfield name="STENCILZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> + <bitfield name="STENCILZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> + </reg32> + <reg32 offset="0x2201" name="RB_BLEND_CONTROL"> + <bitfield name="COLOR_SRCBLEND" low="0" high="4" type="adreno_rb_blend_factor"/> + <bitfield name="COLOR_COMB_FCN" low="5" high="7" type="a2xx_rb_blend_opcode"/> + <bitfield name="COLOR_DESTBLEND" low="8" high="12" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_SRCBLEND" low="16" high="20" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_COMB_FCN" low="21" high="23" type="a2xx_rb_blend_opcode"/> + <bitfield name="ALPHA_DESTBLEND" low="24" high="28" type="adreno_rb_blend_factor"/> + <bitfield name="BLEND_FORCE_ENABLE" pos="29" type="boolean"/> + <bitfield name="BLEND_FORCE" pos="30" type="boolean"/> + </reg32> + <reg32 offset="0x2202" name="RB_COLORCONTROL"> + <bitfield name="ALPHA_FUNC" low="0" high="2" type="adreno_compare_func"/> + <bitfield name="ALPHA_TEST_ENABLE" pos="3" type="boolean"/> + <bitfield name="ALPHA_TO_MASK_ENABLE" pos="4" type="boolean"/> + <bitfield name="BLEND_DISABLE" pos="5" type="boolean"/> + <bitfield name="VOB_ENABLE" pos="6" type="boolean"/> + <bitfield name="VS_EXPORTS_FOG" pos="7" type="boolean"/> + <bitfield name="ROP_CODE" low="8" high="11" type="uint"/> + <bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/> + <bitfield name="DITHER_TYPE" low="14" high="15" type="a2xx_rb_dither_type"/> + <bitfield name="PIXEL_FOG" pos="16" type="boolean"/> + <bitfield name="ALPHA_TO_MASK_OFFSET0" low="24" high="25" type="uint"/> + <bitfield name="ALPHA_TO_MASK_OFFSET1" low="26" high="27" type="uint"/> + <bitfield name="ALPHA_TO_MASK_OFFSET2" low="28" high="29" type="uint"/> + <bitfield name="ALPHA_TO_MASK_OFFSET3" low="30" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2203" name="VGT_CURRENT_BIN_ID_MAX" type="a2xx_vgt_current_bin_id_min_max"/> + <reg32 offset="0x2204" name="PA_CL_CLIP_CNTL"> + <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/> + <bitfield name="BOUNDARY_EDGE_FLAG_ENA" pos="18" type="boolean"/> + <bitfield name="DX_CLIP_SPACE_DEF" pos="19" type="a2xx_dx_clip_space"/> + <bitfield name="DIS_CLIP_ERR_DETECT" pos="20" type="boolean"/> + <bitfield name="VTX_KILL_OR" pos="21" type="boolean"/> + <bitfield name="XY_NAN_RETAIN" pos="22" type="boolean"/> + <bitfield name="Z_NAN_RETAIN" pos="23" type="boolean"/> + <bitfield name="W_NAN_RETAIN" pos="24" type="boolean"/> + </reg32> + <reg32 offset="0x2205" name="PA_SU_SC_MODE_CNTL"> + <bitfield name="CULL_FRONT" pos="0" type="boolean"/> + <bitfield name="CULL_BACK" pos="1" type="boolean"/> + <bitfield name="FACE" pos="2" type="boolean"/> + <bitfield name="POLYMODE" low="3" high="4" type="a2xx_pa_su_sc_polymode"/> + <bitfield name="FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/> + <bitfield name="BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/> + <bitfield name="POLY_OFFSET_FRONT_ENABLE" pos="11" type="boolean"/> + <bitfield name="POLY_OFFSET_BACK_ENABLE" pos="12" type="boolean"/> + <bitfield name="POLY_OFFSET_PARA_ENABLE" pos="13" type="boolean"/> + <bitfield name="MSAA_ENABLE" pos="15" type="boolean"/> + <bitfield name="VTX_WINDOW_OFFSET_ENABLE" pos="16" type="boolean"/> + <bitfield name="LINE_STIPPLE_ENABLE" pos="18" type="boolean"/> + <bitfield name="PROVOKING_VTX_LAST" pos="19" type="boolean"/> + <bitfield name="PERSP_CORR_DIS" pos="20" type="boolean"/> + <bitfield name="MULTI_PRIM_IB_ENA" pos="21" type="boolean"/> + <bitfield name="QUAD_ORDER_ENABLE" pos="23" type="boolean"/> + <bitfield name="WAIT_RB_IDLE_ALL_TRI" pos="25" type="boolean"/> + <bitfield name="WAIT_RB_IDLE_FIRST_TRI_NEW_STATE" pos="26" type="boolean"/> + <bitfield name="CLAMPED_FACENESS" pos="28" type="boolean"/> + <bitfield name="ZERO_AREA_FACENESS" pos="29" type="boolean"/> + <bitfield name="FACE_KILL_ENABLE" pos="30" type="boolean"/> + <bitfield name="FACE_WRITE_ENABLE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x2206" name="PA_CL_VTE_CNTL"> + <bitfield name="VPORT_X_SCALE_ENA" pos="0" type="boolean"/> + <bitfield name="VPORT_X_OFFSET_ENA" pos="1" type="boolean"/> + <bitfield name="VPORT_Y_SCALE_ENA" pos="2" type="boolean"/> + <bitfield name="VPORT_Y_OFFSET_ENA" pos="3" type="boolean"/> + <bitfield name="VPORT_Z_SCALE_ENA" pos="4" type="boolean"/> + <bitfield name="VPORT_Z_OFFSET_ENA" pos="5" type="boolean"/> + <bitfield name="VTX_XY_FMT" pos="8" type="boolean"/> + <bitfield name="VTX_Z_FMT" pos="9" type="boolean"/> + <bitfield name="VTX_W0_FMT" pos="10" type="boolean"/> + <bitfield name="PERFCOUNTER_REF" pos="11" type="boolean"/> + </reg32> + <reg32 offset="0x2207" name="VGT_CURRENT_BIN_ID_MIN" type="a2xx_vgt_current_bin_id_min_max"/> + <reg32 offset="0x2208" name="RB_MODECONTROL"> + <bitfield name="EDRAM_MODE" low="0" high="2" type="a2xx_rb_edram_mode"/> + </reg32> + <reg32 offset="0x2209" name="A220_RB_LRZ_VSC_CONTROL"/> + <reg32 offset="0x220a" name="RB_SAMPLE_POS"/> + <reg32 offset="0x220b" name="CLEAR_COLOR"> + <bitfield name="RED" low="0" high="7"/> + <bitfield name="GREEN" low="8" high="15"/> + <bitfield name="BLUE" low="16" high="23"/> + <bitfield name="ALPHA" low="24" high="31"/> + </reg32> + <reg32 offset="0x2210" name="A220_GRAS_CONTROL"/> + <reg32 offset="0x2280" name="PA_SU_POINT_SIZE"> + <bitfield name="HEIGHT" low="0" high="15" type="ufixed" radix="4"/> + <bitfield name="WIDTH" low="16" high="31" type="ufixed" radix="4"/> + </reg32> + <reg32 offset="0x2281" name="PA_SU_POINT_MINMAX"> + <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> + <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> + </reg32> + <reg32 offset="0x2282" name="PA_SU_LINE_CNTL"> + <bitfield name="WIDTH" low="0" high="15" type="ufixed" radix="4"/> + </reg32> + <reg32 offset="0x2283" name="PA_SC_LINE_STIPPLE"> + <bitfield name="LINE_PATTERN" low="0" high="15" type="hex"/> + <bitfield name="REPEAT_COUNT" low="16" high="23" type="uint"/> + <bitfield name="PATTERN_BIT_ORDER" pos="28" type="a2xx_pa_sc_pattern_bit_order"/> + <bitfield name="AUTO_RESET_CNTL" low="29" high="30" type="a2xx_pa_sc_auto_reset_cntl"/> + </reg32> + <reg32 offset="0x2293" name="PA_SC_VIZ_QUERY"> + <bitfield name="VIZ_QUERY_ENA" pos="0" type="boolean"/> + <bitfield name="VIZ_QUERY_ID" low="1" high="6" type="uint"/> + <bitfield name="KILL_PIX_POST_EARLY_Z" pos="8" type="boolean"/> + </reg32> + <reg32 offset="0x2294" name="VGT_ENHANCE"/> + <reg32 offset="0x2300" name="PA_SC_LINE_CNTL"> + <bitfield name="BRES_CNTL" low="0" high="15" type="uint"/> + <bitfield name="USE_BRES_CNTL" pos="8" type="boolean"/> + <bitfield name="EXPAND_LINE_WIDTH" pos="9" type="boolean"/> + <bitfield name="LAST_PIXEL" pos="10" type="boolean"/> + </reg32> + <reg32 offset="0x2301" name="PA_SC_AA_CONFIG"> + <bitfield name="MSAA_NUM_SAMPLES" low="0" high="2" type="uint"/> + <bitfield name="MAX_SAMPLE_DIST" low="13" high="16" type="uint"/> + </reg32> + <reg32 offset="0x2302" name="PA_SU_VTX_CNTL"> + <bitfield name="PIX_CENTER" pos="0" type="a2xx_pa_pixcenter"/> + <bitfield name="ROUND_MODE" low="1" high="2" type="a2xx_pa_roundmode"/> + <bitfield name="QUANT_MODE" low="7" high="9" type="a2xx_pa_quantmode"/> + </reg32> + <reg32 offset="0x2303" name="PA_CL_GB_VERT_CLIP_ADJ" type="float"/> + <reg32 offset="0x2304" name="PA_CL_GB_VERT_DISC_ADJ" type="float"/> + <reg32 offset="0x2305" name="PA_CL_GB_HORZ_CLIP_ADJ" type="float"/> + <reg32 offset="0x2306" name="PA_CL_GB_HORZ_DISC_ADJ" type="float"/> + <reg32 offset="0x2307" name="SQ_VS_CONST"> + <bitfield name="BASE" low="0" high="8" type="uint"/> + <bitfield name="SIZE" low="12" high="20" type="uint"/> + </reg32> + <reg32 offset="0x2308" name="SQ_PS_CONST"> + <bitfield name="BASE" low="0" high="8" type="uint"/> + <bitfield name="SIZE" low="12" high="20" type="uint"/> + </reg32> + <reg32 offset="0x2309" name="SQ_DEBUG_MISC_0"/> + <reg32 offset="0x230a" name="SQ_DEBUG_MISC_1"/> + <reg32 offset="0x2312" name="PA_SC_AA_MASK"/> + <reg32 offset="0x2316" name="VGT_VERTEX_REUSE_BLOCK_CNTL"> + <bitfield name="VTX_REUSE_DEPTH" low="0" high="2" type="uint"/> + </reg32> + <reg32 offset="0x2317" name="VGT_OUT_DEALLOC_CNTL"> + <bitfield name="DEALLOC_DIST" low="0" high="1" type="uint"/> + </reg32> + <reg32 offset="0x2318" name="RB_COPY_CONTROL"> + <bitfield name="COPY_SAMPLE_SELECT" low="0" high="2" type="a2xx_rb_copy_sample_select"/> + <bitfield name="DEPTH_CLEAR_ENABLE" pos="3" type="boolean"/> + <bitfield name="CLEAR_MASK" low="4" high="7" type="hex"/> + </reg32> + <reg32 offset="0x2319" name="RB_COPY_DEST_BASE"/> + <reg32 offset="0x231a" name="RB_COPY_DEST_PITCH" shr="5" type="uint"/> + <reg32 offset="0x231b" name="RB_COPY_DEST_INFO"> + <bitfield name="DEST_ENDIAN" low="0" high="2" type="adreno_rb_surface_endian"/> + <bitfield name="LINEAR" pos="3" type="boolean"/> + <bitfield name="FORMAT" low="4" high="7" type="a2xx_colorformatx"/> + <bitfield name="SWAP" low="8" high="9" type="uint"/> + <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/> + <bitfield name="DITHER_TYPE" low="12" high="13" type="a2xx_rb_dither_type"/> + <bitfield name="WRITE_RED" pos="14" type="boolean"/> + <bitfield name="WRITE_GREEN" pos="15" type="boolean"/> + <bitfield name="WRITE_BLUE" pos="16" type="boolean"/> + <bitfield name="WRITE_ALPHA" pos="17" type="boolean"/> + </reg32> + <reg32 offset="0x231c" name="RB_COPY_DEST_OFFSET"> + <bitfield name="X" low="0" high="12" type="uint"/> + <bitfield name="Y" low="13" high="25" type="uint"/> + </reg32> + <reg32 offset="0x231d" name="RB_DEPTH_CLEAR"/> + <reg32 offset="0x2324" name="RB_SAMPLE_COUNT_CTL"/> + <reg32 offset="0x2326" name="RB_COLOR_DEST_MASK"/> + <reg32 offset="0x2340" name="A225_GRAS_UCP0X"/> + <reg32 offset="0x2357" name="A225_GRAS_UCP5W"/> + <reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/> + <reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/> + <reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/> + <reg32 offset="0x4000" name="SQ_CONSTANT_0"/> + <reg32 offset="0x4800" name="SQ_FETCH_0"/> + <reg32 offset="0x4900" name="SQ_CF_BOOLEANS"/> + <reg32 offset="0x4908" name="SQ_CF_LOOP"/> + <reg32 offset="0xa29" name="COHER_SIZE_PM4"/> + <reg32 offset="0xa2a" name="COHER_BASE_PM4"/> + <reg32 offset="0xa2b" name="COHER_STATUS_PM4"/> + + <reg32 offset="0x0c88" name="PA_SU_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0c89" name="PA_SU_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0c8a" name="PA_SU_PERFCOUNTER2_SELECT"/> + <reg32 offset="0x0c8b" name="PA_SU_PERFCOUNTER3_SELECT"/> + <reg32 offset="0x0c8c" name="PA_SU_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0c8d" name="PA_SU_PERFCOUNTER0_HI"/> + <reg32 offset="0x0c8e" name="PA_SU_PERFCOUNTER1_LOW"/> + <reg32 offset="0x0c8f" name="PA_SU_PERFCOUNTER1_HI"/> + <reg32 offset="0x0c90" name="PA_SU_PERFCOUNTER2_LOW"/> + <reg32 offset="0x0c91" name="PA_SU_PERFCOUNTER2_HI"/> + <reg32 offset="0x0c92" name="PA_SU_PERFCOUNTER3_LOW"/> + <reg32 offset="0x0c93" name="PA_SU_PERFCOUNTER3_HI"/> + <reg32 offset="0x0c98" name="PA_SC_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0c99" name="PA_SC_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0c9a" name="PA_SC_PERFCOUNTER0_HI"/> + <reg32 offset="0x0c48" name="VGT_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0c49" name="VGT_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0c4a" name="VGT_PERFCOUNTER2_SELECT"/> + <reg32 offset="0x0c4b" name="VGT_PERFCOUNTER3_SELECT"/> + <reg32 offset="0x0c4c" name="VGT_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0c4e" name="VGT_PERFCOUNTER1_LOW"/> + <reg32 offset="0x0c50" name="VGT_PERFCOUNTER2_LOW"/> + <reg32 offset="0x0c52" name="VGT_PERFCOUNTER3_LOW"/> + <reg32 offset="0x0c4d" name="VGT_PERFCOUNTER0_HI"/> + <reg32 offset="0x0c4f" name="VGT_PERFCOUNTER1_HI"/> + <reg32 offset="0x0c51" name="VGT_PERFCOUNTER2_HI"/> + <reg32 offset="0x0c53" name="VGT_PERFCOUNTER3_HI"/> + <reg32 offset="0x0e05" name="TCR_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0e08" name="TCR_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0e06" name="TCR_PERFCOUNTER0_HI"/> + <reg32 offset="0x0e09" name="TCR_PERFCOUNTER1_HI"/> + <reg32 offset="0x0e07" name="TCR_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0e0a" name="TCR_PERFCOUNTER1_LOW"/> + <reg32 offset="0x0e1f" name="TP0_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0e20" name="TP0_PERFCOUNTER0_HI"/> + <reg32 offset="0x0e21" name="TP0_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0e22" name="TP0_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0e23" name="TP0_PERFCOUNTER1_HI"/> + <reg32 offset="0x0e24" name="TP0_PERFCOUNTER1_LOW"/> + <reg32 offset="0x0e54" name="TCM_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0e57" name="TCM_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0e55" name="TCM_PERFCOUNTER0_HI"/> + <reg32 offset="0x0e58" name="TCM_PERFCOUNTER1_HI"/> + <reg32 offset="0x0e56" name="TCM_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0e59" name="TCM_PERFCOUNTER1_LOW"/> + <reg32 offset="0x0e5a" name="TCF_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0e5d" name="TCF_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0e60" name="TCF_PERFCOUNTER2_SELECT"/> + <reg32 offset="0x0e63" name="TCF_PERFCOUNTER3_SELECT"/> + <reg32 offset="0x0e66" name="TCF_PERFCOUNTER4_SELECT"/> + <reg32 offset="0x0e69" name="TCF_PERFCOUNTER5_SELECT"/> + <reg32 offset="0x0e6c" name="TCF_PERFCOUNTER6_SELECT"/> + <reg32 offset="0x0e6f" name="TCF_PERFCOUNTER7_SELECT"/> + <reg32 offset="0x0e72" name="TCF_PERFCOUNTER8_SELECT"/> + <reg32 offset="0x0e75" name="TCF_PERFCOUNTER9_SELECT"/> + <reg32 offset="0x0e78" name="TCF_PERFCOUNTER10_SELECT"/> + <reg32 offset="0x0e7b" name="TCF_PERFCOUNTER11_SELECT"/> + <reg32 offset="0x0e5b" name="TCF_PERFCOUNTER0_HI"/> + <reg32 offset="0x0e5e" name="TCF_PERFCOUNTER1_HI"/> + <reg32 offset="0x0e61" name="TCF_PERFCOUNTER2_HI"/> + <reg32 offset="0x0e64" name="TCF_PERFCOUNTER3_HI"/> + <reg32 offset="0x0e67" name="TCF_PERFCOUNTER4_HI"/> + <reg32 offset="0x0e6a" name="TCF_PERFCOUNTER5_HI"/> + <reg32 offset="0x0e6d" name="TCF_PERFCOUNTER6_HI"/> + <reg32 offset="0x0e70" name="TCF_PERFCOUNTER7_HI"/> + <reg32 offset="0x0e73" name="TCF_PERFCOUNTER8_HI"/> + <reg32 offset="0x0e76" name="TCF_PERFCOUNTER9_HI"/> + <reg32 offset="0x0e79" name="TCF_PERFCOUNTER10_HI"/> + <reg32 offset="0x0e7c" name="TCF_PERFCOUNTER11_HI"/> + <reg32 offset="0x0e5c" name="TCF_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0e5f" name="TCF_PERFCOUNTER1_LOW"/> + <reg32 offset="0x0e62" name="TCF_PERFCOUNTER2_LOW"/> + <reg32 offset="0x0e65" name="TCF_PERFCOUNTER3_LOW"/> + <reg32 offset="0x0e68" name="TCF_PERFCOUNTER4_LOW"/> + <reg32 offset="0x0e6b" name="TCF_PERFCOUNTER5_LOW"/> + <reg32 offset="0x0e6e" name="TCF_PERFCOUNTER6_LOW"/> + <reg32 offset="0x0e71" name="TCF_PERFCOUNTER7_LOW"/> + <reg32 offset="0x0e74" name="TCF_PERFCOUNTER8_LOW"/> + <reg32 offset="0x0e77" name="TCF_PERFCOUNTER9_LOW"/> + <reg32 offset="0x0e7a" name="TCF_PERFCOUNTER10_LOW"/> + <reg32 offset="0x0e7d" name="TCF_PERFCOUNTER11_LOW"/> + <reg32 offset="0x0dc8" name="SQ_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0dc9" name="SQ_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0dca" name="SQ_PERFCOUNTER2_SELECT"/> + <reg32 offset="0x0dcb" name="SQ_PERFCOUNTER3_SELECT"/> + <reg32 offset="0x0dcc" name="SQ_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0dcd" name="SQ_PERFCOUNTER0_HI"/> + <reg32 offset="0x0dce" name="SQ_PERFCOUNTER1_LOW"/> + <reg32 offset="0x0dcf" name="SQ_PERFCOUNTER1_HI"/> + <reg32 offset="0x0dd0" name="SQ_PERFCOUNTER2_LOW"/> + <reg32 offset="0x0dd1" name="SQ_PERFCOUNTER2_HI"/> + <reg32 offset="0x0dd2" name="SQ_PERFCOUNTER3_LOW"/> + <reg32 offset="0x0dd3" name="SQ_PERFCOUNTER3_HI"/> + <reg32 offset="0x0dd4" name="SX_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0dd8" name="SX_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0dd9" name="SX_PERFCOUNTER0_HI"/> + <reg32 offset="0x0a46" name="MH_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0a4a" name="MH_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0a47" name="MH_PERFCOUNTER0_CONFIG"/> + <reg32 offset="0x0a4b" name="MH_PERFCOUNTER1_CONFIG"/> + <reg32 offset="0x0a48" name="MH_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0a4c" name="MH_PERFCOUNTER1_LOW"/> + <reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/> + <reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/> + <reg32 offset="0x0395" name="RBBM_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0397" name="RBBM_PERFCOUNTER1_LO"/> + <reg32 offset="0x0398" name="RBBM_PERFCOUNTER1_HI"/> + <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/> + <reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/> + <reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/> + <reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/> + <reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/> + <reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/> +</domain> + +<domain name="A2XX_SQ_TEX" width="32"> + <doc>Texture state dwords</doc> + <enum name="sq_tex_clamp"> + <value name="SQ_TEX_WRAP" value="0"/> + <value name="SQ_TEX_MIRROR" value="1"/> + <value name="SQ_TEX_CLAMP_LAST_TEXEL" value="2"/> + <value name="SQ_TEX_MIRROR_ONCE_LAST_TEXEL" value="3"/> + <value name="SQ_TEX_CLAMP_HALF_BORDER" value="4"/> + <value name="SQ_TEX_MIRROR_ONCE_HALF_BORDER" value="5"/> + <value name="SQ_TEX_CLAMP_BORDER" value="6"/> + <value name="SQ_TEX_MIRROR_ONCE_BORDER" value="7"/> + </enum> + <enum name="sq_tex_swiz"> + <value name="SQ_TEX_X" value="0"/> + <value name="SQ_TEX_Y" value="1"/> + <value name="SQ_TEX_Z" value="2"/> + <value name="SQ_TEX_W" value="3"/> + <value name="SQ_TEX_ZERO" value="4"/> + <value name="SQ_TEX_ONE" value="5"/> + </enum> + <enum name="sq_tex_filter"> + <value name="SQ_TEX_FILTER_POINT" value="0"/> + <value name="SQ_TEX_FILTER_BILINEAR" value="1"/> + <value name="SQ_TEX_FILTER_BASEMAP" value="2"/> + <value name="SQ_TEX_FILTER_USE_FETCH_CONST" value="3"/> + </enum> + <enum name="sq_tex_aniso_filter"> + <value name="SQ_TEX_ANISO_FILTER_DISABLED" value="0"/> + <value name="SQ_TEX_ANISO_FILTER_MAX_1_1" value="1"/> + <value name="SQ_TEX_ANISO_FILTER_MAX_2_1" value="2"/> + <value name="SQ_TEX_ANISO_FILTER_MAX_4_1" value="3"/> + <value name="SQ_TEX_ANISO_FILTER_MAX_8_1" value="4"/> + <value name="SQ_TEX_ANISO_FILTER_MAX_16_1" value="5"/> + <value name="SQ_TEX_ANISO_FILTER_USE_FETCH_CONST" value="7"/> + </enum> + <enum name="sq_tex_dimension"> + <value name="SQ_TEX_DIMENSION_1D" value="0"/> + <value name="SQ_TEX_DIMENSION_2D" value="1"/> + <value name="SQ_TEX_DIMENSION_3D" value="2"/> + <value name="SQ_TEX_DIMENSION_CUBE" value="3"/> + </enum> + <enum name="sq_tex_border_color"> + <value name="SQ_TEX_BORDER_COLOR_BLACK" value="0"/> + <value name="SQ_TEX_BORDER_COLOR_WHITE" value="1"/> + <value name="SQ_TEX_BORDER_COLOR_ACBYCR_BLACK" value="2"/> + <value name="SQ_TEX_BORDER_COLOR_ACBCRY_BLACK" value="3"/> + </enum> + <enum name="sq_tex_sign"> + <value name="SQ_TEX_SIGN_UNISIGNED" value="0"/> + <value name="SQ_TEX_SIGN_SIGNED" value="1"/> + <!-- biased: 2*color-1 (range -1,1 when sampling) --> + <value name="SQ_TEX_SIGN_UNISIGNED_BIASED" value="2"/> + <!-- gamma: sRGB to linear? --> + <value name="SQ_TEX_SIGN_GAMMA" value="3"/> + </enum> + <enum name="sq_tex_endian"> + <value name="SQ_TEX_ENDIAN_NONE" value="0"/> + <value name="SQ_TEX_ENDIAN_8IN16" value="1"/> + <value name="SQ_TEX_ENDIAN_8IN32" value="2"/> + <value name="SQ_TEX_ENDIAN_16IN32" value="3"/> + </enum> + <enum name="sq_tex_clamp_policy"> + <value name="SQ_TEX_CLAMP_POLICY_D3D" value="0"/> + <value name="SQ_TEX_CLAMP_POLICY_OGL" value="1"/> + </enum> + <enum name="sq_tex_num_format"> + <value name="SQ_TEX_NUM_FORMAT_FRAC" value="0"/> + <value name="SQ_TEX_NUM_FORMAT_INT" value="1"/> + </enum> + <enum name="sq_tex_type"> + <value name="SQ_TEX_TYPE_0" value="0"/> + <value name="SQ_TEX_TYPE_1" value="1"/> + <value name="SQ_TEX_TYPE_2" value="2"/> + <value name="SQ_TEX_TYPE_3" value="3"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="TYPE" low="0" high="1" type="sq_tex_type"/> + <bitfield name="SIGN_X" low="2" high="3" type="sq_tex_sign"/> + <bitfield name="SIGN_Y" low="4" high="5" type="sq_tex_sign"/> + <bitfield name="SIGN_Z" low="6" high="7" type="sq_tex_sign"/> + <bitfield name="SIGN_W" low="8" high="9" type="sq_tex_sign"/> + <bitfield name="CLAMP_X" low="10" high="12" type="sq_tex_clamp"/> + <bitfield name="CLAMP_Y" low="13" high="15" type="sq_tex_clamp"/>" + <bitfield name="CLAMP_Z" low="16" high="18" type="sq_tex_clamp"/>" + <bitfield name="PITCH" low="22" high="30" shr="5" type="uint"/> + <bitfield name="TILED" pos="1" type="boolean"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="FORMAT" low="0" high="5" type="a2xx_sq_surfaceformat"/> + <bitfield name="ENDIANNESS" low="6" high="7" type="sq_tex_endian"/> + <bitfield name="REQUEST_SIZE" low="8" high="9" type="uint"/> + <bitfield name="STACKED" pos="10" type="boolean"/> + <bitfield name="CLAMP_POLICY" pos="11" type="sq_tex_clamp_policy"/> + <bitfield name="BASE_ADDRESS" low="12" high="31" type="uint" shr="12"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="WIDTH" low="0" high="12" type="uint"/> + <bitfield name="HEIGHT" low="13" high="25" type="uint"/> + <bitfield name="DEPTH" low="26" high="31" type="uint"/> + <!-- 1d/3d have different bit configurations --> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="NUM_FORMAT" pos="0" type="sq_tex_num_format"/> + <bitfield name="SWIZ_X" low="1" high="3" type="sq_tex_swiz"/> + <bitfield name="SWIZ_Y" low="4" high="6" type="sq_tex_swiz"/> + <bitfield name="SWIZ_Z" low="7" high="9" type="sq_tex_swiz"/> + <bitfield name="SWIZ_W" low="10" high="12" type="sq_tex_swiz"/> + <bitfield name="EXP_ADJUST" low="13" high="18" type="uint"/> + <bitfield name="XY_MAG_FILTER" low="19" high="20" type="sq_tex_filter"/> + <bitfield name="XY_MIN_FILTER" low="21" high="22" type="sq_tex_filter"/> + <bitfield name="MIP_FILTER" low="23" high="24" type="sq_tex_filter"/> + <bitfield name="ANISO_FILTER" low="25" high="27" type="sq_tex_aniso_filter"/> + <bitfield name="BORDER_SIZE" pos="31" type="uint"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="VOL_MAG_FILTER" pos="0" type="sq_tex_filter"/> + <bitfield name="VOL_MIN_FILTER" pos="1" type="sq_tex_filter"/> + <bitfield name="MIP_MIN_LEVEL" low="2" high="5" type="uint"/> + <bitfield name="MIP_MAX_LEVEL" low="6" high="9" type="uint"/> + <bitfield name="MAX_ANISO_WALK" pos="10" type="boolean"/> + <bitfield name="MIN_ANISO_WALK" pos="11" type="boolean"/> + <bitfield name="LOD_BIAS" low="12" high="21" type="fixed" radix="5"/> + <bitfield name="GRAD_EXP_ADJUST_H" low="22" high="26" type="uint"/> + <bitfield name="GRAD_EXP_ADJUST_V" low="27" high="31" type="uint"/> + </reg32> + <reg32 offset="5" name="5"> + <bitfield name="BORDER_COLOR" low="0" high="1" type="sq_tex_border_color"/> + <bitfield name="FORCE_BCW_MAX" pos="2" type="boolean"/> + <bitfield name="TRI_CLAMP" low="3" high="4" type="uint"/> + <bitfield name="ANISO_BIAS" low="5" high="8" type="fixed" radix="0"/> <!-- radix unknown --> + <bitfield name="DIMENSION" low="9" high="10" type="sq_tex_dimension"/> + <bitfield name="PACKED_MIPS" pos="11" type="boolean"/> + <bitfield name="MIP_ADDRESS" low="12" high="31" type="uint" shr="12"/> + </reg32> +</domain> + +</database> diff --git a/src/freedreno/registers/a2xx.xml.h b/src/freedreno/registers/a2xx.xml.h deleted file mode 100644 index deded78035c..00000000000 --- a/src/freedreno/registers/a2xx.xml.h +++ /dev/null @@ -1,3017 +0,0 @@ -#ifndef A2XX_XML -#define A2XX_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2019 by the following authors: -- Rob Clark <[email protected]> (robclark) -- Ilia Mirkin <[email protected]> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum a2xx_rb_dither_type { - DITHER_PIXEL = 0, - DITHER_SUBPIXEL = 1, -}; - -enum a2xx_colorformatx { - COLORX_4_4_4_4 = 0, - COLORX_1_5_5_5 = 1, - COLORX_5_6_5 = 2, - COLORX_8 = 3, - COLORX_8_8 = 4, - COLORX_8_8_8_8 = 5, - COLORX_S8_8_8_8 = 6, - COLORX_16_FLOAT = 7, - COLORX_16_16_FLOAT = 8, - COLORX_16_16_16_16_FLOAT = 9, - COLORX_32_FLOAT = 10, - COLORX_32_32_FLOAT = 11, - COLORX_32_32_32_32_FLOAT = 12, - COLORX_2_3_3 = 13, - COLORX_8_8_8 = 14, -}; - -enum a2xx_sq_surfaceformat { - FMT_1_REVERSE = 0, - FMT_1 = 1, - FMT_8 = 2, - FMT_1_5_5_5 = 3, - FMT_5_6_5 = 4, - FMT_6_5_5 = 5, - FMT_8_8_8_8 = 6, - FMT_2_10_10_10 = 7, - FMT_8_A = 8, - FMT_8_B = 9, - FMT_8_8 = 10, - FMT_Cr_Y1_Cb_Y0 = 11, - FMT_Y1_Cr_Y0_Cb = 12, - FMT_5_5_5_1 = 13, - FMT_8_8_8_8_A = 14, - FMT_4_4_4_4 = 15, - FMT_8_8_8 = 16, - FMT_DXT1 = 18, - FMT_DXT2_3 = 19, - FMT_DXT4_5 = 20, - FMT_10_10_10_2 = 21, - FMT_24_8 = 22, - FMT_16 = 24, - FMT_16_16 = 25, - FMT_16_16_16_16 = 26, - FMT_16_EXPAND = 27, - FMT_16_16_EXPAND = 28, - FMT_16_16_16_16_EXPAND = 29, - FMT_16_FLOAT = 30, - FMT_16_16_FLOAT = 31, - FMT_16_16_16_16_FLOAT = 32, - FMT_32 = 33, - FMT_32_32 = 34, - FMT_32_32_32_32 = 35, - FMT_32_FLOAT = 36, - FMT_32_32_FLOAT = 37, - FMT_32_32_32_32_FLOAT = 38, - FMT_ATI_TC_RGB = 39, - FMT_ATI_TC_RGBA = 40, - FMT_ATI_TC_555_565_RGB = 41, - FMT_ATI_TC_555_565_RGBA = 42, - FMT_ATI_TC_RGBA_INTERP = 43, - FMT_ATI_TC_555_565_RGBA_INTERP = 44, - FMT_ETC1_RGBA_INTERP = 46, - FMT_ETC1_RGB = 47, - FMT_ETC1_RGBA = 48, - FMT_DXN = 49, - FMT_2_3_3 = 51, - FMT_2_10_10_10_AS_16_16_16_16 = 54, - FMT_10_10_10_2_AS_16_16_16_16 = 55, - FMT_32_32_32_FLOAT = 57, - FMT_DXT3A = 58, - FMT_DXT5A = 59, - FMT_CTX1 = 60, -}; - -enum a2xx_sq_ps_vtx_mode { - POSITION_1_VECTOR = 0, - POSITION_2_VECTORS_UNUSED = 1, - POSITION_2_VECTORS_SPRITE = 2, - POSITION_2_VECTORS_EDGE = 3, - POSITION_2_VECTORS_KILL = 4, - POSITION_2_VECTORS_SPRITE_KILL = 5, - POSITION_2_VECTORS_EDGE_KILL = 6, - MULTIPASS = 7, -}; - -enum a2xx_sq_sample_cntl { - CENTROIDS_ONLY = 0, - CENTERS_ONLY = 1, - CENTROIDS_AND_CENTERS = 2, -}; - -enum a2xx_dx_clip_space { - DXCLIP_OPENGL = 0, - DXCLIP_DIRECTX = 1, -}; - -enum a2xx_pa_su_sc_polymode { - POLY_DISABLED = 0, - POLY_DUALMODE = 1, -}; - -enum a2xx_rb_edram_mode { - EDRAM_NOP = 0, - COLOR_DEPTH = 4, - DEPTH_ONLY = 5, - EDRAM_COPY = 6, -}; - -enum a2xx_pa_sc_pattern_bit_order { - LITTLE = 0, - BIG = 1, -}; - -enum a2xx_pa_sc_auto_reset_cntl { - NEVER = 0, - EACH_PRIMITIVE = 1, - EACH_PACKET = 2, -}; - -enum a2xx_pa_pixcenter { - PIXCENTER_D3D = 0, - PIXCENTER_OGL = 1, -}; - -enum a2xx_pa_roundmode { - TRUNCATE = 0, - ROUND = 1, - ROUNDTOEVEN = 2, - ROUNDTOODD = 3, -}; - -enum a2xx_pa_quantmode { - ONE_SIXTEENTH = 0, - ONE_EIGTH = 1, - ONE_QUARTER = 2, - ONE_HALF = 3, - ONE = 4, -}; - -enum a2xx_rb_copy_sample_select { - SAMPLE_0 = 0, - SAMPLE_1 = 1, - SAMPLE_2 = 2, - SAMPLE_3 = 3, - SAMPLE_01 = 4, - SAMPLE_23 = 5, - SAMPLE_0123 = 6, -}; - -enum a2xx_rb_blend_opcode { - BLEND2_DST_PLUS_SRC = 0, - BLEND2_SRC_MINUS_DST = 1, - BLEND2_MIN_DST_SRC = 2, - BLEND2_MAX_DST_SRC = 3, - BLEND2_DST_MINUS_SRC = 4, - BLEND2_DST_PLUS_SRC_BIAS = 5, -}; - -enum a2xx_su_perfcnt_select { - PERF_PAPC_PASX_REQ = 0, - PERF_PAPC_PASX_FIRST_VECTOR = 2, - PERF_PAPC_PASX_SECOND_VECTOR = 3, - PERF_PAPC_PASX_FIRST_DEAD = 4, - PERF_PAPC_PASX_SECOND_DEAD = 5, - PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, - PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, - PERF_PAPC_PA_INPUT_PRIM = 8, - PERF_PAPC_PA_INPUT_NULL_PRIM = 9, - PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, - PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, - PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, - PERF_PAPC_CLPR_CULL_PRIM = 13, - PERF_PAPC_CLPR_VV_CULL_PRIM = 15, - PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, - PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, - PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, - PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, - PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, - PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, - PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, - PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, - PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, - PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, - PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, - PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, - PERF_PAPC_CLSM_NULL_PRIM = 36, - PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, - PERF_PAPC_CLSM_CLIP_PRIM = 38, - PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, - PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, - PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, - PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, - PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, - PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, - PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, - PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, - PERF_PAPC_SU_INPUT_PRIM = 47, - PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, - PERF_PAPC_SU_INPUT_NULL_PRIM = 49, - PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, - PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, - PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, - PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, - PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, - PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, - PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, - PERF_PAPC_SU_OUTPUT_PRIM = 57, - PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, - PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, - PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, - PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, - PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, - PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, - PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, - PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, - PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, - PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, - PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, - PERF_PAPC_PASX_REQ_IDLE = 69, - PERF_PAPC_PASX_REQ_BUSY = 70, - PERF_PAPC_PASX_REQ_STALLED = 71, - PERF_PAPC_PASX_REC_IDLE = 72, - PERF_PAPC_PASX_REC_BUSY = 73, - PERF_PAPC_PASX_REC_STARVED_SX = 74, - PERF_PAPC_PASX_REC_STALLED = 75, - PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, - PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, - PERF_PAPC_CCGSM_IDLE = 78, - PERF_PAPC_CCGSM_BUSY = 79, - PERF_PAPC_CCGSM_STALLED = 80, - PERF_PAPC_CLPRIM_IDLE = 81, - PERF_PAPC_CLPRIM_BUSY = 82, - PERF_PAPC_CLPRIM_STALLED = 83, - PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, - PERF_PAPC_CLIPSM_IDLE = 85, - PERF_PAPC_CLIPSM_BUSY = 86, - PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, - PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, - PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, - PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, - PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, - PERF_PAPC_CLIPGA_IDLE = 92, - PERF_PAPC_CLIPGA_BUSY = 93, - PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, - PERF_PAPC_CLIPGA_STALLED = 95, - PERF_PAPC_CLIP_IDLE = 96, - PERF_PAPC_CLIP_BUSY = 97, - PERF_PAPC_SU_IDLE = 98, - PERF_PAPC_SU_BUSY = 99, - PERF_PAPC_SU_STARVED_CLIP = 100, - PERF_PAPC_SU_STALLED_SC = 101, - PERF_PAPC_SU_FACENESS_CULL = 102, -}; - -enum a2xx_sc_perfcnt_select { - SC_SR_WINDOW_VALID = 0, - SC_CW_WINDOW_VALID = 1, - SC_QM_WINDOW_VALID = 2, - SC_FW_WINDOW_VALID = 3, - SC_EZ_WINDOW_VALID = 4, - SC_IT_WINDOW_VALID = 5, - SC_STARVED_BY_PA = 6, - SC_STALLED_BY_RB_TILE = 7, - SC_STALLED_BY_RB_SAMP = 8, - SC_STARVED_BY_RB_EZ = 9, - SC_STALLED_BY_SAMPLE_FF = 10, - SC_STALLED_BY_SQ = 11, - SC_STALLED_BY_SP = 12, - SC_TOTAL_NO_PRIMS = 13, - SC_NON_EMPTY_PRIMS = 14, - SC_NO_TILES_PASSING_QM = 15, - SC_NO_PIXELS_PRE_EZ = 16, - SC_NO_PIXELS_POST_EZ = 17, -}; - -enum a2xx_vgt_perfcount_select { - VGT_SQ_EVENT_WINDOW_ACTIVE = 0, - VGT_SQ_SEND = 1, - VGT_SQ_STALLED = 2, - VGT_SQ_STARVED_BUSY = 3, - VGT_SQ_STARVED_IDLE = 4, - VGT_SQ_STATIC = 5, - VGT_PA_EVENT_WINDOW_ACTIVE = 6, - VGT_PA_CLIP_V_SEND = 7, - VGT_PA_CLIP_V_STALLED = 8, - VGT_PA_CLIP_V_STARVED_BUSY = 9, - VGT_PA_CLIP_V_STARVED_IDLE = 10, - VGT_PA_CLIP_V_STATIC = 11, - VGT_PA_CLIP_P_SEND = 12, - VGT_PA_CLIP_P_STALLED = 13, - VGT_PA_CLIP_P_STARVED_BUSY = 14, - VGT_PA_CLIP_P_STARVED_IDLE = 15, - VGT_PA_CLIP_P_STATIC = 16, - VGT_PA_CLIP_S_SEND = 17, - VGT_PA_CLIP_S_STALLED = 18, - VGT_PA_CLIP_S_STARVED_BUSY = 19, - VGT_PA_CLIP_S_STARVED_IDLE = 20, - VGT_PA_CLIP_S_STATIC = 21, - RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, - RBIU_IMMED_DATA_FIFO_STARVED = 23, - RBIU_IMMED_DATA_FIFO_STALLED = 24, - RBIU_DMA_REQUEST_FIFO_STARVED = 25, - RBIU_DMA_REQUEST_FIFO_STALLED = 26, - RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, - RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, - BIN_PRIM_NEAR_CULL = 29, - BIN_PRIM_ZERO_CULL = 30, - BIN_PRIM_FAR_CULL = 31, - BIN_PRIM_BIN_CULL = 32, - BIN_PRIM_FACE_CULL = 33, - SPARE34 = 34, - SPARE35 = 35, - SPARE36 = 36, - SPARE37 = 37, - SPARE38 = 38, - SPARE39 = 39, - TE_SU_IN_VALID = 40, - TE_SU_IN_READ = 41, - TE_SU_IN_PRIM = 42, - TE_SU_IN_EOP = 43, - TE_SU_IN_NULL_PRIM = 44, - TE_WK_IN_VALID = 45, - TE_WK_IN_READ = 46, - TE_OUT_PRIM_VALID = 47, - TE_OUT_PRIM_READ = 48, -}; - -enum a2xx_tcr_perfcount_select { - DGMMPD_IPMUX0_STALL = 0, - DGMMPD_IPMUX_ALL_STALL = 4, - OPMUX0_L2_WRITES = 5, -}; - -enum a2xx_tp_perfcount_select { - POINT_QUADS = 0, - BILIN_QUADS = 1, - ANISO_QUADS = 2, - MIP_QUADS = 3, - VOL_QUADS = 4, - MIP_VOL_QUADS = 5, - MIP_ANISO_QUADS = 6, - VOL_ANISO_QUADS = 7, - ANISO_2_1_QUADS = 8, - ANISO_4_1_QUADS = 9, - ANISO_6_1_QUADS = 10, - ANISO_8_1_QUADS = 11, - ANISO_10_1_QUADS = 12, - ANISO_12_1_QUADS = 13, - ANISO_14_1_QUADS = 14, - ANISO_16_1_QUADS = 15, - MIP_VOL_ANISO_QUADS = 16, - ALIGN_2_QUADS = 17, - ALIGN_4_QUADS = 18, - PIX_0_QUAD = 19, - PIX_1_QUAD = 20, - PIX_2_QUAD = 21, - PIX_3_QUAD = 22, - PIX_4_QUAD = 23, - TP_MIPMAP_LOD0 = 24, - TP_MIPMAP_LOD1 = 25, - TP_MIPMAP_LOD2 = 26, - TP_MIPMAP_LOD3 = 27, - TP_MIPMAP_LOD4 = 28, - TP_MIPMAP_LOD5 = 29, - TP_MIPMAP_LOD6 = 30, - TP_MIPMAP_LOD7 = 31, - TP_MIPMAP_LOD8 = 32, - TP_MIPMAP_LOD9 = 33, - TP_MIPMAP_LOD10 = 34, - TP_MIPMAP_LOD11 = 35, - TP_MIPMAP_LOD12 = 36, - TP_MIPMAP_LOD13 = 37, - TP_MIPMAP_LOD14 = 38, -}; - -enum a2xx_tcm_perfcount_select { - QUAD0_RD_LAT_FIFO_EMPTY = 0, - QUAD0_RD_LAT_FIFO_4TH_FULL = 3, - QUAD0_RD_LAT_FIFO_HALF_FULL = 4, - QUAD0_RD_LAT_FIFO_FULL = 5, - QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, - READ_STARVED_QUAD0 = 28, - READ_STARVED = 32, - READ_STALLED_QUAD0 = 33, - READ_STALLED = 37, - VALID_READ_QUAD0 = 38, - TC_TP_STARVED_QUAD0 = 42, - TC_TP_STARVED = 46, -}; - -enum a2xx_tcf_perfcount_select { - VALID_CYCLES = 0, - SINGLE_PHASES = 1, - ANISO_PHASES = 2, - MIP_PHASES = 3, - VOL_PHASES = 4, - MIP_VOL_PHASES = 5, - MIP_ANISO_PHASES = 6, - VOL_ANISO_PHASES = 7, - ANISO_2_1_PHASES = 8, - ANISO_4_1_PHASES = 9, - ANISO_6_1_PHASES = 10, - ANISO_8_1_PHASES = 11, - ANISO_10_1_PHASES = 12, - ANISO_12_1_PHASES = 13, - ANISO_14_1_PHASES = 14, - ANISO_16_1_PHASES = 15, - MIP_VOL_ANISO_PHASES = 16, - ALIGN_2_PHASES = 17, - ALIGN_4_PHASES = 18, - TPC_BUSY = 19, - TPC_STALLED = 20, - TPC_STARVED = 21, - TPC_WORKING = 22, - TPC_WALKER_BUSY = 23, - TPC_WALKER_STALLED = 24, - TPC_WALKER_WORKING = 25, - TPC_ALIGNER_BUSY = 26, - TPC_ALIGNER_STALLED = 27, - TPC_ALIGNER_STALLED_BY_BLEND = 28, - TPC_ALIGNER_STALLED_BY_CACHE = 29, - TPC_ALIGNER_WORKING = 30, - TPC_BLEND_BUSY = 31, - TPC_BLEND_SYNC = 32, - TPC_BLEND_STARVED = 33, - TPC_BLEND_WORKING = 34, - OPCODE_0x00 = 35, - OPCODE_0x01 = 36, - OPCODE_0x04 = 37, - OPCODE_0x10 = 38, - OPCODE_0x11 = 39, - OPCODE_0x12 = 40, - OPCODE_0x13 = 41, - OPCODE_0x18 = 42, - OPCODE_0x19 = 43, - OPCODE_0x1A = 44, - OPCODE_OTHER = 45, - IN_FIFO_0_EMPTY = 56, - IN_FIFO_0_LT_HALF_FULL = 57, - IN_FIFO_0_HALF_FULL = 58, - IN_FIFO_0_FULL = 59, - IN_FIFO_TPC_EMPTY = 72, - IN_FIFO_TPC_LT_HALF_FULL = 73, - IN_FIFO_TPC_HALF_FULL = 74, - IN_FIFO_TPC_FULL = 75, - TPC_TC_XFC = 76, - TPC_TC_STATE = 77, - TC_STALL = 78, - QUAD0_TAPS = 79, - QUADS = 83, - TCA_SYNC_STALL = 84, - TAG_STALL = 85, - TCB_SYNC_STALL = 88, - TCA_VALID = 89, - PROBES_VALID = 90, - MISS_STALL = 91, - FETCH_FIFO_STALL = 92, - TCO_STALL = 93, - ANY_STALL = 94, - TAG_MISSES = 95, - TAG_HITS = 96, - SUB_TAG_MISSES = 97, - SET0_INVALIDATES = 98, - SET1_INVALIDATES = 99, - SET2_INVALIDATES = 100, - SET3_INVALIDATES = 101, - SET0_TAG_MISSES = 102, - SET1_TAG_MISSES = 103, - SET2_TAG_MISSES = 104, - SET3_TAG_MISSES = 105, - SET0_TAG_HITS = 106, - SET1_TAG_HITS = 107, - SET2_TAG_HITS = 108, - SET3_TAG_HITS = 109, - SET0_SUB_TAG_MISSES = 110, - SET1_SUB_TAG_MISSES = 111, - SET2_SUB_TAG_MISSES = 112, - SET3_SUB_TAG_MISSES = 113, - SET0_EVICT1 = 114, - SET0_EVICT2 = 115, - SET0_EVICT3 = 116, - SET0_EVICT4 = 117, - SET0_EVICT5 = 118, - SET0_EVICT6 = 119, - SET0_EVICT7 = 120, - SET0_EVICT8 = 121, - SET1_EVICT1 = 130, - SET1_EVICT2 = 131, - SET1_EVICT3 = 132, - SET1_EVICT4 = 133, - SET1_EVICT5 = 134, - SET1_EVICT6 = 135, - SET1_EVICT7 = 136, - SET1_EVICT8 = 137, - SET2_EVICT1 = 146, - SET2_EVICT2 = 147, - SET2_EVICT3 = 148, - SET2_EVICT4 = 149, - SET2_EVICT5 = 150, - SET2_EVICT6 = 151, - SET2_EVICT7 = 152, - SET2_EVICT8 = 153, - SET3_EVICT1 = 162, - SET3_EVICT2 = 163, - SET3_EVICT3 = 164, - SET3_EVICT4 = 165, - SET3_EVICT5 = 166, - SET3_EVICT6 = 167, - SET3_EVICT7 = 168, - SET3_EVICT8 = 169, - FF_EMPTY = 178, - FF_LT_HALF_FULL = 179, - FF_HALF_FULL = 180, - FF_FULL = 181, - FF_XFC = 182, - FF_STALLED = 183, - FG_MASKS = 184, - FG_LEFT_MASKS = 185, - FG_LEFT_MASK_STALLED = 186, - FG_LEFT_NOT_DONE_STALL = 187, - FG_LEFT_FG_STALL = 188, - FG_LEFT_SECTORS = 189, - FG0_REQUESTS = 195, - FG0_STALLED = 196, - MEM_REQ512 = 199, - MEM_REQ_SENT = 200, - MEM_LOCAL_READ_REQ = 202, - TC0_MH_STALLED = 203, -}; - -enum a2xx_sq_perfcnt_select { - SQ_PIXEL_VECTORS_SUB = 0, - SQ_VERTEX_VECTORS_SUB = 1, - SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, - SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, - SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, - SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, - SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, - SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, - SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, - SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, - SQ_EXPORT_CYCLES = 10, - SQ_ALU_CST_WRITTEN = 11, - SQ_TEX_CST_WRITTEN = 12, - SQ_ALU_CST_STALL = 13, - SQ_ALU_TEX_STALL = 14, - SQ_INST_WRITTEN = 15, - SQ_BOOLEAN_WRITTEN = 16, - SQ_LOOPS_WRITTEN = 17, - SQ_PIXEL_SWAP_IN = 18, - SQ_PIXEL_SWAP_OUT = 19, - SQ_VERTEX_SWAP_IN = 20, - SQ_VERTEX_SWAP_OUT = 21, - SQ_ALU_VTX_INST_ISSUED = 22, - SQ_TEX_VTX_INST_ISSUED = 23, - SQ_VC_VTX_INST_ISSUED = 24, - SQ_CF_VTX_INST_ISSUED = 25, - SQ_ALU_PIX_INST_ISSUED = 26, - SQ_TEX_PIX_INST_ISSUED = 27, - SQ_VC_PIX_INST_ISSUED = 28, - SQ_CF_PIX_INST_ISSUED = 29, - SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, - SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, - SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, - SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, - SQ_ALU_NOPS = 34, - SQ_PRED_SKIP = 35, - SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, - SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, - SQ_SYNC_TEX_STALL_VTX = 38, - SQ_SYNC_VC_STALL_VTX = 39, - SQ_CONSTANTS_USED_SIMD0 = 40, - SQ_CONSTANTS_SENT_SP_SIMD0 = 41, - SQ_GPR_STALL_VTX = 42, - SQ_GPR_STALL_PIX = 43, - SQ_VTX_RS_STALL = 44, - SQ_PIX_RS_STALL = 45, - SQ_SX_PC_FULL = 46, - SQ_SX_EXP_BUFF_FULL = 47, - SQ_SX_POS_BUFF_FULL = 48, - SQ_INTERP_QUADS = 49, - SQ_INTERP_ACTIVE = 50, - SQ_IN_PIXEL_STALL = 51, - SQ_IN_VTX_STALL = 52, - SQ_VTX_CNT = 53, - SQ_VTX_VECTOR2 = 54, - SQ_VTX_VECTOR3 = 55, - SQ_VTX_VECTOR4 = 56, - SQ_PIXEL_VECTOR1 = 57, - SQ_PIXEL_VECTOR23 = 58, - SQ_PIXEL_VECTOR4 = 59, - SQ_CONSTANTS_USED_SIMD1 = 60, - SQ_CONSTANTS_SENT_SP_SIMD1 = 61, - SQ_SX_MEM_EXP_FULL = 62, - SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, - SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, - SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, - SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, - SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, - SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, - SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, - SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, - SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, - SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, - SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, - SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, - SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, - SQ_PERFCOUNT_VTX_POP_THREAD = 76, - SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, - SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, - SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, - SQ_PERFCOUNT_PIX_POP_THREAD = 80, - SQ_SYNC_TEX_STALL_PIX = 81, - SQ_SYNC_VC_STALL_PIX = 82, - SQ_CONSTANTS_USED_SIMD2 = 83, - SQ_CONSTANTS_SENT_SP_SIMD2 = 84, - SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, - SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, - SQ_ALU0_FIFO_FULL_SIMD0 = 87, - SQ_ALU1_FIFO_FULL_SIMD0 = 88, - SQ_ALU0_FIFO_FULL_SIMD1 = 89, - SQ_ALU1_FIFO_FULL_SIMD1 = 90, - SQ_ALU0_FIFO_FULL_SIMD2 = 91, - SQ_ALU1_FIFO_FULL_SIMD2 = 92, - SQ_ALU0_FIFO_FULL_SIMD3 = 93, - SQ_ALU1_FIFO_FULL_SIMD3 = 94, - VC_PERF_STATIC = 95, - VC_PERF_STALLED = 96, - VC_PERF_STARVED = 97, - VC_PERF_SEND = 98, - VC_PERF_ACTUAL_STARVED = 99, - PIXEL_THREAD_0_ACTIVE = 100, - VERTEX_THREAD_0_ACTIVE = 101, - PIXEL_THREAD_0_NUMBER = 102, - VERTEX_THREAD_0_NUMBER = 103, - VERTEX_EVENT_NUMBER = 104, - PIXEL_EVENT_NUMBER = 105, - PTRBUFF_EF_PUSH = 106, - PTRBUFF_EF_POP_EVENT = 107, - PTRBUFF_EF_POP_NEW_VTX = 108, - PTRBUFF_EF_POP_DEALLOC = 109, - PTRBUFF_EF_POP_PVECTOR = 110, - PTRBUFF_EF_POP_PVECTOR_X = 111, - PTRBUFF_EF_POP_PVECTOR_VNZ = 112, - PTRBUFF_PB_DEALLOC = 113, - PTRBUFF_PI_STATE_PPB_POP = 114, - PTRBUFF_PI_RTR = 115, - PTRBUFF_PI_READ_EN = 116, - PTRBUFF_PI_BUFF_SWAP = 117, - PTRBUFF_SQ_FREE_BUFF = 118, - PTRBUFF_SQ_DEC = 119, - PTRBUFF_SC_VALID_CNTL_EVENT = 120, - PTRBUFF_SC_VALID_IJ_XFER = 121, - PTRBUFF_SC_NEW_VECTOR_1_Q = 122, - PTRBUFF_QUAL_NEW_VECTOR = 123, - PTRBUFF_QUAL_EVENT = 124, - PTRBUFF_END_BUFFER = 125, - PTRBUFF_FILL_QUAD = 126, - VERTS_WRITTEN_SPI = 127, - TP_FETCH_INSTR_EXEC = 128, - TP_FETCH_INSTR_REQ = 129, - TP_DATA_RETURN = 130, - SPI_WRITE_CYCLES_SP = 131, - SPI_WRITES_SP = 132, - SP_ALU_INSTR_EXEC = 133, - SP_CONST_ADDR_TO_SQ = 134, - SP_PRED_KILLS_TO_SQ = 135, - SP_EXPORT_CYCLES_TO_SX = 136, - SP_EXPORTS_TO_SX = 137, - SQ_CYCLES_ELAPSED = 138, - SQ_TCFS_OPT_ALLOC_EXEC = 139, - SQ_TCFS_NO_OPT_ALLOC = 140, - SQ_ALU0_NO_OPT_ALLOC = 141, - SQ_ALU1_NO_OPT_ALLOC = 142, - SQ_TCFS_ARB_XFC_CNT = 143, - SQ_ALU0_ARB_XFC_CNT = 144, - SQ_ALU1_ARB_XFC_CNT = 145, - SQ_TCFS_CFS_UPDATE_CNT = 146, - SQ_ALU0_CFS_UPDATE_CNT = 147, - SQ_ALU1_CFS_UPDATE_CNT = 148, - SQ_VTX_PUSH_THREAD_CNT = 149, - SQ_VTX_POP_THREAD_CNT = 150, - SQ_PIX_PUSH_THREAD_CNT = 151, - SQ_PIX_POP_THREAD_CNT = 152, - SQ_PIX_TOTAL = 153, - SQ_PIX_KILLED = 154, -}; - -enum a2xx_sx_perfcnt_select { - SX_EXPORT_VECTORS = 0, - SX_DUMMY_QUADS = 1, - SX_ALPHA_FAIL = 2, - SX_RB_QUAD_BUSY = 3, - SX_RB_COLOR_BUSY = 4, - SX_RB_QUAD_STALL = 5, - SX_RB_COLOR_STALL = 6, -}; - -enum a2xx_rbbm_perfcount1_sel { - RBBM1_COUNT = 0, - RBBM1_NRT_BUSY = 1, - RBBM1_RB_BUSY = 2, - RBBM1_SQ_CNTX0_BUSY = 3, - RBBM1_SQ_CNTX17_BUSY = 4, - RBBM1_VGT_BUSY = 5, - RBBM1_VGT_NODMA_BUSY = 6, - RBBM1_PA_BUSY = 7, - RBBM1_SC_CNTX_BUSY = 8, - RBBM1_TPC_BUSY = 9, - RBBM1_TC_BUSY = 10, - RBBM1_SX_BUSY = 11, - RBBM1_CP_COHER_BUSY = 12, - RBBM1_CP_NRT_BUSY = 13, - RBBM1_GFX_IDLE_STALL = 14, - RBBM1_INTERRUPT = 15, -}; - -enum a2xx_cp_perfcount_sel { - ALWAYS_COUNT = 0, - TRANS_FIFO_FULL = 1, - TRANS_FIFO_AF = 2, - RCIU_PFPTRANS_WAIT = 3, - RCIU_NRTTRANS_WAIT = 6, - CSF_NRT_READ_WAIT = 8, - CSF_I1_FIFO_FULL = 9, - CSF_I2_FIFO_FULL = 10, - CSF_ST_FIFO_FULL = 11, - CSF_RING_ROQ_FULL = 13, - CSF_I1_ROQ_FULL = 14, - CSF_I2_ROQ_FULL = 15, - CSF_ST_ROQ_FULL = 16, - MIU_TAG_MEM_FULL = 18, - MIU_WRITECLEAN = 19, - MIU_NRT_WRITE_STALLED = 22, - MIU_NRT_READ_STALLED = 23, - ME_WRITE_CONFIRM_FIFO_FULL = 24, - ME_VS_DEALLOC_FIFO_FULL = 25, - ME_PS_DEALLOC_FIFO_FULL = 26, - ME_REGS_VS_EVENT_FIFO_FULL = 27, - ME_REGS_PS_EVENT_FIFO_FULL = 28, - ME_REGS_CF_EVENT_FIFO_FULL = 29, - ME_MICRO_RB_STARVED = 30, - ME_MICRO_I1_STARVED = 31, - ME_MICRO_I2_STARVED = 32, - ME_MICRO_ST_STARVED = 33, - RCIU_RBBM_DWORD_SENT = 40, - ME_BUSY_CLOCKS = 41, - ME_WAIT_CONTEXT_AVAIL = 42, - PFP_TYPE0_PACKET = 43, - PFP_TYPE3_PACKET = 44, - CSF_RB_WPTR_NEQ_RPTR = 45, - CSF_I1_SIZE_NEQ_ZERO = 46, - CSF_I2_SIZE_NEQ_ZERO = 47, - CSF_RBI1I2_FETCHING = 48, -}; - -enum a2xx_rb_perfcnt_select { - RBPERF_CNTX_BUSY = 0, - RBPERF_CNTX_BUSY_MAX = 1, - RBPERF_SX_QUAD_STARVED = 2, - RBPERF_SX_QUAD_STARVED_MAX = 3, - RBPERF_GA_GC_CH0_SYS_REQ = 4, - RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, - RBPERF_GA_GC_CH1_SYS_REQ = 6, - RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, - RBPERF_MH_STARVED = 8, - RBPERF_MH_STARVED_MAX = 9, - RBPERF_AZ_BC_COLOR_BUSY = 10, - RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, - RBPERF_AZ_BC_Z_BUSY = 12, - RBPERF_AZ_BC_Z_BUSY_MAX = 13, - RBPERF_RB_SC_TILE_RTR_N = 14, - RBPERF_RB_SC_TILE_RTR_N_MAX = 15, - RBPERF_RB_SC_SAMP_RTR_N = 16, - RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, - RBPERF_RB_SX_QUAD_RTR_N = 18, - RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, - RBPERF_RB_SX_COLOR_RTR_N = 20, - RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, - RBPERF_RB_SC_SAMP_LZ_BUSY = 22, - RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, - RBPERF_ZXP_STALL = 24, - RBPERF_ZXP_STALL_MAX = 25, - RBPERF_EVENT_PENDING = 26, - RBPERF_EVENT_PENDING_MAX = 27, - RBPERF_RB_MH_VALID = 28, - RBPERF_RB_MH_VALID_MAX = 29, - RBPERF_SX_RB_QUAD_SEND = 30, - RBPERF_SX_RB_COLOR_SEND = 31, - RBPERF_SC_RB_TILE_SEND = 32, - RBPERF_SC_RB_SAMPLE_SEND = 33, - RBPERF_SX_RB_MEM_EXPORT = 34, - RBPERF_SX_RB_QUAD_EVENT = 35, - RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, - RBPERF_SC_RB_TILE_EVENT_ALL = 37, - RBPERF_RB_SC_EZ_SEND = 38, - RBPERF_RB_SX_INDEX_SEND = 39, - RBPERF_GMEM_INTFO_RD = 40, - RBPERF_GMEM_INTF1_RD = 41, - RBPERF_GMEM_INTFO_WR = 42, - RBPERF_GMEM_INTF1_WR = 43, - RBPERF_RB_CP_CONTEXT_DONE = 44, - RBPERF_RB_CP_CACHE_FLUSH = 45, - RBPERF_ZPASS_DONE = 46, - RBPERF_ZCMD_VALID = 47, - RBPERF_CCMD_VALID = 48, - RBPERF_ACCUM_GRANT = 49, - RBPERF_ACCUM_C0_GRANT = 50, - RBPERF_ACCUM_C1_GRANT = 51, - RBPERF_ACCUM_FULL_BE_WR = 52, - RBPERF_ACCUM_REQUEST_NO_GRANT = 53, - RBPERF_ACCUM_TIMEOUT_PULSE = 54, - RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, - RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, -}; - -enum adreno_mmu_clnt_beh { - BEH_NEVR = 0, - BEH_TRAN_RNG = 1, - BEH_TRAN_FLT = 2, -}; - -enum sq_tex_clamp { - SQ_TEX_WRAP = 0, - SQ_TEX_MIRROR = 1, - SQ_TEX_CLAMP_LAST_TEXEL = 2, - SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, - SQ_TEX_CLAMP_HALF_BORDER = 4, - SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, - SQ_TEX_CLAMP_BORDER = 6, - SQ_TEX_MIRROR_ONCE_BORDER = 7, -}; - -enum sq_tex_swiz { - SQ_TEX_X = 0, - SQ_TEX_Y = 1, - SQ_TEX_Z = 2, - SQ_TEX_W = 3, - SQ_TEX_ZERO = 4, - SQ_TEX_ONE = 5, -}; - -enum sq_tex_filter { - SQ_TEX_FILTER_POINT = 0, - SQ_TEX_FILTER_BILINEAR = 1, - SQ_TEX_FILTER_BASEMAP = 2, - SQ_TEX_FILTER_USE_FETCH_CONST = 3, -}; - -enum sq_tex_aniso_filter { - SQ_TEX_ANISO_FILTER_DISABLED = 0, - SQ_TEX_ANISO_FILTER_MAX_1_1 = 1, - SQ_TEX_ANISO_FILTER_MAX_2_1 = 2, - SQ_TEX_ANISO_FILTER_MAX_4_1 = 3, - SQ_TEX_ANISO_FILTER_MAX_8_1 = 4, - SQ_TEX_ANISO_FILTER_MAX_16_1 = 5, - SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7, -}; - -enum sq_tex_dimension { - SQ_TEX_DIMENSION_1D = 0, - SQ_TEX_DIMENSION_2D = 1, - SQ_TEX_DIMENSION_3D = 2, - SQ_TEX_DIMENSION_CUBE = 3, -}; - -enum sq_tex_border_color { - SQ_TEX_BORDER_COLOR_BLACK = 0, - SQ_TEX_BORDER_COLOR_WHITE = 1, - SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2, - SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3, -}; - -enum sq_tex_sign { - SQ_TEX_SIGN_UNISIGNED = 0, - SQ_TEX_SIGN_SIGNED = 1, - SQ_TEX_SIGN_UNISIGNED_BIASED = 2, - SQ_TEX_SIGN_GAMMA = 3, -}; - -enum sq_tex_endian { - SQ_TEX_ENDIAN_NONE = 0, - SQ_TEX_ENDIAN_8IN16 = 1, - SQ_TEX_ENDIAN_8IN32 = 2, - SQ_TEX_ENDIAN_16IN32 = 3, -}; - -enum sq_tex_clamp_policy { - SQ_TEX_CLAMP_POLICY_D3D = 0, - SQ_TEX_CLAMP_POLICY_OGL = 1, -}; - -enum sq_tex_num_format { - SQ_TEX_NUM_FORMAT_FRAC = 0, - SQ_TEX_NUM_FORMAT_INT = 1, -}; - -enum sq_tex_type { - SQ_TEX_TYPE_0 = 0, - SQ_TEX_TYPE_1 = 1, - SQ_TEX_TYPE_2 = 2, - SQ_TEX_TYPE_3 = 3, -}; - -#define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 - -#define REG_A2XX_RBBM_CNTL 0x0000003b - -#define REG_A2XX_RBBM_SOFT_RESET 0x0000003c - -#define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 - -#define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 - -#define REG_A2XX_MH_MMU_CONFIG 0x00000040 -#define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 -#define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 -#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 -#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 -static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 -#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 -static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 -#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 -static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 -#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 -static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 -#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 -static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 -#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 -static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 -#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 -static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 -#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 -static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 -#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 -static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 -#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 -static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; -} -#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 -#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 -static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) -{ - return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; -} - -#define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 -#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff -#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0 -static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) -{ - return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK; -} -#define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000 -#define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12 -static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) -{ - return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK; -} - -#define REG_A2XX_MH_MMU_PT_BASE 0x00000042 - -#define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 - -#define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 - -#define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 -#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001 -#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002 - -#define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 - -#define REG_A2XX_MH_MMU_MPU_END 0x00000047 - -#define REG_A2XX_NQWAIT_UNTIL 0x00000394 - -#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 - -#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 - -#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 - -#define REG_A2XX_RBBM_DEBUG 0x0000039b - -#define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c -#define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 -#define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 -#define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 -#define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 -#define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 -#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 -#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 -#define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 -#define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 -#define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 -#define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 -#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 -#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 -#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 -#define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 -#define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 -#define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 -#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 -#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 -#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 -#define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 -#define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 -#define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 -#define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 -#define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 -#define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 -#define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 -#define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 -#define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 -#define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 -#define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 -#define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 - -#define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d - -#define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 - -#define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 - -#define REG_A2XX_RBBM_READ_ERROR 0x000003b3 - -#define REG_A2XX_RBBM_INT_CNTL 0x000003b4 -#define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001 -#define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002 -#define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000 - -#define REG_A2XX_RBBM_INT_STATUS 0x000003b5 - -#define REG_A2XX_RBBM_INT_ACK 0x000003b6 - -#define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 -#define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020 -#define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000 -#define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000 -#define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000 - -#define REG_A2XX_RBBM_PERIPHID1 0x000003f9 - -#define REG_A2XX_RBBM_PERIPHID2 0x000003fa - -#define REG_A2XX_CP_PERFMON_CNTL 0x00000444 - -#define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 - -#define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 - -#define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 - -#define REG_A2XX_RBBM_STATUS 0x000005d0 -#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f -#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 -static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) -{ - return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; -} -#define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 -#define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 -#define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 -#define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 -#define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 -#define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 -#define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 -#define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 -#define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 -#define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 -#define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 -#define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 -#define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 -#define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 -#define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 -#define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 -#define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 -#define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 -#define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 - -#define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 -#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f -#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 -static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) -{ - return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; -} -#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 -#define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 -#define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 -#define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 -#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 -#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 -static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) -{ - return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; -} -#define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 -#define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 -#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 -#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 -#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 -static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) -{ - return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; -} -#define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 -#define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 -#define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 -#define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 -#define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 - -#define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42 -#define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001 -#define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002 -#define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004 - -#define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43 - -#define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44 - -#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54 - -#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55 - -#define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 -#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f -#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 -static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; -} -#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 -#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 -static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; -} - -static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } - -static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } - -static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } - -static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } - -#define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 - -#define REG_A2XX_PC_DEBUG_DATA 0x00000c39 - -#define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 - -#define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 - -#define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 - -#define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 - -#define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 - -#define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 -#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 -#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 -static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) -{ - return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; -} - -#define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 -#define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 -#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 -#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 -static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) -{ - return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; -} -#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 -#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 -static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) -{ - return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; -} - -#define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 - -#define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 -#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff -#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 -static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) -{ - return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; -} -#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 -#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 -static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) -{ - return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; -} - -#define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 - -#define REG_A2XX_SQ_INT_CNTL 0x00000d34 - -#define REG_A2XX_SQ_INT_STATUS 0x00000d35 - -#define REG_A2XX_SQ_INT_ACK 0x00000d36 - -#define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae - -#define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf - -#define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 - -#define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 - -#define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 - -#define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 - -#define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 - -#define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 - -#define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 - -#define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 - -#define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 - -#define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 - -#define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba - -#define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb - -#define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc - -#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd - -#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe - -#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf - -#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 - -#define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 - -#define REG_A2XX_TC_CNTL_STATUS 0x00000e00 -#define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 - -#define REG_A2XX_TP0_CHICKEN 0x00000e1e - -#define REG_A2XX_RB_BC_CONTROL 0x00000f01 -#define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 -#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 -#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 -static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) -{ - return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; -} -#define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 -#define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 -#define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 -#define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 -#define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 -#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 -#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 -static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) -{ - return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; -} -#define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 -#define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 -#define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 -#define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 -#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 -#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 -static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) -{ - return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; -} -#define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 -#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 -#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 -static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) -{ - return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; -} -#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 -#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 -static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) -{ - return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; -} -#define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 -#define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 -#define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 - -#define REG_A2XX_RB_EDRAM_INFO 0x00000f02 - -#define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 - -#define REG_A2XX_RB_DEBUG_DATA 0x00000f27 - -#define REG_A2XX_RB_SURFACE_INFO 0x00002000 -#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff -#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0 -static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) -{ - return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK; -} -#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000 -#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14 -static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) -{ - return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK; -} - -#define REG_A2XX_RB_COLOR_INFO 0x00002001 -#define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f -#define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 -static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) -{ - return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; -} -#define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 -#define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 -static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) -{ - return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; -} -#define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 -#define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 -#define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 -static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) -{ - return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; -} -#define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 -#define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 -static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) -{ - return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; -} -#define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 -#define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 -static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; -} - -#define REG_A2XX_RB_DEPTH_INFO 0x00002002 -#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 -#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 -static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) -{ - return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; -} -#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 -#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 -static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; -} - -#define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 - -#define REG_A2XX_COHER_DEST_BASE_0 0x00002006 - -#define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e -#define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff -#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 -static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) -{ - return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; -} -#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 -#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 -static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) -{ - return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; -} - -#define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f -#define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff -#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 -static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) -{ - return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; -} -#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 -#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 -static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) -{ - return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; -} - -#define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 -#define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff -#define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 -static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) -{ - return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; -} -#define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 -#define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 -static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) -{ - return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; -} -#define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 - -#define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 -#define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff -#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 -static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) -{ - return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; -} -#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 -#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 -static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) -{ - return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; -} - -#define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 -#define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff -#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 -static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) -{ - return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; -} -#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 -#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 -static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) -{ - return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; -} - -#define REG_A2XX_UNKNOWN_2010 0x00002010 - -#define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 - -#define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 - -#define REG_A2XX_VGT_INDX_OFFSET 0x00002102 - -#define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 - -#define REG_A2XX_RB_COLOR_MASK 0x00002104 -#define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 -#define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 -#define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 -#define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 - -#define REG_A2XX_RB_BLEND_RED 0x00002105 - -#define REG_A2XX_RB_BLEND_GREEN 0x00002106 - -#define REG_A2XX_RB_BLEND_BLUE 0x00002107 - -#define REG_A2XX_RB_BLEND_ALPHA 0x00002108 - -#define REG_A2XX_RB_FOG_COLOR 0x00002109 -#define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff -#define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 -static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) -{ - return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; -} -#define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 -#define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 -static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) -{ - return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; -} -#define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 -#define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 -static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) -{ - return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; -} - -#define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c -#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff -#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 -static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) -{ - return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; -} -#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 -#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 -static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) -{ - return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; -} -#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 -#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 -static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) -{ - return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; -} - -#define REG_A2XX_RB_STENCILREFMASK 0x0000210d -#define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff -#define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 -static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) -{ - return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; -} -#define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 -#define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 -static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) -{ - return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; -} -#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 -#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 -static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) -{ - return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; -} - -#define REG_A2XX_RB_ALPHA_REF 0x0000210e - -#define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f -#define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff -#define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 -static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) -{ - return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; -} - -#define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 -#define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff -#define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 -static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) -{ - return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; -} - -#define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 -#define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff -#define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 -static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) -{ - return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; -} - -#define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 -#define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff -#define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 -static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) -{ - return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; -} - -#define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 -#define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff -#define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 -static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) -{ - return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; -} - -#define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 -#define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff -#define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 -static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) -{ - return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; -} - -#define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 -#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff -#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 -static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) -{ - return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; -} -#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 -#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 -static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) -{ - return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; -} -#define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 -#define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 -#define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 -#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 -#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 -#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 -static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) -{ - return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; -} -#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 -#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 -static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) -{ - return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; -} -#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 -#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 -static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) -{ - return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; -} -#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 - -#define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 -#define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 -#define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 -#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c -#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 -static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) -{ - return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; -} -#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 -#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 -static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) -{ - return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; -} -#define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 -#define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 -#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 - -#define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 -#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff -#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 -static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) -{ - return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; -} -#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 -#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 -static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) -{ - return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; -} - -#define REG_A2XX_SQ_WRAPPING_0 0x00002183 -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 -static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; -} -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 -static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; -} -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 -static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; -} -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 -static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; -} -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 -static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; -} -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 -static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; -} -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 -static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; -} -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 -#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 -static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; -} - -#define REG_A2XX_SQ_WRAPPING_1 0x00002184 -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 -static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; -} -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 -static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; -} -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 -static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; -} -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 -static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; -} -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 -static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; -} -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 -static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; -} -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 -static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; -} -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 -#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 -static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) -{ - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; -} - -#define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 -#define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff -#define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 -static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) -{ - return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; -} -#define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 -#define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 -static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) -{ - return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; -} - -#define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 -#define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff -#define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 -static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) -{ - return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; -} -#define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 -#define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 -static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) -{ - return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; -} - -#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 - -#define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc -#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f -#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 -static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; -} -#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 -#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 -static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; -} -#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 -#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 -static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; -} -#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 -#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 -static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) -{ - return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; -} -#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 -#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 -#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 -#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 -#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 -static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) -{ - return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; -} - -#define REG_A2XX_VGT_IMMED_DATA 0x000021fd - -#define REG_A2XX_RB_DEPTHCONTROL 0x00002200 -#define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 -#define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 -#define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 -#define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 -#define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 -#define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 -static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) -{ - return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; -} -#define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 -#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 -#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 -static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) -{ - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; -} -#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 -#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 -static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) -{ - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; -} -#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 -#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 -static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) -{ - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; -} -#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 -#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 -static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) -{ - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; -} -#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 -#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 -static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) -{ - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; -} -#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 -#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 -static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; -} -#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 -#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 -static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) -{ - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; -} -#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 -#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 -static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; -} - -#define REG_A2XX_RB_BLEND_CONTROL 0x00002201 -#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f -#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 -static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) -{ - return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; -} -#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 -#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 -static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) -{ - return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; -} -#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 -#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 -static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) -{ - return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; -} -#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 -#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 -static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) -{ - return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; -} -#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 -#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 -static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) -{ - return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; -} -#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 -#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 -static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) -{ - return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; -} -#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 -#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 - -#define REG_A2XX_RB_COLORCONTROL 0x00002202 -#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 -#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 -static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) -{ - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; -} -#define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 -#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 -#define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 -#define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 -#define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 -#define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 -#define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 -static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) -{ - return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; -} -#define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 -#define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 -static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) -{ - return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; -} -#define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 -#define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 -static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) -{ - return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; -} -#define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 -#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 -#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 -static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) -{ - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; -} -#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 -#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 -static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) -{ - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; -} -#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 -#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 -static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) -{ - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; -} -#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 -#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 -static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) -{ - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; -} - -#define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 -#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 -#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 -static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) -{ - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; -} -#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 -#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 -static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) -{ - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; -} -#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 -#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 -static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) -{ - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; -} - -#define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 -#define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 -#define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 -#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 -#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 -static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) -{ - return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; -} -#define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 -#define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 -#define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 -#define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 -#define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 - -#define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 -#define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 -#define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 -#define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 -#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 -#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 -static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) -{ - return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; -} -#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 -#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 -static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; -} -#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 -#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 -static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; -} -#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 -#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 -#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 -#define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 -#define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 -#define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 -#define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 -#define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 -#define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 -#define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 -#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 -#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 -#define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 -#define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 -#define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 -#define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 - -#define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 -#define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 -#define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 -#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 -#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 -#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 -#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 -#define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 -#define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 -#define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 -#define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 - -#define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 -#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 -#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 -static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) -{ - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; -} -#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 -#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 -static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) -{ - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; -} -#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 -#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 -static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) -{ - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; -} - -#define REG_A2XX_RB_MODECONTROL 0x00002208 -#define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 -#define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 -static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) -{ - return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; -} - -#define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 - -#define REG_A2XX_RB_SAMPLE_POS 0x0000220a - -#define REG_A2XX_CLEAR_COLOR 0x0000220b -#define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff -#define A2XX_CLEAR_COLOR_RED__SHIFT 0 -static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) -{ - return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; -} -#define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 -#define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 -static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) -{ - return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; -} -#define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 -#define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 -static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) -{ - return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; -} -#define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 -#define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 -static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) -{ - return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; -} - -#define REG_A2XX_A220_GRAS_CONTROL 0x00002210 - -#define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 -#define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff -#define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 -static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) -{ - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; -} -#define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 -#define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 -static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) -{ - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; -} - -#define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 -#define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff -#define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 -static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) -{ - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; -} -#define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 -#define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 -static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) -{ - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; -} - -#define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 -#define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff -#define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 -static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) -{ - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; -} - -#define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 -#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff -#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 -static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) -{ - return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; -} -#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 -#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 -static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) -{ - return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; -} -#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 -#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 -static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) -{ - return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; -} -#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 -#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 -static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) -{ - return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; -} - -#define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 -#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 -#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e -#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 -static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) -{ - return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; -} -#define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 - -#define REG_A2XX_VGT_ENHANCE 0x00002294 - -#define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 -#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff -#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 -static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) -{ - return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; -} -#define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 -#define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 -#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 - -#define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 -#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 -#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 -static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) -{ - return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; -} -#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 -#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 -static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) -{ - return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; -} - -#define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 -#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 -#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 -static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) -{ - return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; -} -#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 -#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 -static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) -{ - return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; -} -#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 -#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 -static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) -{ - return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; -} - -#define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 -#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff -#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 -static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) -{ - return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; -} - -#define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 -#define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff -#define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 -static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) -{ - return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; -} - -#define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 -#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff -#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 -static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) -{ - return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; -} - -#define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 -#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff -#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 -static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) -{ - return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; -} - -#define REG_A2XX_SQ_VS_CONST 0x00002307 -#define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff -#define A2XX_SQ_VS_CONST_BASE__SHIFT 0 -static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) -{ - return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; -} -#define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 -#define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 -static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) -{ - return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; -} - -#define REG_A2XX_SQ_PS_CONST 0x00002308 -#define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff -#define A2XX_SQ_PS_CONST_BASE__SHIFT 0 -static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) -{ - return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; -} -#define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 -#define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 -static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) -{ - return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; -} - -#define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 - -#define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a - -#define REG_A2XX_PA_SC_AA_MASK 0x00002312 - -#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 -#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 -#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 -static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) -{ - return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; -} - -#define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 -#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 -#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 -static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) -{ - return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; -} - -#define REG_A2XX_RB_COPY_CONTROL 0x00002318 -#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 -#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 -static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) -{ - return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; -} -#define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 -#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 -#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 -static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) -{ - return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; -} - -#define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 - -#define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a -#define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff -#define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 -static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; -} - -#define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b -#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 -#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 -static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) -{ - return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; -} -#define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 -#define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 -#define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 -static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) -{ - return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; -} -#define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 -#define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 -static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) -{ - return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; -} -#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 -#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 -static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) -{ - return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; -} -#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 -#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 -static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) -{ - return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; -} -#define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 -#define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 -#define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 -#define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 - -#define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c -#define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff -#define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 -static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) -{ - return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; -} -#define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 -#define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 -static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) -{ - return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; -} - -#define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d - -#define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 - -#define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 - -#define REG_A2XX_A225_GRAS_UCP0X 0x00002340 - -#define REG_A2XX_A225_GRAS_UCP5W 0x00002357 - -#define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 - -#define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 - -#define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 - -#define REG_A2XX_SQ_CONSTANT_0 0x00004000 - -#define REG_A2XX_SQ_FETCH_0 0x00004800 - -#define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 - -#define REG_A2XX_SQ_CF_LOOP 0x00004908 - -#define REG_A2XX_COHER_SIZE_PM4 0x00000a29 - -#define REG_A2XX_COHER_BASE_PM4 0x00000a2a - -#define REG_A2XX_COHER_STATUS_PM4 0x00000a2b - -#define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88 - -#define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89 - -#define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a - -#define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b - -#define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c - -#define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d - -#define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e - -#define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f - -#define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90 - -#define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91 - -#define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92 - -#define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93 - -#define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98 - -#define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99 - -#define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a - -#define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48 - -#define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49 - -#define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a - -#define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b - -#define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c - -#define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e - -#define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50 - -#define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52 - -#define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d - -#define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f - -#define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51 - -#define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53 - -#define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05 - -#define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08 - -#define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06 - -#define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09 - -#define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07 - -#define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a - -#define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f - -#define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20 - -#define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21 - -#define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22 - -#define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23 - -#define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24 - -#define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54 - -#define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57 - -#define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55 - -#define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58 - -#define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56 - -#define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59 - -#define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a - -#define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d - -#define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60 - -#define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63 - -#define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66 - -#define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69 - -#define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c - -#define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f - -#define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72 - -#define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75 - -#define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78 - -#define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b - -#define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b - -#define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e - -#define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61 - -#define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64 - -#define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67 - -#define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a - -#define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d - -#define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70 - -#define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73 - -#define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76 - -#define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79 - -#define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c - -#define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c - -#define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f - -#define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62 - -#define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65 - -#define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68 - -#define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b - -#define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e - -#define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71 - -#define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74 - -#define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77 - -#define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a - -#define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d - -#define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8 - -#define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9 - -#define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca - -#define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb - -#define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc - -#define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd - -#define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce - -#define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf - -#define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0 - -#define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1 - -#define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2 - -#define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3 - -#define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4 - -#define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8 - -#define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9 - -#define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46 - -#define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a - -#define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47 - -#define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b - -#define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48 - -#define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c - -#define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49 - -#define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d - -#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 - -#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 - -#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 - -#define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 - -#define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 - -#define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 - -#define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04 - -#define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08 - -#define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09 - -#define REG_A2XX_SQ_TEX_0 0x00000000 -#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003 -#define A2XX_SQ_TEX_0_TYPE__SHIFT 0 -static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) -{ - return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK; -} -#define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c -#define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2 -static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) -{ - return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK; -} -#define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030 -#define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4 -static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) -{ - return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK; -} -#define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0 -#define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6 -static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) -{ - return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK; -} -#define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300 -#define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8 -static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) -{ - return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK; -} -#define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 -#define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 -static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) -{ - return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; -} -#define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 -#define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 -static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) -{ - return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; -} -#define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 -#define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 -static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) -{ - return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; -} -#define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000 -#define A2XX_SQ_TEX_0_PITCH__SHIFT 22 -static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; -} -#define A2XX_SQ_TEX_0_TILED 0x00000002 - -#define REG_A2XX_SQ_TEX_1 0x00000001 -#define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f -#define A2XX_SQ_TEX_1_FORMAT__SHIFT 0 -static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) -{ - return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK; -} -#define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0 -#define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6 -static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) -{ - return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK; -} -#define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300 -#define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8 -static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK; -} -#define A2XX_SQ_TEX_1_STACKED 0x00000400 -#define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800 -#define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11 -static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) -{ - return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK; -} -#define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000 -#define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12 -static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; -} - -#define REG_A2XX_SQ_TEX_2 0x00000002 -#define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff -#define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 -static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; -} -#define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 -#define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 -static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; -} -#define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000 -#define A2XX_SQ_TEX_2_DEPTH__SHIFT 26 -static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK; -} - -#define REG_A2XX_SQ_TEX_3 0x00000003 -#define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001 -#define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0 -static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) -{ - return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK; -} -#define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e -#define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 -static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) -{ - return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; -} -#define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 -#define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 -static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) -{ - return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; -} -#define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 -#define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 -static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) -{ - return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; -} -#define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 -#define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 -static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) -{ - return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; -} -#define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000 -#define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13 -static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK; -} -#define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 -#define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 -static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) -{ - return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; -} -#define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 -#define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 -static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) -{ - return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; -} -#define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000 -#define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23 -static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) -{ - return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK; -} -#define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000 -#define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25 -static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) -{ - return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK; -} -#define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000 -#define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31 -static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK; -} - -#define REG_A2XX_SQ_TEX_4 0x00000004 -#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001 -#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0 -static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) -{ - return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK; -} -#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002 -#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1 -static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) -{ - return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK; -} -#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c -#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2 -static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK; -} -#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0 -#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6 -static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK; -} -#define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400 -#define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800 -#define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000 -#define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12 -static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) -{ - return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK; -} -#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000 -#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22 -static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK; -} -#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000 -#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27 -static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK; -} - -#define REG_A2XX_SQ_TEX_5 0x00000005 -#define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003 -#define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0 -static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) -{ - return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK; -} -#define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004 -#define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018 -#define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3 -static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) -{ - return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK; -} -#define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0 -#define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5 -static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) -{ - return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK; -} -#define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600 -#define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9 -static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) -{ - return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK; -} -#define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800 -#define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000 -#define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12 -static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; -} - - -#endif /* A2XX_XML */ diff --git a/src/freedreno/registers/a3xx.xml b/src/freedreno/registers/a3xx.xml new file mode 100644 index 00000000000..bf93b0cb009 --- /dev/null +++ b/src/freedreno/registers/a3xx.xml @@ -0,0 +1,1754 @@ +<?xml version="1.0" encoding="UTF-8"?> +<database xmlns="http://nouveau.freedesktop.org/" +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" +xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> +<import file="freedreno_copyright.xml"/> +<import file="adreno/adreno_common.xml"/> +<import file="adreno/adreno_pm4.xml"/> + +<enum name="a3xx_tile_mode"> + <value name="LINEAR" value="0"/> + <value name="TILE_4X4" value="1"/> <!-- "normal" case for textures --> + <value name="TILE_32X32" value="2"/> <!-- only used in GMEM --> + <value name="TILE_4X2" value="3"/> <!-- only used for CrCb --> +</enum> + +<enum name="a3xx_state_block_id"> + <value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/> + <value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/> + <value name="HLSQ_BLOCK_ID_SP_VS" value="4"/> + <value name="HLSQ_BLOCK_ID_SP_FS" value="6"/> +</enum> + +<enum name="a3xx_cache_opcode"> + <value name="INVALIDATE" value="1"/> +</enum> + +<enum name="a3xx_vtx_fmt"> + <value name="VFMT_32_FLOAT" value="0x0"/> + <value name="VFMT_32_32_FLOAT" value="0x1"/> + <value name="VFMT_32_32_32_FLOAT" value="0x2"/> + <value name="VFMT_32_32_32_32_FLOAT" value="0x3"/> + + <value name="VFMT_16_FLOAT" value="0x4"/> + <value name="VFMT_16_16_FLOAT" value="0x5"/> + <value name="VFMT_16_16_16_FLOAT" value="0x6"/> + <value name="VFMT_16_16_16_16_FLOAT" value="0x7"/> + + <value name="VFMT_32_FIXED" value="0x8"/> + <value name="VFMT_32_32_FIXED" value="0x9"/> + <value name="VFMT_32_32_32_FIXED" value="0xa"/> + <value name="VFMT_32_32_32_32_FIXED" value="0xb"/> + + <value name="VFMT_16_SINT" value="0x10"/> + <value name="VFMT_16_16_SINT" value="0x11"/> + <value name="VFMT_16_16_16_SINT" value="0x12"/> + <value name="VFMT_16_16_16_16_SINT" value="0x13"/> + <value name="VFMT_16_UINT" value="0x14"/> + <value name="VFMT_16_16_UINT" value="0x15"/> + <value name="VFMT_16_16_16_UINT" value="0x16"/> + <value name="VFMT_16_16_16_16_UINT" value="0x17"/> + <value name="VFMT_16_SNORM" value="0x18"/> + <value name="VFMT_16_16_SNORM" value="0x19"/> + <value name="VFMT_16_16_16_SNORM" value="0x1a"/> + <value name="VFMT_16_16_16_16_SNORM" value="0x1b"/> + <value name="VFMT_16_UNORM" value="0x1c"/> + <value name="VFMT_16_16_UNORM" value="0x1d"/> + <value name="VFMT_16_16_16_UNORM" value="0x1e"/> + <value name="VFMT_16_16_16_16_UNORM" value="0x1f"/> + + <!-- seems to be no NORM variants for 32bit.. --> + <value name="VFMT_32_UINT" value="0x20"/> + <value name="VFMT_32_32_UINT" value="0x21"/> + <value name="VFMT_32_32_32_UINT" value="0x22"/> + <value name="VFMT_32_32_32_32_UINT" value="0x23"/> + <value name="VFMT_32_SINT" value="0x24"/> + <value name="VFMT_32_32_SINT" value="0x25"/> + <value name="VFMT_32_32_32_SINT" value="0x26"/> + <value name="VFMT_32_32_32_32_SINT" value="0x27"/> + + <value name="VFMT_8_UINT" value="0x28"/> + <value name="VFMT_8_8_UINT" value="0x29"/> + <value name="VFMT_8_8_8_UINT" value="0x2a"/> + <value name="VFMT_8_8_8_8_UINT" value="0x2b"/> + <value name="VFMT_8_UNORM" value="0x2c"/> + <value name="VFMT_8_8_UNORM" value="0x2d"/> + <value name="VFMT_8_8_8_UNORM" value="0x2e"/> + <value name="VFMT_8_8_8_8_UNORM" value="0x2f"/> + <value name="VFMT_8_SINT" value="0x30"/> + <value name="VFMT_8_8_SINT" value="0x31"/> + <value name="VFMT_8_8_8_SINT" value="0x32"/> + <value name="VFMT_8_8_8_8_SINT" value="0x33"/> + <value name="VFMT_8_SNORM" value="0x34"/> + <value name="VFMT_8_8_SNORM" value="0x35"/> + <value name="VFMT_8_8_8_SNORM" value="0x36"/> + <value name="VFMT_8_8_8_8_SNORM" value="0x37"/> + <value name="VFMT_10_10_10_2_UINT" value="0x38"/> + <value name="VFMT_10_10_10_2_UNORM" value="0x39"/> + <value name="VFMT_10_10_10_2_SINT" value="0x3a"/> + <value name="VFMT_10_10_10_2_SNORM" value="0x3b"/> + <value name="VFMT_2_10_10_10_UINT" value="0x3c"/> + <value name="VFMT_2_10_10_10_UNORM" value="0x3d"/> + <value name="VFMT_2_10_10_10_SINT" value="0x3e"/> + <value name="VFMT_2_10_10_10_SNORM" value="0x3f"/> +</enum> + +<enum name="a3xx_tex_fmt"> + <value name="TFMT_5_6_5_UNORM" value="0x4"/> + <value name="TFMT_5_5_5_1_UNORM" value="0x5"/> + <value name="TFMT_4_4_4_4_UNORM" value="0x7"/> + <value name="TFMT_Z16_UNORM" value="0x9"/> + <value name="TFMT_X8Z24_UNORM" value="0xa"/> + <value name="TFMT_Z32_FLOAT" value="0xb"/> + + <!-- + The NV12 tiled/linear formats seem to require gang'd sampler + slots (ie. sampler state N plus N+1) for Y and UV planes. + They fetch yuv in single sam instruction, but still require + colorspace conversion in the shader. + --> + <value name="TFMT_UV_64X32" value="0x10"/> + <value name="TFMT_VU_64X32" value="0x11"/> + <value name="TFMT_Y_64X32" value="0x12"/> + <value name="TFMT_NV12_64X32" value="0x13"/> + <value name="TFMT_UV_LINEAR" value="0x14"/> + <value name="TFMT_VU_LINEAR" value="0x15"/> + <value name="TFMT_Y_LINEAR" value="0x16"/> + <value name="TFMT_NV12_LINEAR" value="0x17"/> + <value name="TFMT_I420_Y" value="0x18"/> + <value name="TFMT_I420_U" value="0x1a"/> + <value name="TFMT_I420_V" value="0x1b"/> + + <value name="TFMT_ATC_RGB" value="0x20"/> + <value name="TFMT_ATC_RGBA_EXPLICIT" value="0x21"/> + <value name="TFMT_ETC1" value="0x22"/> + <value name="TFMT_ATC_RGBA_INTERPOLATED" value="0x23"/> + + <value name="TFMT_DXT1" value="0x24"/> + <value name="TFMT_DXT3" value="0x25"/> + <value name="TFMT_DXT5" value="0x26"/> + + <value name="TFMT_2_10_10_10_UNORM" value="0x28"/> + <value name="TFMT_10_10_10_2_UNORM" value="0x29"/> + <value name="TFMT_9_9_9_E5_FLOAT" value="0x2a"/> + <value name="TFMT_11_11_10_FLOAT" value="0x2b"/> + <value name="TFMT_A8_UNORM" value="0x2c"/> <!-- GL_ALPHA --> + <value name="TFMT_L8_UNORM" value="0x2d"/> + <value name="TFMT_L8_A8_UNORM" value="0x2f"/> <!-- GL_LUMINANCE_ALPHA --> + + <!-- + NOTE: GL_ALPHA and GL_LUMINANCE_ALPHA aren't handled in a similar way + to float16, float32.. but they seem to use non-standard swizzle too.. + perhaps we can ditch that if the pattern follows of 0xn0, 0xn1, 0xn2, + 0xn3 for 1, 2, 3, 4 components respectively.. + + Only formats filled in below are the ones that have been observed by + the blob or tested.. you can guess what the missing ones are.. + --> + + <value name="TFMT_8_UNORM" value="0x30"/> <!-- GL_LUMINANCE --> + <value name="TFMT_8_8_UNORM" value="0x31"/> + <value name="TFMT_8_8_8_UNORM" value="0x32"/> + <value name="TFMT_8_8_8_8_UNORM" value="0x33"/> + + <value name="TFMT_8_SNORM" value="0x34"/> + <value name="TFMT_8_8_SNORM" value="0x35"/> + <value name="TFMT_8_8_8_SNORM" value="0x36"/> + <value name="TFMT_8_8_8_8_SNORM" value="0x37"/> + + <value name="TFMT_8_UINT" value="0x38"/> + <value name="TFMT_8_8_UINT" value="0x39"/> + <value name="TFMT_8_8_8_UINT" value="0x3a"/> + <value name="TFMT_8_8_8_8_UINT" value="0x3b"/> + + <value name="TFMT_8_SINT" value="0x3c"/> + <value name="TFMT_8_8_SINT" value="0x3d"/> + <value name="TFMT_8_8_8_SINT" value="0x3e"/> + <value name="TFMT_8_8_8_8_SINT" value="0x3f"/> + + <value name="TFMT_16_FLOAT" value="0x40"/> + <value name="TFMT_16_16_FLOAT" value="0x41"/> + <!-- TFMT_FLOAT_16_16_16 --> + <value name="TFMT_16_16_16_16_FLOAT" value="0x43"/> + + <value name="TFMT_16_UINT" value="0x44"/> + <value name="TFMT_16_16_UINT" value="0x45"/> + <value name="TFMT_16_16_16_16_UINT" value="0x47"/> + + <value name="TFMT_16_SINT" value="0x48"/> + <value name="TFMT_16_16_SINT" value="0x49"/> + <value name="TFMT_16_16_16_16_SINT" value="0x4b"/> + + <value name="TFMT_16_UNORM" value="0x4c"/> + <value name="TFMT_16_16_UNORM" value="0x4d"/> + <value name="TFMT_16_16_16_16_UNORM" value="0x4f"/> + + <value name="TFMT_16_SNORM" value="0x50"/> + <value name="TFMT_16_16_SNORM" value="0x51"/> + <value name="TFMT_16_16_16_16_SNORM" value="0x53"/> + + <value name="TFMT_32_FLOAT" value="0x54"/> + <value name="TFMT_32_32_FLOAT" value="0x55"/> + <!-- TFMT_32_32_32_FLOAT --> + <value name="TFMT_32_32_32_32_FLOAT" value="0x57"/> + + <value name="TFMT_32_UINT" value="0x58"/> + <value name="TFMT_32_32_UINT" value="0x59"/> + <value name="TFMT_32_32_32_32_UINT" value="0x5b"/> + + <value name="TFMT_32_SINT" value="0x5c"/> + <value name="TFMT_32_32_SINT" value="0x5d"/> + <value name="TFMT_32_32_32_32_SINT" value="0x5f"/> + + <value name="TFMT_2_10_10_10_UINT" value="0x60"/> + <value name="TFMT_10_10_10_2_UINT" value="0x61"/> + + <value name="TFMT_ETC2_RG11_SNORM" value="0x70"/> + <value name="TFMT_ETC2_RG11_UNORM" value="0x71"/> + <value name="TFMT_ETC2_R11_SNORM" value="0x72"/> + <value name="TFMT_ETC2_R11_UNORM" value="0x73"/> + <value name="TFMT_ETC2_RGBA8" value="0x74"/> + <value name="TFMT_ETC2_RGB8A1" value="0x75"/> + <value name="TFMT_ETC2_RGB8" value="0x76"/> +</enum> + +<enum name="a3xx_tex_fetchsize"> + <doc> + Size pixel to fetch, in bytes. Doesn't seem to be required, setting + it to 0x0 seems to work ok, but may be less optimal. + </doc> + <value name="TFETCH_DISABLE" value="0"/> + <value name="TFETCH_1_BYTE" value="1"/> + <value name="TFETCH_2_BYTE" value="2"/> + <value name="TFETCH_4_BYTE" value="3"/> + <value name="TFETCH_8_BYTE" value="4"/> + <value name="TFETCH_16_BYTE" value="5"/> +</enum> + +<enum name="a3xx_color_fmt"> + <value name="RB_R5G6B5_UNORM" value="0x00"/> + <value name="RB_R5G5B5A1_UNORM" value="0x01"/> + <value name="RB_R4G4B4A4_UNORM" value="0x03"/> + <value name="RB_R8G8B8_UNORM" value="0x04"/> + <value name="RB_R8G8B8A8_UNORM" value="0x08"/> + <value name="RB_R8G8B8A8_SNORM" value="0x09"/> + <value name="RB_R8G8B8A8_UINT" value="0x0a"/> + <value name="RB_R8G8B8A8_SINT" value="0x0b"/> + <value name="RB_R8G8_UNORM" value="0x0c"/> + <value name="RB_R8G8_SNORM" value="0x0d"/> + <value name="RB_R8_UINT" value="0x0e"/> <!-- also used for R8G8_UINT? --> + <value name="RB_R8_SINT" value="0x0f"/> <!-- also used for R8G8_SINT? --> + <value name="RB_R10G10B10A2_UNORM" value="0x10"/> + <value name="RB_A2R10G10B10_UNORM" value="0x11"/> + <value name="RB_R10G10B10A2_UINT" value="0x12"/> + <value name="RB_A2R10G10B10_UINT" value="0x13"/> + + <value name="RB_A8_UNORM" value="0x14"/> + <value name="RB_R8_UNORM" value="0x15"/> + + <value name="RB_R16_FLOAT" value="0x18"/> + <value name="RB_R16G16_FLOAT" value="0x19"/> + <value name="RB_R16G16B16A16_FLOAT" value="0x1b"/> <!-- GL_HALF_FLOAT_OES --> + <value name="RB_R11G11B10_FLOAT" value="0x1c"/> + + <value name="RB_R16_SNORM" value="0x20"/> + <value name="RB_R16G16_SNORM" value="0x21"/> + <value name="RB_R16G16B16A16_SNORM" value="0x23"/> + + <value name="RB_R16_UNORM" value="0x24"/> + <value name="RB_R16G16_UNORM" value="0x25"/> + <value name="RB_R16G16B16A16_UNORM" value="0x27"/> + + <value name="RB_R16_SINT" value="0x28"/> + <value name="RB_R16G16_SINT" value="0x29"/> + <value name="RB_R16G16B16A16_SINT" value="0x2b"/> + + <value name="RB_R16_UINT" value="0x2c"/> + <value name="RB_R16G16_UINT" value="0x2d"/> + <value name="RB_R16G16B16A16_UINT" value="0x2f"/> + + <value name="RB_R32_FLOAT" value="0x30"/> + <value name="RB_R32G32_FLOAT" value="0x31"/> + <value name="RB_R32G32B32A32_FLOAT" value="0x33"/> <!-- GL_FLOAT --> + + <value name="RB_R32_SINT" value="0x34"/> + <value name="RB_R32G32_SINT" value="0x35"/> + <value name="RB_R32G32B32A32_SINT" value="0x37"/> + + <value name="RB_R32_UINT" value="0x38"/> + <value name="RB_R32G32_UINT" value="0x39"/> + <value name="RB_R32G32B32A32_UINT" value="0x3b"/> +</enum> + +<enum name="a3xx_cp_perfcounter_select"> + <value value="0x00" name="CP_ALWAYS_COUNT"/> + <value value="0x03" name="CP_AHB_PFPTRANS_WAIT"/> + <value value="0x06" name="CP_AHB_NRTTRANS_WAIT"/> + <value value="0x08" name="CP_CSF_NRT_READ_WAIT"/> + <value value="0x09" name="CP_CSF_I1_FIFO_FULL"/> + <value value="0x0a" name="CP_CSF_I2_FIFO_FULL"/> + <value value="0x0b" name="CP_CSF_ST_FIFO_FULL"/> + <value value="0x0c" name="CP_RESERVED_12"/> + <value value="0x0d" name="CP_CSF_RING_ROQ_FULL"/> + <value value="0x0e" name="CP_CSF_I1_ROQ_FULL"/> + <value value="0x0f" name="CP_CSF_I2_ROQ_FULL"/> + <value value="0x10" name="CP_CSF_ST_ROQ_FULL"/> + <value value="0x11" name="CP_RESERVED_17"/> + <value value="0x12" name="CP_MIU_TAG_MEM_FULL"/> + <value value="0x16" name="CP_MIU_NRT_WRITE_STALLED"/> + <value value="0x17" name="CP_MIU_NRT_READ_STALLED"/> + <value value="0x1a" name="CP_ME_REGS_RB_DONE_FIFO_FULL"/> + <value value="0x1b" name="CP_ME_REGS_VS_EVENT_FIFO_FULL"/> + <value value="0x1c" name="CP_ME_REGS_PS_EVENT_FIFO_FULL"/> + <value value="0x1d" name="CP_ME_REGS_CF_EVENT_FIFO_FULL"/> + <value value="0x1e" name="CP_ME_MICRO_RB_STARVED"/> + <value value="0x28" name="CP_AHB_RBBM_DWORD_SENT"/> + <value value="0x29" name="CP_ME_BUSY_CLOCKS"/> + <value value="0x2a" name="CP_ME_WAIT_CONTEXT_AVAIL"/> + <value value="0x2b" name="CP_PFP_TYPE0_PACKET"/> + <value value="0x2c" name="CP_PFP_TYPE3_PACKET"/> + <value value="0x2d" name="CP_CSF_RB_WPTR_NEQ_RPTR"/> + <value value="0x2e" name="CP_CSF_I1_SIZE_NEQ_ZERO"/> + <value value="0x2f" name="CP_CSF_I2_SIZE_NEQ_ZERO"/> + <value value="0x30" name="CP_CSF_RBI1I2_FETCHING"/> +</enum> + +<enum name="a3xx_gras_tse_perfcounter_select"> + <value value="0x00" name="GRAS_TSEPERF_INPUT_PRIM"/> + <value value="0x01" name="GRAS_TSEPERF_INPUT_NULL_PRIM"/> + <value value="0x02" name="GRAS_TSEPERF_TRIVAL_REJ_PRIM"/> + <value value="0x03" name="GRAS_TSEPERF_CLIPPED_PRIM"/> + <value value="0x04" name="GRAS_TSEPERF_NEW_PRIM"/> + <value value="0x05" name="GRAS_TSEPERF_ZERO_AREA_PRIM"/> + <value value="0x06" name="GRAS_TSEPERF_FACENESS_CULLED_PRIM"/> + <value value="0x07" name="GRAS_TSEPERF_ZERO_PIXEL_PRIM"/> + <value value="0x08" name="GRAS_TSEPERF_OUTPUT_NULL_PRIM"/> + <value value="0x09" name="GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM"/> + <value value="0x0a" name="GRAS_TSEPERF_PRE_CLIP_PRIM"/> + <value value="0x0b" name="GRAS_TSEPERF_POST_CLIP_PRIM"/> + <value value="0x0c" name="GRAS_TSEPERF_WORKING_CYCLES"/> + <value value="0x0d" name="GRAS_TSEPERF_PC_STARVE"/> + <value value="0x0e" name="GRAS_TSERASPERF_STALL"/> +</enum> + +<enum name="a3xx_gras_ras_perfcounter_select"> + <value value="0x00" name="GRAS_RASPERF_16X16_TILES"/> + <value value="0x01" name="GRAS_RASPERF_8X8_TILES"/> + <value value="0x02" name="GRAS_RASPERF_4X4_TILES"/> + <value value="0x03" name="GRAS_RASPERF_WORKING_CYCLES"/> + <value value="0x04" name="GRAS_RASPERF_STALL_CYCLES_BY_RB"/> + <value value="0x05" name="GRAS_RASPERF_STALL_CYCLES_BY_VSC"/> + <value value="0x06" name="GRAS_RASPERF_STARVE_CYCLES_BY_TSE"/> +</enum> + +<enum name="a3xx_hlsq_perfcounter_select"> + <value value="0x00" name="HLSQ_PERF_SP_VS_CONSTANT"/> + <value value="0x01" name="HLSQ_PERF_SP_VS_INSTRUCTIONS"/> + <value value="0x02" name="HLSQ_PERF_SP_FS_CONSTANT"/> + <value value="0x03" name="HLSQ_PERF_SP_FS_INSTRUCTIONS"/> + <value value="0x04" name="HLSQ_PERF_TP_STATE"/> + <value value="0x05" name="HLSQ_PERF_QUADS"/> + <value value="0x06" name="HLSQ_PERF_PIXELS"/> + <value value="0x07" name="HLSQ_PERF_VERTICES"/> + <value value="0x08" name="HLSQ_PERF_FS8_THREADS"/> + <value value="0x09" name="HLSQ_PERF_FS16_THREADS"/> + <value value="0x0a" name="HLSQ_PERF_FS32_THREADS"/> + <value value="0x0b" name="HLSQ_PERF_VS8_THREADS"/> + <value value="0x0c" name="HLSQ_PERF_VS16_THREADS"/> + <value value="0x0d" name="HLSQ_PERF_SP_VS_DATA_BYTES"/> + <value value="0x0e" name="HLSQ_PERF_SP_FS_DATA_BYTES"/> + <value value="0x0f" name="HLSQ_PERF_ACTIVE_CYCLES"/> + <value value="0x10" name="HLSQ_PERF_STALL_CYCLES_SP_STATE"/> + <value value="0x11" name="HLSQ_PERF_STALL_CYCLES_SP_VS"/> + <value value="0x12" name="HLSQ_PERF_STALL_CYCLES_SP_FS"/> + <value value="0x13" name="HLSQ_PERF_STALL_CYCLES_UCHE"/> + <value value="0x14" name="HLSQ_PERF_RBBM_LOAD_CYCLES"/> + <value value="0x15" name="HLSQ_PERF_DI_TO_VS_START_SP0"/> + <value value="0x16" name="HLSQ_PERF_DI_TO_FS_START_SP0"/> + <value value="0x17" name="HLSQ_PERF_VS_START_TO_DONE_SP0"/> + <value value="0x18" name="HLSQ_PERF_FS_START_TO_DONE_SP0"/> + <value value="0x19" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_VS"/> + <value value="0x1a" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_FS"/> + <value value="0x1b" name="HLSQ_PERF_UCHE_LATENCY_CYCLES"/> + <value value="0x1c" name="HLSQ_PERF_UCHE_LATENCY_COUNT"/> +</enum> + +<enum name="a3xx_pc_perfcounter_select"> + <value value="0x00" name="PC_PCPERF_VISIBILITY_STREAMS"/> + <value value="0x01" name="PC_PCPERF_TOTAL_INSTANCES"/> + <value value="0x02" name="PC_PCPERF_PRIMITIVES_PC_VPC"/> + <value value="0x03" name="PC_PCPERF_PRIMITIVES_KILLED_BY_VS"/> + <value value="0x04" name="PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS"/> + <value value="0x05" name="PC_PCPERF_DRAWCALLS_KILLED_BY_VS"/> + <value value="0x06" name="PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS"/> + <value value="0x07" name="PC_PCPERF_VERTICES_TO_VFD"/> + <value value="0x08" name="PC_PCPERF_REUSED_VERTICES"/> + <value value="0x09" name="PC_PCPERF_CYCLES_STALLED_BY_VFD"/> + <value value="0x0a" name="PC_PCPERF_CYCLES_STALLED_BY_TSE"/> + <value value="0x0b" name="PC_PCPERF_CYCLES_STALLED_BY_VBIF"/> + <value value="0x0c" name="PC_PCPERF_CYCLES_IS_WORKING"/> +</enum> + +<enum name="a3xx_rb_perfcounter_select"> + <value value="0x00" name="RB_RBPERF_ACTIVE_CYCLES_ANY"/> + <value value="0x01" name="RB_RBPERF_ACTIVE_CYCLES_ALL"/> + <value value="0x02" name="RB_RBPERF_STARVE_CYCLES_BY_SP"/> + <value value="0x03" name="RB_RBPERF_STARVE_CYCLES_BY_RAS"/> + <value value="0x04" name="RB_RBPERF_STARVE_CYCLES_BY_MARB"/> + <value value="0x05" name="RB_RBPERF_STALL_CYCLES_BY_MARB"/> + <value value="0x06" name="RB_RBPERF_STALL_CYCLES_BY_HLSQ"/> + <value value="0x07" name="RB_RBPERF_RB_MARB_DATA"/> + <value value="0x08" name="RB_RBPERF_SP_RB_QUAD"/> + <value value="0x09" name="RB_RBPERF_RAS_EARLY_Z_QUADS"/> + <value value="0x0a" name="RB_RBPERF_GMEM_CH0_READ"/> + <value value="0x0b" name="RB_RBPERF_GMEM_CH1_READ"/> + <value value="0x0c" name="RB_RBPERF_GMEM_CH0_WRITE"/> + <value value="0x0d" name="RB_RBPERF_GMEM_CH1_WRITE"/> + <value value="0x0e" name="RB_RBPERF_CP_CONTEXT_DONE"/> + <value value="0x0f" name="RB_RBPERF_CP_CACHE_FLUSH"/> + <value value="0x10" name="RB_RBPERF_CP_ZPASS_DONE"/> +</enum> + +<enum name="a3xx_rbbm_perfcounter_select"> + <value value="0" name="RBBM_ALAWYS_ON"/> + <value value="1" name="RBBM_VBIF_BUSY"/> + <value value="2" name="RBBM_TSE_BUSY"/> + <value value="3" name="RBBM_RAS_BUSY"/> + <value value="4" name="RBBM_PC_DCALL_BUSY"/> + <value value="5" name="RBBM_PC_VSD_BUSY"/> + <value value="6" name="RBBM_VFD_BUSY"/> + <value value="7" name="RBBM_VPC_BUSY"/> + <value value="8" name="RBBM_UCHE_BUSY"/> + <value value="9" name="RBBM_VSC_BUSY"/> + <value value="10" name="RBBM_HLSQ_BUSY"/> + <value value="11" name="RBBM_ANY_RB_BUSY"/> + <value value="12" name="RBBM_ANY_TEX_BUSY"/> + <value value="13" name="RBBM_ANY_USP_BUSY"/> + <value value="14" name="RBBM_ANY_MARB_BUSY"/> + <value value="15" name="RBBM_ANY_ARB_BUSY"/> + <value value="16" name="RBBM_AHB_STATUS_BUSY"/> + <value value="17" name="RBBM_AHB_STATUS_STALLED"/> + <value value="18" name="RBBM_AHB_STATUS_TXFR"/> + <value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/> + <value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/> + <value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/> + <value value="22" name="RBBM_RBBM_STATUS_MASKED"/> +</enum> + +<enum name="a3xx_sp_perfcounter_select"> + <value value="0x00" name="SP_LM_LOAD_INSTRUCTIONS"/> + <value value="0x01" name="SP_LM_STORE_INSTRUCTIONS"/> + <value value="0x02" name="SP_LM_ATOMICS"/> + <value value="0x03" name="SP_UCHE_LOAD_INSTRUCTIONS"/> + <value value="0x04" name="SP_UCHE_STORE_INSTRUCTIONS"/> + <value value="0x05" name="SP_UCHE_ATOMICS"/> + <value value="0x06" name="SP_VS_TEX_INSTRUCTIONS"/> + <value value="0x07" name="SP_VS_CFLOW_INSTRUCTIONS"/> + <value value="0x08" name="SP_VS_EFU_INSTRUCTIONS"/> + <value value="0x09" name="SP_VS_FULL_ALU_INSTRUCTIONS"/> + <value value="0x0a" name="SP_VS_HALF_ALU_INSTRUCTIONS"/> + <value value="0x0b" name="SP_FS_TEX_INSTRUCTIONS"/> + <value value="0x0c" name="SP_FS_CFLOW_INSTRUCTIONS"/> + <value value="0x0d" name="SP_FS_EFU_INSTRUCTIONS"/> + <value value="0x0e" name="SP_FS_FULL_ALU_INSTRUCTIONS"/> + <value value="0x0f" name="SP_FS_HALF_ALU_INSTRUCTIONS"/> + <value value="0x10" name="SP_FS_BARY_INSTRUCTIONS"/> + <value value="0x11" name="SP_VS_INSTRUCTIONS"/> + <value value="0x12" name="SP_FS_INSTRUCTIONS"/> + <value value="0x13" name="SP_ADDR_LOCK_COUNT"/> + <value value="0x14" name="SP_UCHE_READ_TRANS"/> + <value value="0x15" name="SP_UCHE_WRITE_TRANS"/> + <value value="0x16" name="SP_EXPORT_VPC_TRANS"/> + <value value="0x17" name="SP_EXPORT_RB_TRANS"/> + <value value="0x18" name="SP_PIXELS_KILLED"/> + <value value="0x19" name="SP_ICL1_REQUESTS"/> + <value value="0x1a" name="SP_ICL1_MISSES"/> + <value value="0x1b" name="SP_ICL0_REQUESTS"/> + <value value="0x1c" name="SP_ICL0_MISSES"/> + <value value="0x1d" name="SP_ALU_ACTIVE_CYCLES"/> + <value value="0x1e" name="SP_EFU_ACTIVE_CYCLES"/> + <value value="0x1f" name="SP_STALL_CYCLES_BY_VPC"/> + <value value="0x20" name="SP_STALL_CYCLES_BY_TP"/> + <value value="0x21" name="SP_STALL_CYCLES_BY_UCHE"/> + <value value="0x22" name="SP_STALL_CYCLES_BY_RB"/> + <value value="0x23" name="SP_ACTIVE_CYCLES_ANY"/> + <value value="0x24" name="SP_ACTIVE_CYCLES_ALL"/> +</enum> + +<enum name="a3xx_tp_perfcounter_select"> + <value value="0x00" name="TPL1_TPPERF_L1_REQUESTS"/> + <value value="0x01" name="TPL1_TPPERF_TP0_L1_REQUESTS"/> + <value value="0x02" name="TPL1_TPPERF_TP0_L1_MISSES"/> + <value value="0x03" name="TPL1_TPPERF_TP1_L1_REQUESTS"/> + <value value="0x04" name="TPL1_TPPERF_TP1_L1_MISSES"/> + <value value="0x05" name="TPL1_TPPERF_TP2_L1_REQUESTS"/> + <value value="0x06" name="TPL1_TPPERF_TP2_L1_MISSES"/> + <value value="0x07" name="TPL1_TPPERF_TP3_L1_REQUESTS"/> + <value value="0x08" name="TPL1_TPPERF_TP3_L1_MISSES"/> + <value value="0x09" name="TPL1_TPPERF_OUTPUT_TEXELS_POINT"/> + <value value="0x0a" name="TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR"/> + <value value="0x0b" name="TPL1_TPPERF_OUTPUT_TEXELS_MIP"/> + <value value="0x0c" name="TPL1_TPPERF_OUTPUT_TEXELS_ANISO"/> + <value value="0x0d" name="TPL1_TPPERF_BILINEAR_OPS"/> + <value value="0x0e" name="TPL1_TPPERF_QUADSQUADS_OFFSET"/> + <value value="0x0f" name="TPL1_TPPERF_QUADQUADS_SHADOW"/> + <value value="0x10" name="TPL1_TPPERF_QUADS_ARRAY"/> + <value value="0x11" name="TPL1_TPPERF_QUADS_PROJECTION"/> + <value value="0x12" name="TPL1_TPPERF_QUADS_GRADIENT"/> + <value value="0x13" name="TPL1_TPPERF_QUADS_1D2D"/> + <value value="0x14" name="TPL1_TPPERF_QUADS_3DCUBE"/> + <value value="0x15" name="TPL1_TPPERF_ZERO_LOD"/> + <value value="0x16" name="TPL1_TPPERF_OUTPUT_TEXELS"/> + <value value="0x17" name="TPL1_TPPERF_ACTIVE_CYCLES_ANY"/> + <value value="0x18" name="TPL1_TPPERF_ACTIVE_CYCLES_ALL"/> + <value value="0x19" name="TPL1_TPPERF_STALL_CYCLES_BY_ARB"/> + <value value="0x1a" name="TPL1_TPPERF_LATENCY"/> + <value value="0x1b" name="TPL1_TPPERF_LATENCY_TRANS"/> +</enum> + +<enum name="a3xx_vfd_perfcounter_select"> + <value value="0" name="VFD_PERF_UCHE_BYTE_FETCHED"/> + <value value="1" name="VFD_PERF_UCHE_TRANS"/> + <value value="2" name="VFD_PERF_VPC_BYPASS_COMPONENTS"/> + <value value="3" name="VFD_PERF_FETCH_INSTRUCTIONS"/> + <value value="4" name="VFD_PERF_DECODE_INSTRUCTIONS"/> + <value value="5" name="VFD_PERF_ACTIVE_CYCLES"/> + <value value="6" name="VFD_PERF_STALL_CYCLES_UCHE"/> + <value value="7" name="VFD_PERF_STALL_CYCLES_HLSQ"/> + <value value="8" name="VFD_PERF_STALL_CYCLES_VPC_BYPASS"/> + <value value="9" name="VFD_PERF_STALL_CYCLES_VPC_ALLOC"/> +</enum> + +<enum name="a3xx_vpc_perfcounter_select"> + <value value="0" name="VPC_PERF_SP_LM_PRIMITIVES"/> + <value value="1" name="VPC_PERF_COMPONENTS_FROM_SP"/> + <value value="2" name="VPC_PERF_SP_LM_COMPONENTS"/> + <value value="3" name="VPC_PERF_ACTIVE_CYCLES"/> + <value value="4" name="VPC_PERF_STALL_CYCLES_LM"/> + <value value="5" name="VPC_PERF_STALL_CYCLES_RAS"/> +</enum> + +<enum name="a3xx_uche_perfcounter_select"> + <value value="0x00" name="UCHE_UCHEPERF_VBIF_READ_BEATS_TP"/> + <value value="0x01" name="UCHE_UCHEPERF_VBIF_READ_BEATS_VFD"/> + <value value="0x02" name="UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ"/> + <value value="0x03" name="UCHE_UCHEPERF_VBIF_READ_BEATS_MARB"/> + <value value="0x04" name="UCHE_UCHEPERF_VBIF_READ_BEATS_SP"/> + <value value="0x08" name="UCHE_UCHEPERF_READ_REQUESTS_TP"/> + <value value="0x09" name="UCHE_UCHEPERF_READ_REQUESTS_VFD"/> + <value value="0x0a" name="UCHE_UCHEPERF_READ_REQUESTS_HLSQ"/> + <value value="0x0b" name="UCHE_UCHEPERF_READ_REQUESTS_MARB"/> + <value value="0x0c" name="UCHE_UCHEPERF_READ_REQUESTS_SP"/> + <value value="0x0d" name="UCHE_UCHEPERF_WRITE_REQUESTS_MARB"/> + <value value="0x0e" name="UCHE_UCHEPERF_WRITE_REQUESTS_SP"/> + <value value="0x0f" name="UCHE_UCHEPERF_TAG_CHECK_FAILS"/> + <value value="0x10" name="UCHE_UCHEPERF_EVICTS"/> + <value value="0x11" name="UCHE_UCHEPERF_FLUSHES"/> + <value value="0x12" name="UCHE_UCHEPERF_VBIF_LATENCY_CYCLES"/> + <value value="0x13" name="UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES"/> + <value value="0x14" name="UCHE_UCHEPERF_ACTIVE_CYCLES"/> +</enum> + +<enum name="a3xx_intp_mode"> + <value name="SMOOTH" value="0"/> + <value name="FLAT" value="1"/> + <value name="ZERO" value="2"/> + <value name="ONE" value="3"/> +</enum> + +<enum name="a3xx_repl_mode"> + <value name="S" value="1"/> + <value name="T" value="2"/> + <value name="ONE_T" value="3"/> +</enum> + +<domain name="A3XX" width="32"> + <!-- RBBM registers --> + <reg32 offset="0x0000" name="RBBM_HW_VERSION"/> + <reg32 offset="0x0001" name="RBBM_HW_RELEASE"/> + <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/> + <reg32 offset="0x0010" name="RBBM_CLOCK_CTL"/> + <reg32 offset="0x0012" name="RBBM_SP_HYST_CNT"/> + <reg32 offset="0x0018" name="RBBM_SW_RESET_CMD"/> + <reg32 offset="0x0020" name="RBBM_AHB_CTL0"/> + <reg32 offset="0x0021" name="RBBM_AHB_CTL1"/> + <reg32 offset="0x0022" name="RBBM_AHB_CMD"/> + <reg32 offset="0x0027" name="RBBM_AHB_ERROR_STATUS"/> + <reg32 offset="0x002e" name="RBBM_GPR0_CTL"/> + <reg32 offset="0x0030" name="RBBM_STATUS"> + <bitfield name="HI_BUSY" pos="0" type="boolean"/> + <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/> + <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/> + <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/> + <bitfield name="VBIF_BUSY" pos="15" type="boolean"/> + <bitfield name="TSE_BUSY" pos="16" type="boolean"/> + <bitfield name="RAS_BUSY" pos="17" type="boolean"/> + <bitfield name="RB_BUSY" pos="18" type="boolean"/> + <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/> + <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/> + <bitfield name="VFD_BUSY" pos="21" type="boolean"/> + <bitfield name="VPC_BUSY" pos="22" type="boolean"/> + <bitfield name="UCHE_BUSY" pos="23" type="boolean"/> + <bitfield name="SP_BUSY" pos="24" type="boolean"/> + <bitfield name="TPL1_BUSY" pos="25" type="boolean"/> + <bitfield name="MARB_BUSY" pos="26" type="boolean"/> + <bitfield name="VSC_BUSY" pos="27" type="boolean"/> + <bitfield name="ARB_BUSY" pos="28" type="boolean"/> + <bitfield name="HLSQ_BUSY" pos="29" type="boolean"/> + <bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/> + <bitfield name="GPU_BUSY" pos="31" type="boolean"/> + </reg32> + <!-- used in fw CP_WAIT_FOR_IDLE, similar to NQWAIT_UNTIL on a2xx: --> + <reg32 offset="0x0040" name="RBBM_NQWAIT_UNTIL"/> + <reg32 offset="0x0033" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/> + <reg32 offset="0x0050" name="RBBM_INTERFACE_HANG_INT_CTL"/> + <reg32 offset="0x0051" name="RBBM_INTERFACE_HANG_MASK_CTL0"/> + <reg32 offset="0x0054" name="RBBM_INTERFACE_HANG_MASK_CTL1"/> + <reg32 offset="0x0057" name="RBBM_INTERFACE_HANG_MASK_CTL2"/> + <reg32 offset="0x005a" name="RBBM_INTERFACE_HANG_MASK_CTL3"/> + + <bitset name="A3XX_INT0"> + <bitfield name="RBBM_GPU_IDLE" pos="0"/> + <bitfield name="RBBM_AHB_ERROR" pos="1"/> + <bitfield name="RBBM_REG_TIMEOUT" pos="2"/> + <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/> + <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/> + <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5"/> + <bitfield name="VFD_ERROR" pos="6"/> + <bitfield name="CP_SW_INT" pos="7"/> + <bitfield name="CP_T0_PACKET_IN_IB" pos="8"/> + <bitfield name="CP_OPCODE_ERROR" pos="9"/> + <bitfield name="CP_RESERVED_BIT_ERROR" pos="10"/> + <bitfield name="CP_HW_FAULT" pos="11"/> + <bitfield name="CP_DMA" pos="12"/> + <bitfield name="CP_IB2_INT" pos="13"/> + <bitfield name="CP_IB1_INT" pos="14"/> + <bitfield name="CP_RB_INT" pos="15"/> + <bitfield name="CP_REG_PROTECT_FAULT" pos="16"/> + <bitfield name="CP_RB_DONE_TS" pos="17"/> + <bitfield name="CP_VS_DONE_TS" pos="18"/> + <bitfield name="CP_PS_DONE_TS" pos="19"/> + <bitfield name="CACHE_FLUSH_TS" pos="20"/> + <bitfield name="CP_AHB_ERROR_HALT" pos="21"/> + <bitfield name="MISC_HANG_DETECT" pos="24"/> + <bitfield name="UCHE_OOB_ACCESS" pos="25"/> + </bitset> + + + <!-- + set in pm4 fw INVALID_JUMP_TABLE_ENTRY and CP_INTERRUPT (compare + to CP_INT_STATUS in a2xx firmware), so this seems to be the a3xx + way for fw to raise and irq: + --> + <reg32 offset="0x0060" name="RBBM_INT_SET_CMD" type="A3XX_INT0"/> + <reg32 offset="0x0061" name="RBBM_INT_CLEAR_CMD" type="A3XX_INT0"/> + <reg32 offset="0x0063" name="RBBM_INT_0_MASK" type="A3XX_INT0"/> + <reg32 offset="0x0064" name="RBBM_INT_0_STATUS" type="A3XX_INT0"/> + <reg32 offset="0x0080" name="RBBM_PERFCTR_CTL"> + <bitfield name="ENABLE" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x0081" name="RBBM_PERFCTR_LOAD_CMD0"/> + <reg32 offset="0x0082" name="RBBM_PERFCTR_LOAD_CMD1"/> + <reg32 offset="0x0084" name="RBBM_PERFCTR_LOAD_VALUE_LO"/> + <reg32 offset="0x0085" name="RBBM_PERFCTR_LOAD_VALUE_HI"/> + <reg32 offset="0x0086" name="RBBM_PERFCOUNTER0_SELECT" type="a3xx_rbbm_perfcounter_select"/> + <reg32 offset="0x0087" name="RBBM_PERFCOUNTER1_SELECT" type="a3xx_rbbm_perfcounter_select"/> + <reg32 offset="0x0088" name="RBBM_GPU_BUSY_MASKED"/> + <reg32 offset="0x0090" name="RBBM_PERFCTR_CP_0_LO"/> + <reg32 offset="0x0091" name="RBBM_PERFCTR_CP_0_HI"/> + <reg32 offset="0x0092" name="RBBM_PERFCTR_RBBM_0_LO"/> + <reg32 offset="0x0093" name="RBBM_PERFCTR_RBBM_0_HI"/> + <reg32 offset="0x0094" name="RBBM_PERFCTR_RBBM_1_LO"/> + <reg32 offset="0x0095" name="RBBM_PERFCTR_RBBM_1_HI"/> + <reg32 offset="0x0096" name="RBBM_PERFCTR_PC_0_LO"/> + <reg32 offset="0x0097" name="RBBM_PERFCTR_PC_0_HI"/> + <reg32 offset="0x0098" name="RBBM_PERFCTR_PC_1_LO"/> + <reg32 offset="0x0099" name="RBBM_PERFCTR_PC_1_HI"/> + <reg32 offset="0x009a" name="RBBM_PERFCTR_PC_2_LO"/> + <reg32 offset="0x009b" name="RBBM_PERFCTR_PC_2_HI"/> + <reg32 offset="0x009c" name="RBBM_PERFCTR_PC_3_LO"/> + <reg32 offset="0x009d" name="RBBM_PERFCTR_PC_3_HI"/> + <reg32 offset="0x009e" name="RBBM_PERFCTR_VFD_0_LO"/> + <reg32 offset="0x009f" name="RBBM_PERFCTR_VFD_0_HI"/> + <reg32 offset="0x00a0" name="RBBM_PERFCTR_VFD_1_LO"/> + <reg32 offset="0x00a1" name="RBBM_PERFCTR_VFD_1_HI"/> + <reg32 offset="0x00a2" name="RBBM_PERFCTR_HLSQ_0_LO"/> + <reg32 offset="0x00a3" name="RBBM_PERFCTR_HLSQ_0_HI"/> + <reg32 offset="0x00a4" name="RBBM_PERFCTR_HLSQ_1_LO"/> + <reg32 offset="0x00a5" name="RBBM_PERFCTR_HLSQ_1_HI"/> + <reg32 offset="0x00a6" name="RBBM_PERFCTR_HLSQ_2_LO"/> + <reg32 offset="0x00a7" name="RBBM_PERFCTR_HLSQ_2_HI"/> + <reg32 offset="0x00a8" name="RBBM_PERFCTR_HLSQ_3_LO"/> + <reg32 offset="0x00a9" name="RBBM_PERFCTR_HLSQ_3_HI"/> + <reg32 offset="0x00aa" name="RBBM_PERFCTR_HLSQ_4_LO"/> + <reg32 offset="0x00ab" name="RBBM_PERFCTR_HLSQ_4_HI"/> + <reg32 offset="0x00ac" name="RBBM_PERFCTR_HLSQ_5_LO"/> + <reg32 offset="0x00ad" name="RBBM_PERFCTR_HLSQ_5_HI"/> + <reg32 offset="0x00ae" name="RBBM_PERFCTR_VPC_0_LO"/> + <reg32 offset="0x00af" name="RBBM_PERFCTR_VPC_0_HI"/> + <reg32 offset="0x00b0" name="RBBM_PERFCTR_VPC_1_LO"/> + <reg32 offset="0x00b1" name="RBBM_PERFCTR_VPC_1_HI"/> + <reg32 offset="0x00b2" name="RBBM_PERFCTR_TSE_0_LO"/> + <reg32 offset="0x00b3" name="RBBM_PERFCTR_TSE_0_HI"/> + <reg32 offset="0x00b4" name="RBBM_PERFCTR_TSE_1_LO"/> + <reg32 offset="0x00b5" name="RBBM_PERFCTR_TSE_1_HI"/> + <reg32 offset="0x00b6" name="RBBM_PERFCTR_RAS_0_LO"/> + <reg32 offset="0x00b7" name="RBBM_PERFCTR_RAS_0_HI"/> + <reg32 offset="0x00b8" name="RBBM_PERFCTR_RAS_1_LO"/> + <reg32 offset="0x00b9" name="RBBM_PERFCTR_RAS_1_HI"/> + <reg32 offset="0x00ba" name="RBBM_PERFCTR_UCHE_0_LO"/> + <reg32 offset="0x00bb" name="RBBM_PERFCTR_UCHE_0_HI"/> + <reg32 offset="0x00bc" name="RBBM_PERFCTR_UCHE_1_LO"/> + <reg32 offset="0x00bd" name="RBBM_PERFCTR_UCHE_1_HI"/> + <reg32 offset="0x00be" name="RBBM_PERFCTR_UCHE_2_LO"/> + <reg32 offset="0x00bf" name="RBBM_PERFCTR_UCHE_2_HI"/> + <reg32 offset="0x00c0" name="RBBM_PERFCTR_UCHE_3_LO"/> + <reg32 offset="0x00c1" name="RBBM_PERFCTR_UCHE_3_HI"/> + <reg32 offset="0x00c2" name="RBBM_PERFCTR_UCHE_4_LO"/> + <reg32 offset="0x00c3" name="RBBM_PERFCTR_UCHE_4_HI"/> + <reg32 offset="0x00c4" name="RBBM_PERFCTR_UCHE_5_LO"/> + <reg32 offset="0x00c5" name="RBBM_PERFCTR_UCHE_5_HI"/> + <reg32 offset="0x00c6" name="RBBM_PERFCTR_TP_0_LO"/> + <reg32 offset="0x00c7" name="RBBM_PERFCTR_TP_0_HI"/> + <reg32 offset="0x00c8" name="RBBM_PERFCTR_TP_1_LO"/> + <reg32 offset="0x00c9" name="RBBM_PERFCTR_TP_1_HI"/> + <reg32 offset="0x00ca" name="RBBM_PERFCTR_TP_2_LO"/> + <reg32 offset="0x00cb" name="RBBM_PERFCTR_TP_2_HI"/> + <reg32 offset="0x00cc" name="RBBM_PERFCTR_TP_3_LO"/> + <reg32 offset="0x00cd" name="RBBM_PERFCTR_TP_3_HI"/> + <reg32 offset="0x00ce" name="RBBM_PERFCTR_TP_4_LO"/> + <reg32 offset="0x00cf" name="RBBM_PERFCTR_TP_4_HI"/> + <reg32 offset="0x00d0" name="RBBM_PERFCTR_TP_5_LO"/> + <reg32 offset="0x00d1" name="RBBM_PERFCTR_TP_5_HI"/> + <reg32 offset="0x00d2" name="RBBM_PERFCTR_SP_0_LO"/> + <reg32 offset="0x00d3" name="RBBM_PERFCTR_SP_0_HI"/> + <reg32 offset="0x00d4" name="RBBM_PERFCTR_SP_1_LO"/> + <reg32 offset="0x00d5" name="RBBM_PERFCTR_SP_1_HI"/> + <reg32 offset="0x00d6" name="RBBM_PERFCTR_SP_2_LO"/> + <reg32 offset="0x00d7" name="RBBM_PERFCTR_SP_2_HI"/> + <reg32 offset="0x00d8" name="RBBM_PERFCTR_SP_3_LO"/> + <reg32 offset="0x00d9" name="RBBM_PERFCTR_SP_3_HI"/> + <reg32 offset="0x00da" name="RBBM_PERFCTR_SP_4_LO"/> + <reg32 offset="0x00db" name="RBBM_PERFCTR_SP_4_HI"/> + <reg32 offset="0x00dc" name="RBBM_PERFCTR_SP_5_LO"/> + <reg32 offset="0x00dd" name="RBBM_PERFCTR_SP_5_HI"/> + <reg32 offset="0x00de" name="RBBM_PERFCTR_SP_6_LO"/> + <reg32 offset="0x00df" name="RBBM_PERFCTR_SP_6_HI"/> + <reg32 offset="0x00e0" name="RBBM_PERFCTR_SP_7_LO"/> + <reg32 offset="0x00e1" name="RBBM_PERFCTR_SP_7_HI"/> + <reg32 offset="0x00e2" name="RBBM_PERFCTR_RB_0_LO"/> + <reg32 offset="0x00e3" name="RBBM_PERFCTR_RB_0_HI"/> + <reg32 offset="0x00e4" name="RBBM_PERFCTR_RB_1_LO"/> + <reg32 offset="0x00e5" name="RBBM_PERFCTR_RB_1_HI"/> + <reg32 offset="0x00ea" name="RBBM_PERFCTR_PWR_0_LO"/> + <reg32 offset="0x00eb" name="RBBM_PERFCTR_PWR_0_HI"/> + <reg32 offset="0x00ec" name="RBBM_PERFCTR_PWR_1_LO"/> + <reg32 offset="0x00ed" name="RBBM_PERFCTR_PWR_1_HI"/> + <reg32 offset="0x0100" name="RBBM_RBBM_CTL"/> + <reg32 offset="0x0111" name="RBBM_DEBUG_BUS_CTL"/> + <reg32 offset="0x0112" name="RBBM_DEBUG_BUS_DATA_STATUS"/> + + <!-- CP registers --> + <reg32 offset="0x01c9" name="CP_PFP_UCODE_ADDR"/> + <reg32 offset="0x01ca" name="CP_PFP_UCODE_DATA"/> + <reg32 offset="0x01cc" name="CP_ROQ_ADDR"/> + <reg32 offset="0x01cd" name="CP_ROQ_DATA"/> + <reg32 offset="0x01d1" name="CP_MERCIU_ADDR"/> + <reg32 offset="0x01d2" name="CP_MERCIU_DATA"/> + <reg32 offset="0x01d3" name="CP_MERCIU_DATA2"/> + <!-- see a3xx_snapshot_cp_meq().. looks like the way to dump queue between pfp and pm4 --> + <reg32 offset="0x01da" name="CP_MEQ_ADDR"/> + <reg32 offset="0x01db" name="CP_MEQ_DATA"/> + <reg32 offset="0x01f5" name="CP_WFI_PEND_CTR"/> + <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/> + + <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT" type="a3xx_cp_perfcounter_select"/> + <reg32 offset="0x045c" name="CP_HW_FAULT"/> + <reg32 offset="0x045e" name="CP_PROTECT_CTRL"/> + <reg32 offset="0x045f" name="CP_PROTECT_STATUS"/> + <array offset="0x0460" name="CP_PROTECT" stride="1" length="16"> + <reg32 offset="0x0" name="REG"/> + </array> + <reg32 offset="0x054d" name="CP_AHB_FAULT"/> + + <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT"/> + <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT"/> + <reg32 offset="0x0e1e" name="TP0_CHICKEN"/> + + <!-- these I guess or either SP or HLSQ since related to shader core setup: --> + <reg32 offset="0x0e22" name="SP_GLOBAL_MEM_SIZE" type="uint"> + <doc> + The pair of MEM_SIZE/ADDR registers get programmed + in sequence with the size/addr of each buffer. + </doc> + </reg32> + <reg32 offset="0x0e23" name="SP_GLOBAL_MEM_ADDR"/> + + <!-- GRAS registers --> + <reg32 offset="0x2040" name="GRAS_CL_CLIP_CNTL"> + <bitfield name="IJ_PERSP_CENTER" pos="12" type="boolean"/> <!-- is it more bits? --> + <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/> + <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/> + <bitfield name="VP_CLIP_CODE_IGNORE" pos="19" type="boolean"/> + <bitfield name="VP_XFORM_DISABLE" pos="20" type="boolean"/> + <bitfield name="PERSP_DIVISION_DISABLE" pos="21" type="boolean"/> + <bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean"> + <doc>aka clip_halfz</doc> + </bitfield> + <!-- set when gl_FragCoord.z is enabled in frag shader: --> + <bitfield name="ZCOORD" pos="23" type="boolean"/> + <bitfield name="WCOORD" pos="24" type="boolean"/> + <!-- set when frag shader writes z (so early z test disabled: --> + <bitfield name="ZCLIP_DISABLE" pos="25" type="boolean"/> + <bitfield name="NUM_USER_CLIP_PLANES" low="26" high="28" type="uint"/> + </reg32> + <reg32 offset="0x2044" name="GRAS_CL_GB_CLIP_ADJ"> + <bitfield name="HORZ" low="0" high="9" type="uint"/> + <bitfield name="VERT" low="10" high="19" type="uint"/> + </reg32> + <reg32 offset="0x2048" name="GRAS_CL_VPORT_XOFFSET" type="float"/> + <reg32 offset="0x2049" name="GRAS_CL_VPORT_XSCALE" type="float"/> + <reg32 offset="0x204a" name="GRAS_CL_VPORT_YOFFSET" type="float"/> + <reg32 offset="0x204b" name="GRAS_CL_VPORT_YSCALE" type="float"/> + <reg32 offset="0x204c" name="GRAS_CL_VPORT_ZOFFSET" type="float"/> + <reg32 offset="0x204d" name="GRAS_CL_VPORT_ZSCALE" type="float"/> + <reg32 offset="0x2068" name="GRAS_SU_POINT_MINMAX"> + <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> + <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> + </reg32> + <reg32 offset="0x2069" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/> + <reg32 offset="0x206c" name="GRAS_SU_POLY_OFFSET_SCALE"> + <bitfield name="VAL" low="0" high="23" type="fixed" radix="20"/> + <doc>range of -8.0 to 8.0</doc> + </reg32> + <reg32 offset="0x206d" name="GRAS_SU_POLY_OFFSET_OFFSET" radix="6" type="fixed"> + <doc>range of -512.0 to 512.0</doc> + </reg32> + <reg32 offset="0x2070" name="GRAS_SU_MODE_CONTROL"> + <bitfield name="CULL_FRONT" pos="0" type="boolean"/> + <bitfield name="CULL_BACK" pos="1" type="boolean"/> + <bitfield name="FRONT_CW" pos="2" type="boolean"/> + <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/> + <bitfield name="POLY_OFFSET" pos="11" type="boolean"/> + </reg32> + <reg32 offset="0x2072" name="GRAS_SC_CONTROL"> + <!-- complete wild-ass-guess for sizes of these bitfields.. --> + <bitfield name="RENDER_MODE" low="4" high="7" type="a3xx_render_mode"/> + <bitfield name="MSAA_SAMPLES" low="8" high="11" type="a3xx_msaa_samples"/> + <bitfield name="RASTER_MODE" low="12" high="15"/> + </reg32> + + <reg32 offset="0x2074" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/> + <reg32 offset="0x2075" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/> + <reg32 offset="0x2079" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/> + <reg32 offset="0x207a" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/> + + <!-- RB registers --> + <reg32 offset="0x20c0" name="RB_MODE_CONTROL"> + <!-- guess on the # of bits here.. --> + <bitfield name="GMEM_BYPASS" pos="7" type="boolean"/> + <doc> + RENDER_MODE is RB_RESOLVE_PASS for gmem->mem, otherwise RB_RENDER_PASS + </doc> + <bitfield name="RENDER_MODE" low="8" high="10" type="a3xx_render_mode"/> + <bitfield name="MRT" low="12" high="13" type="uint"> + <doc>render targets - 1</doc> + </bitfield> + <bitfield name="MARB_CACHE_SPLIT_MODE" pos="15" type="boolean"/> + <bitfield name="PACKER_TIMER_ENABLE" pos="16" type="boolean"/> + </reg32> + <reg32 offset="0x20c1" name="RB_RENDER_CONTROL"> + <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> + <bitfield name="YUV_IN_ENABLE" pos="1" type="boolean"/> + <bitfield name="COV_VALUE_INPUT_ENABLE" pos="2" type="boolean"/> + <!-- set when gl_FrontFacing is accessed in frag shader: --> + <bitfield name="FACENESS" pos="3" type="boolean"/> + <bitfield name="BIN_WIDTH" low="4" high="11" shr="5" type="uint"/> + <bitfield name="DISABLE_COLOR_PIPE" pos="12" type="boolean"/> + <!-- + ENABLE_GMEM not set on mem2gmem.. so possibly it is actually + controlling blend or readback from GMEM?? + --> + <bitfield name="ENABLE_GMEM" pos="13" type="boolean"/> + <bitfield name="XCOORD" pos="14" type="boolean"/> + <bitfield name="YCOORD" pos="15" type="boolean"/> + <bitfield name="ZCOORD" pos="16" type="boolean"/> + <bitfield name="WCOORD" pos="17" type="boolean"/> + <bitfield name="I_CLAMP_ENABLE" pos="19" type="boolean"/> + <bitfield name="COV_VALUE_OUTPUT_ENABLE" pos="20" type="boolean"/> + <bitfield name="ALPHA_TEST" pos="22" type="boolean"/> + <bitfield name="ALPHA_TEST_FUNC" low="24" high="26" type="adreno_compare_func"/> + <bitfield name="ALPHA_TO_COVERAGE" pos="30" type="boolean"/> + <bitfield name="ALPHA_TO_ONE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x20c2" name="RB_MSAA_CONTROL"> + <bitfield name="DISABLE" pos="10" type="boolean"/> + <bitfield name="SAMPLES" low="12" high="15" type="a3xx_msaa_samples"/> + <bitfield name="SAMPLE_MASK" low="16" high="31" type="hex"/> + </reg32> + <reg32 offset="0x20c3" name="RB_ALPHA_REF"> + <bitfield name="UINT" low="8" high="15" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <array offset="0x20c4" name="RB_MRT" stride="4" length="4"> + <reg32 offset="0x0" name="CONTROL"> + <bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/> + <!-- both these bits seem to get set when enabling GL_BLEND.. --> + <bitfield name="BLEND" pos="4" type="boolean"/> + <bitfield name="BLEND2" pos="5" type="boolean"/> + <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/> + <bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/> + <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/> + </reg32> + <reg32 offset="0x1" name="BUF_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="5" type="a3xx_color_fmt"/> + <bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a3xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> + <bitfield name="COLOR_SRGB" pos="14" type="boolean"/> + <doc> + Pitch (actually, appears to be pitch in bytes, so really is a stride) + in GMEM, so pitch of the current tile. + </doc> + <bitfield name="COLOR_BUF_PITCH" low="17" high="31" shr="5" type="uint"/> + </reg32> + <reg32 offset="0x2" name="BUF_BASE"> + <doc>offset into GMEM (or system memory address in bypass mode)</doc> + <bitfield name="COLOR_BUF_BASE" low="4" high="31" shr="5" type="hex"/> + </reg32> + <reg32 offset="0x3" name="BLEND_CONTROL"> + <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/> + <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/> + <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/> + <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/> + <bitfield name="CLAMP_ENABLE" pos="29" type="boolean"/> + </reg32> + </array> + + <reg32 offset="0x20e4" name="RB_BLEND_RED"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0x20e5" name="RB_BLEND_GREEN"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0x20e6" name="RB_BLEND_BLUE"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0x20e7" name="RB_BLEND_ALPHA"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + + <reg32 offset="0x20e8" name="RB_CLEAR_COLOR_DW0"/> + <reg32 offset="0x20e9" name="RB_CLEAR_COLOR_DW1"/> + <reg32 offset="0x20ea" name="RB_CLEAR_COLOR_DW2"/> + <reg32 offset="0x20eb" name="RB_CLEAR_COLOR_DW3"/> + <reg32 offset="0x20ec" name="RB_COPY_CONTROL"> + <!-- not sure # of bits --> + <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/> + <bitfield name="DEPTHCLEAR" pos="3" type="boolean"/> + <bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/> + <bitfield name="MSAA_SRGB_DOWNSAMPLE" pos="7" type="boolean"/> + <bitfield name="FASTCLEAR" low="8" high="11" type="hex"/> + <bitfield name="DEPTH32_RESOLVE" pos="12" type="boolean"/> <!-- enabled on a Z32F copy --> + <bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/> + </reg32> + <reg32 offset="0x20ed" name="RB_COPY_DEST_BASE"> + <bitfield name="BASE" low="4" high="31" shr="5" type="hex"/> + </reg32> + <reg32 offset="0x20ee" name="RB_COPY_DEST_PITCH"> + <doc>actually, appears to be pitch in bytes, so really is a stride</doc> + <!-- not actually sure about max pitch... --> + <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/> + </reg32> + <reg32 offset="0x20ef" name="RB_COPY_DEST_INFO"> + <bitfield name="TILE" low="0" high="1" type="a3xx_tile_mode"/> + <bitfield name="FORMAT" low="2" high="7" type="a3xx_color_fmt"/> + <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/> + <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/> + <bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/> + <bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/> + </reg32> + <reg32 offset="0x2100" name="RB_DEPTH_CONTROL"> + <!-- + guessing that this matches a2xx with the stencil fields + moved out into RB_STENCIL_CONTROL? + --> + <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/> + <bitfield name="Z_ENABLE" pos="1" type="boolean"/> + <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/> + <bitfield name="EARLY_Z_DISABLE" pos="3" type="boolean"/> + <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/> + <bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/> + <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc> + <bitfield name="Z_TEST_ENABLE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x2101" name="RB_DEPTH_CLEAR"> + <doc>seems to be always set to 0x00000000</doc> + </reg32> + <reg32 offset="0x2102" name="RB_DEPTH_INFO"> + <bitfield name="DEPTH_FORMAT" low="0" high="1" type="adreno_rb_depth_format"/> + <doc> + DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie + bin_w * bin_h / 1024 (possible rounded up to multiple of + something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes + 80.. so maybe it needs to be multiple of 8?? + </doc> + <bitfield name="DEPTH_BASE" low="11" high="31" shr="12" type="hex"/> + </reg32> + <reg32 offset="0x2103" name="RB_DEPTH_PITCH" shr="3" type="uint"> + <doc> + Pitch of depth buffer or combined depth+stencil buffer + in z24s8 cases. + </doc> + </reg32> + <reg32 offset="0x2104" name="RB_STENCIL_CONTROL"> + <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> + <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> + <!-- + set for stencil operations that require read from stencil + buffer, but not for example for stencil clear (which does + not require read).. so guessing this is analogous to + READ_DEST_ENABLE for color buffer.. + --> + <bitfield name="STENCIL_READ" pos="2" type="boolean"/> + <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/> + <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/> + <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/> + <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/> + <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/> + <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/> + <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> + <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> + </reg32> + <reg32 offset="0x2105" name="RB_STENCIL_CLEAR"> + <doc>seems to be always set to 0x00000000</doc> + </reg32> + <reg32 offset="0x2106" name="RB_STENCIL_INFO"> + <doc>Base address for stencil when not using interleaved depth/stencil</doc> + <bitfield name="STENCIL_BASE" low="11" high="31" shr="12" type="hex"/> + </reg32> + <reg32 offset="0x2107" name="RB_STENCIL_PITCH" shr="3" type="uint"> + <doc>pitch of stencil buffer when not using interleaved depth/stencil</doc> + </reg32> + <reg32 offset="0x2108" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/> + <reg32 offset="0x2109" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/> + <!-- VSC == visibility stream c?? --> + <reg32 offset="0x210c" name="RB_LRZ_VSC_CONTROL"> + <doc>seems to be set to 0x00000002 during binning pass</doc> + <bitfield name="BINNING_ENABLE" pos="1" type="boolean"/> + </reg32> + <reg32 offset="0x210e" name="RB_WINDOW_OFFSET"> + <doc>X/Y offset of current bin</doc> + <bitfield name="X" low="0" high="15" type="uint"/> + <bitfield name="Y" low="16" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2110" name="RB_SAMPLE_COUNT_CONTROL"> + <bitfield name="RESET" pos="0" type="boolean"/> + <bitfield name="COPY" pos="1" type="boolean"/> + </reg32> + <reg32 offset="0x2111" name="RB_SAMPLE_COUNT_ADDR"/> + <reg32 offset="0x2114" name="RB_Z_CLAMP_MIN"/> + <reg32 offset="0x2115" name="RB_Z_CLAMP_MAX"/> + + <!-- PC registers --> + <reg32 offset="0x21e1" name="VGT_BIN_BASE"> + <doc> + seems to be where firmware writes BIN_DATA_ADDR from + CP_SET_BIN_DATA packet.. probably should be called + PC_BIN_BASE (just using name from yamato for now) + </doc> + </reg32> + <reg32 offset="0x21e2" name="VGT_BIN_SIZE"> + <doc>probably should be PC_BIN_SIZE</doc> + </reg32> + <reg32 offset="0x21e4" name="PC_VSTREAM_CONTROL"> + <doc>SIZE is current pipe width * height (in tiles)</doc> + <bitfield name="SIZE" low="16" high="21" type="uint"/> + <doc> + N is some sort of slot # between 0..(SIZE-1). In case + multiple tiles use same pipe, each tile gets unique slot # + </doc> + <bitfield name="N" low="22" high="26" type="uint"/> + </reg32> + <reg32 offset="0x21ea" name="PC_VERTEX_REUSE_BLOCK_CNTL"/> + <reg32 offset="0x21ec" name="PC_PRIM_VTX_CNTL"> + <doc> + STRIDE_IN_VPC: ALIGN(next_outloc - 8, 4) / 4 + (but, in cases where you'd expect 1, the blob driver uses + 2, so possibly 0 (no varying) or minimum of 2) + </doc> + <bitfield name="STRIDE_IN_VPC" low="0" high="4" type="uint"/> + <bitfield name="POLYMODE_FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/> + <bitfield name="POLYMODE_BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/> + <bitfield name="POLYMODE_ENABLE" pos="12" type="boolean"/> + <bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/> + <bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/> + <!-- PSIZE bit set if gl_PointSize written: --> + <bitfield name="PSIZE" pos="26" type="boolean"/> + </reg32> + <reg32 offset="0x21ed" name="PC_RESTART_INDEX"/> + + <!-- HLSQ registers --> + <bitset name="a3xx_hlsq_vs_fs_control_reg" inline="yes"> + <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/> + <bitfield name="CONSTSTARTOFFSET" low="12" high="20" type="uint"/> + <bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/> + </bitset> + <bitset name="a3xx_hlsq_const_vs_fs_presv_range_reg" inline="yes"> + <!-- are these a3xx_regid?? --> + <bitfield name="STARTENTRY" low="0" high="8"/> + <bitfield name="ENDENTRY" low="16" high="24"/> + </bitset> + + <reg32 offset="0x2200" name="HLSQ_CONTROL_0_REG"> + <bitfield name="FSTHREADSIZE" low="4" high="5" type="a3xx_threadsize"/> + <bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/> + <bitfield name="COMPUTEMODE" pos="8" type="boolean"/> + <bitfield name="SPSHADERRESTART" pos="9" type="boolean"/> + <bitfield name="RESERVED2" pos="10" type="boolean"/> + <bitfield name="CYCLETIMEOUTLIMITVPC" low="12" high="23" type="uint"/> + <bitfield name="FSONLYTEX" pos="25" type="boolean"/> + <bitfield name="CHUNKDISABLE" pos="26" type="boolean"/> + <bitfield name="CONSTMODE" pos="27" type="uint"/> + <bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/> + <bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/> + <bitfield name="TPFULLUPDATE" pos="30" type="boolean"/> + <bitfield name="SINGLECONTEXT" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x2201" name="HLSQ_CONTROL_1_REG"> + <bitfield name="VSTHREADSIZE" low="6" high="7" type="a3xx_threadsize"/> + <bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/> + <bitfield name="FRAGCOORDXYREGID" low="16" high="23" type="a3xx_regid"/> + <bitfield name="FRAGCOORDZWREGID" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0x2202" name="HLSQ_CONTROL_2_REG"> + <bitfield name="FACENESSREGID" low="2" high="9" type="a3xx_regid"/> + <bitfield name="COVVALUEREGID" low="18" high="25" type="a3xx_regid"/> + <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2203" name="HLSQ_CONTROL_3_REG"> + <!-- register loaded with position (bary.f, gl_FragCoord, etc) --> + <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> + </reg32> + <reg32 offset="0x2204" name="HLSQ_VS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/> + <reg32 offset="0x2205" name="HLSQ_FS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/> + <reg32 offset="0x2206" name="HLSQ_CONST_VSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/> + <reg32 offset="0x2207" name="HLSQ_CONST_FSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/> + <reg32 offset="0x220a" name="HLSQ_CL_NDRANGE_0_REG"> + <bitfield name="WORKDIM" low="0" high="1" type="uint"/> + <bitfield name="LOCALSIZE0" low="2" high="11" type="uint"/> + <bitfield name="LOCALSIZE1" low="12" high="21" type="uint"/> + <bitfield name="LOCALSIZE2" low="22" high="31" type="uint"/> + </reg32> + <array offset="0x220b" name="HLSQ_CL_GLOBAL_WORK" stride="2" length="3"> + <doc>indexed by dimension</doc> + <reg32 offset="0" name="SIZE" type="uint"/> + <reg32 offset="1" name="OFFSET" type="uint"/> + </array> + <reg32 offset="0x2211" name="HLSQ_CL_CONTROL_0_REG"/> + <reg32 offset="0x2212" name="HLSQ_CL_CONTROL_1_REG"/> + <reg32 offset="0x2214" name="HLSQ_CL_KERNEL_CONST_REG"/> + <array offset="0x2215" name="HLSQ_CL_KERNEL_GROUP" stride="1" length="3"> + <doc>indexed by dimension, global_size / local_size</doc> + <reg32 offset="0" name="RATIO" type="uint"/> + </array> + <reg32 offset="0x2216" name="HLSQ_CL_KERNEL_GROUP_Y_REG" type="uint"/> + <reg32 offset="0x2217" name="HLSQ_CL_KERNEL_GROUP_Z_REG" type="uint"/> + <reg32 offset="0x221a" name="HLSQ_CL_WG_OFFSET_REG"/> + + <!-- VFD registers --> + <reg32 offset="0x2240" name="VFD_CONTROL_0"> + <doc> + TOTALATTRTOVS is # of attributes to vertex shader, in register + slots (ie. vec4+vec3 -> 7) + </doc> + <bitfield name="TOTALATTRTOVS" low="0" high="17" type="uint"/> + <bitfield name="PACKETSIZE" low="18" high="21" type="uint"/> + <doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc> + <bitfield name="STRMDECINSTRCNT" low="22" high="26" type="uint"/> + <doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc> + <bitfield name="STRMFETCHINSTRCNT" low="27" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2241" name="VFD_CONTROL_1"> + <doc>MAXSTORAGE could be # of attributes/vbo's</doc> + <bitfield name="MAXSTORAGE" low="0" high="3" type="uint"/> + <bitfield name="MAXTHRESHOLD" low="4" high="7" type="uint"/> + <bitfield name="MINTHRESHOLD" low="8" high="11" type="uint"/> + <bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/> + <bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0x2242" name="VFD_INDEX_MIN" type="uint"/> + <reg32 offset="0x2243" name="VFD_INDEX_MAX" type="uint"/> + <reg32 offset="0x2244" name="VFD_INSTANCEID_OFFSET" type="uint"/> + <reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/> + <reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/> + <array offset="0x2246" name="VFD_FETCH" stride="2" length="16"> + <reg32 offset="0x0" name="INSTR_0"> + <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/> + <bitfield name="BUFSTRIDE" low="7" high="15" type="uint"/> + <bitfield name="INSTANCED" pos="16" type="boolean"/> + <bitfield name="SWITCHNEXT" pos="17" type="boolean"/> + <bitfield name="INDEXCODE" low="18" high="23" type="uint"/> + <bitfield name="STEPRATE" low="24" high="31" type="uint"/> + </reg32> + <reg32 offset="0x1" name="INSTR_1"/> + </array> + <array offset="0x2266" name="VFD_DECODE" stride="1" length="16"> + <reg32 offset="0x0" name="INSTR"> + <bitfield name="WRITEMASK" low="0" high="3" type="hex"/> + <!-- not sure if this is a bit flag and another flag above it, or?? --> + <bitfield name="CONSTFILL" pos="4" type="boolean"/> + <bitfield name="FORMAT" low="6" high="11" type="a3xx_vtx_fmt"/> + <bitfield name="REGID" low="12" high="19" type="a3xx_regid"/> + <bitfield name="INT" pos="20" type="boolean"/> + <doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc> + <bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/> + <bitfield name="SHIFTCNT" low="24" high="28" type="uint"/> + <bitfield name="LASTCOMPVALID" pos="29" type="boolean"/> + <bitfield name="SWITCHNEXT" pos="30" type="boolean"/> + </reg32> + </array> + <reg32 offset="0x227e" name="VFD_VS_THREADING_THRESHOLD"> + <bitfield name="REGID_THRESHOLD" low="0" high="3" type="uint"/> + <!-- <bitfield name="RESERVED6" low="4" high="7" type="uint"/> --> + <bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/> + </reg32> + + <!-- VPC registers --> + <reg32 offset="0x2280" name="VPC_ATTR"> + <bitfield name="TOTALATTR" low="0" high="8" type="uint"/> + <!-- PSIZE bit set if gl_PointSize written: --> + <bitfield name="PSIZE" pos="9" type="boolean"/> + <bitfield name="THRDASSIGN" low="12" high="27" type="uint"/> + <bitfield name="LMSIZE" low="28" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2281" name="VPC_PACK"> + <!-- these are always seem to be set to same as TOTALATTR --> + <bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/> + <bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/> + </reg32> + <!-- + varying interpolate mode. One field per scalar/component + (since varying slots are scalar, so things don't have to + be aligned to vec4). + 4 regs * 16 scalar components each => 16 vec4 + --> + <array offset="0x2282" name="VPC_VARYING_INTERP" stride="1" length="4"> + <reg32 offset="0x0" name="MODE"> + <bitfield name="C0" low="0" high="1" type="a3xx_intp_mode"/> + <bitfield name="C1" low="2" high="3" type="a3xx_intp_mode"/> + <bitfield name="C2" low="4" high="5" type="a3xx_intp_mode"/> + <bitfield name="C3" low="6" high="7" type="a3xx_intp_mode"/> + <bitfield name="C4" low="8" high="9" type="a3xx_intp_mode"/> + <bitfield name="C5" low="10" high="11" type="a3xx_intp_mode"/> + <bitfield name="C6" low="12" high="13" type="a3xx_intp_mode"/> + <bitfield name="C7" low="14" high="15" type="a3xx_intp_mode"/> + <bitfield name="C8" low="16" high="17" type="a3xx_intp_mode"/> + <bitfield name="C9" low="18" high="19" type="a3xx_intp_mode"/> + <bitfield name="CA" low="20" high="21" type="a3xx_intp_mode"/> + <bitfield name="CB" low="22" high="23" type="a3xx_intp_mode"/> + <bitfield name="CC" low="24" high="25" type="a3xx_intp_mode"/> + <bitfield name="CD" low="26" high="27" type="a3xx_intp_mode"/> + <bitfield name="CE" low="28" high="29" type="a3xx_intp_mode"/> + <bitfield name="CF" low="30" high="31" type="a3xx_intp_mode"/> + </reg32> + </array> + <array offset="0x2286" name="VPC_VARYING_PS_REPL" stride="1" length="4"> + <reg32 offset="0x0" name="MODE"> + <bitfield name="C0" low="0" high="1" type="a3xx_repl_mode"/> + <bitfield name="C1" low="2" high="3" type="a3xx_repl_mode"/> + <bitfield name="C2" low="4" high="5" type="a3xx_repl_mode"/> + <bitfield name="C3" low="6" high="7" type="a3xx_repl_mode"/> + <bitfield name="C4" low="8" high="9" type="a3xx_repl_mode"/> + <bitfield name="C5" low="10" high="11" type="a3xx_repl_mode"/> + <bitfield name="C6" low="12" high="13" type="a3xx_repl_mode"/> + <bitfield name="C7" low="14" high="15" type="a3xx_repl_mode"/> + <bitfield name="C8" low="16" high="17" type="a3xx_repl_mode"/> + <bitfield name="C9" low="18" high="19" type="a3xx_repl_mode"/> + <bitfield name="CA" low="20" high="21" type="a3xx_repl_mode"/> + <bitfield name="CB" low="22" high="23" type="a3xx_repl_mode"/> + <bitfield name="CC" low="24" high="25" type="a3xx_repl_mode"/> + <bitfield name="CD" low="26" high="27" type="a3xx_repl_mode"/> + <bitfield name="CE" low="28" high="29" type="a3xx_repl_mode"/> + <bitfield name="CF" low="30" high="31" type="a3xx_repl_mode"/> + </reg32> + </array> + <reg32 offset="0x228a" name="VPC_VARY_CYLWRAP_ENABLE_0"/> + <reg32 offset="0x228b" name="VPC_VARY_CYLWRAP_ENABLE_1"/> + + <!-- SP registers --> + <bitset name="a3xx_vs_fs_length_reg" inline="yes"> + <bitfield name="SHADERLENGTH" low="0" high="31" type="uint"/> + </bitset> + + <bitset name="sp_vs_fs_obj_offset_reg" inline="yes"> + <bitfield name="FIRSTEXECINSTROFFSET" low="0" high="15" type="uint"/> + <doc> + From register spec: + SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object + start offset in on chip RAM, + 128bit aligned + </doc> + <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/> + <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/> + </bitset> + + <reg32 offset="0x22c0" name="SP_SP_CTRL_REG"> + <!-- this bit is set during resolve pass: --> + <bitfield name="RESOLVE" pos="16" type="boolean"/> + <bitfield name="CONSTMODE" pos="18" type="uint"/> + <bitfield name="BINNING" pos="19" type="boolean"/> + <bitfield name="SLEEPMODE" low="20" high="21" type="uint"/> + <!-- L0MODE==1 when oxiliForceSpL0ModeBuffer=1 --> + <bitfield name="L0MODE" low="22" high="23" type="uint"/> + </reg32> + <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0"> + <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> + <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/> + <!-- maybe CACHEINVALID is two bits?? --> + <bitfield name="CACHEINVALID" pos="2" type="boolean"/> + <bitfield name="ALUSCHMODE" pos="3" type="boolean"/> + <doc> + The full/half register footprint is in units of four components, + so if r0.x is used, that counts as all of r0.[xyzw] as used. + There are separate full/half register footprint values as the + full and half registers are independent (not overlapping). + Presumably the thread scheduler hardware allocates the full/half + register names from the actual physical register file and + handles the register renaming. + </doc> + <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/> + <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/> + <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/> + <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/> + <doc> + From regspec: + SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits. + If bit31 is 1, it means overflow + or any long shader. + </doc> + <bitfield name="LENGTH" low="24" high="31" type="uint"/> + </reg32> + <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1"> + <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/> + <!-- + not sure about full vs half const.. I can't get blob generate + something with a mediump/lowp uniform. + --> + <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/> + <bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/> + </reg32> + <reg32 offset="0x22c6" name="SP_VS_PARAM_REG"> + <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/> + <bitfield name="POS2DMODE" pos="16" type="boolean"/> + <bitfield name="TOTALVSOUTVAR" low="20" high="24" type="uint"/> + </reg32> + <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="A_HALF" pos="8" type="boolean"/> + <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/> + <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> + <bitfield name="B_HALF" pos="24" type="boolean"/> + <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/> + </reg32> + </array> + <array offset="0x22d0" name="SP_VS_VPC_DST" stride="1" length="4"> + <reg32 offset="0x0" name="REG"> + <doc> + These seem to be offsets for storage of the varyings. + Always seems to start from 8, possibly loc 0 and 4 + are for gl_Position and gl_PointSize? + </doc> + <bitfield name="OUTLOC0" low="0" high="6" type="uint"/> + <bitfield name="OUTLOC1" low="8" high="14" type="uint"/> + <bitfield name="OUTLOC2" low="16" high="22" type="uint"/> + <bitfield name="OUTLOC3" low="24" high="30" type="uint"/> + </reg32> + </array> + <reg32 offset="0x22d4" name="SP_VS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/> + <doc> + SP_VS_OBJ_START_REG contains pointer to the vertex shader program, + immediately followed by the binning shader program (although I + guess that is probably just re-using the same gpu buffer) + </doc> + <reg32 offset="0x22d5" name="SP_VS_OBJ_START_REG"/> + <reg32 offset="0x22d6" name="SP_VS_PVT_MEM_PARAM_REG"> + <bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/> + <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/> + <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/> + </reg32> + <reg32 offset="0x22d7" name="SP_VS_PVT_MEM_ADDR_REG"> + <bitfield name="BURSTLEN" low="0" high="4"/> + <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/> + </reg32> + <reg32 offset="0x22d8" name="SP_VS_PVT_MEM_SIZE_REG"/> + <reg32 offset="0x22df" name="SP_VS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/> + <reg32 offset="0x22e0" name="SP_FS_CTRL_REG0"> + <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> + <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/> + <!-- maybe CACHEINVALID is two bits?? --> + <bitfield name="CACHEINVALID" pos="2" type="boolean"/> + <bitfield name="ALUSCHMODE" pos="3" type="boolean"/> + <doc> + The full/half register footprint is in units of four components, + so if r0.x is used, that counts as all of r0.[xyzw] as used. + There are separate full/half register footprint values as the + full and half registers are independent (not overlapping). + Presumably the thread scheduler hardware allocates the full/half + register names from the actual physical register file and + handles the register renaming. + </doc> + <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/> + <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/> + <bitfield name="FSBYPASSENABLE" pos="17" type="boolean"/> + <bitfield name="INOUTREGOVERLAP" pos="18" type="boolean"/> + <bitfield name="OUTORDERED" pos="19" type="boolean"/> + <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/> + <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/> + <bitfield name="PIXLODENABLE" pos="22" type="boolean"/> + <bitfield name="COMPUTEMODE" pos="23" type="boolean"/> + <doc> + From regspec: + SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits. + If bit31 is 1, it means overflow + or any long shader. + </doc> + <bitfield name="LENGTH" low="24" high="31" type="uint"/> + </reg32> + <reg32 offset="0x22e1" name="SP_FS_CTRL_REG1"> + <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/> + <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/> + <bitfield name="INITIALOUTSTANDING" low="20" high="23" type="uint"/> + <bitfield name="HALFPRECVAROFFSET" low="24" high="30" type="uint"/> + </reg32> + <reg32 offset="0x22e2" name="SP_FS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/> + <doc>SP_FS_OBJ_START_REG contains pointer to fragment shader program</doc> + <reg32 offset="0x22e3" name="SP_FS_OBJ_START_REG"/> + <reg32 offset="0x22e4" name="SP_FS_PVT_MEM_PARAM_REG"> + <bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/> + <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/> + <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/> + </reg32> + <reg32 offset="0x22e5" name="SP_FS_PVT_MEM_ADDR_REG"> + <bitfield name="BURSTLEN" low="0" high="4"/> + <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/> + </reg32> + <reg32 offset="0x22e6" name="SP_FS_PVT_MEM_SIZE_REG"/> + <reg32 offset="0x22e8" name="SP_FS_FLAT_SHAD_MODE_REG_0"> + <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc> + </reg32> + <reg32 offset="0x22e9" name="SP_FS_FLAT_SHAD_MODE_REG_1"> + <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc> + </reg32> + <reg32 offset="0x22ec" name="SP_FS_OUTPUT_REG"> + <bitfield name="MRT" low="0" high="1" type="uint"> + <doc>render targets - 1</doc> + </bitfield> + <bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/> + <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> + </reg32> + <array offset="0x22f0" name="SP_FS_MRT" stride="1" length="4"> + <reg32 offset="0x0" name="REG"> + <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="HALF_PRECISION" pos="8" type="boolean"/> + <bitfield name="SINT" pos="10" type="boolean"/> + <bitfield name="UINT" pos="11" type="boolean"/> + </reg32> + </array> + <array offset="0x22f4" name="SP_FS_IMAGE_OUTPUT" stride="1" length="4"> + <reg32 offset="0x0" name="REG"> + <bitfield name="MRTFORMAT" low="0" high="5" type="a3xx_color_fmt"/> + </reg32> + </array> + <reg32 offset="0x22ff" name="SP_FS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/> + + <reg32 offset="0x2301" name="PA_SC_AA_CONFIG"/> + <!-- TPL1 registers --> + <!-- assume VS/FS_TEX_OFFSET is same --> + <bitset name="a3xx_tpl1_tp_vs_fs_tex_offset" inline="yes"> + <bitfield name="SAMPLEROFFSET" low="0" high="7" type="uint"/> + <bitfield name="MEMOBJOFFSET" low="8" high="15" type="uint"/> + <!-- not sure the size of this: --> + <bitfield name="BASETABLEPTR" low="16" high="31" type="uint"/> + </bitset> + <reg32 offset="0x2340" name="TPL1_TP_VS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/> + <reg32 offset="0x2341" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/> + <reg32 offset="0x2342" name="TPL1_TP_FS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/> + <reg32 offset="0x2343" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/> + + <!-- VBIF registers --> + <reg32 offset="0x3001" name="VBIF_CLKON"/> + <reg32 offset="0x300c" name="VBIF_FIXED_SORT_EN"/> + <reg32 offset="0x300d" name="VBIF_FIXED_SORT_SEL0"/> + <reg32 offset="0x300e" name="VBIF_FIXED_SORT_SEL1"/> + <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/> + <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/> + <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/> + <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/> + <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/> + <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/> + <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/> + <reg32 offset="0x3034" name="VBIF_OUT_RD_LIM_CONF0"/> + <reg32 offset="0x3035" name="VBIF_OUT_WR_LIM_CONF0"/> + <reg32 offset="0x3036" name="VBIF_DDR_OUT_MAX_BURST"/> + <reg32 offset="0x303c" name="VBIF_ARB_CTL"/> + <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/> + <reg32 offset="0x3058" name="VBIF_OUT_AXI_AMEMTYPE_CONF0"/> + <reg32 offset="0x305e" name="VBIF_OUT_AXI_AOOO_EN"/> + <reg32 offset="0x305f" name="VBIF_OUT_AXI_AOOO"/> + + <bitset name="a3xx_vbif_perf_cnt" inline="yes"> + <bitfield name="CNT0" pos="0" type="boolean"/> + <bitfield name="CNT1" pos="1" type="boolean"/> + <bitfield name="PWRCNT0" pos="2" type="boolean"/> + <bitfield name="PWRCNT1" pos="3" type="boolean"/> + <bitfield name="PWRCNT2" pos="4" type="boolean"/> + </bitset> + + <reg32 offset="0x3070" name="VBIF_PERF_CNT_EN" type="a3xx_vbif_perf_cnt"/> + <reg32 offset="0x3071" name="VBIF_PERF_CNT_CLR" type="a3xx_vbif_perf_cnt"/> + <reg32 offset="0x3072" name="VBIF_PERF_CNT_SEL"/> + <reg32 offset="0x3073" name="VBIF_PERF_CNT0_LO"/> + <reg32 offset="0x3074" name="VBIF_PERF_CNT0_HI"/> + <reg32 offset="0x3075" name="VBIF_PERF_CNT1_LO"/> + <reg32 offset="0x3076" name="VBIF_PERF_CNT1_HI"/> + <reg32 offset="0x3077" name="VBIF_PERF_PWR_CNT0_LO"/> + <reg32 offset="0x3078" name="VBIF_PERF_PWR_CNT0_HI"/> + <reg32 offset="0x3079" name="VBIF_PERF_PWR_CNT1_LO"/> + <reg32 offset="0x307a" name="VBIF_PERF_PWR_CNT1_HI"/> + <reg32 offset="0x307b" name="VBIF_PERF_PWR_CNT2_LO"/> + <reg32 offset="0x307c" name="VBIF_PERF_PWR_CNT2_HI"/> + + + <reg32 offset="0x0c01" name="VSC_BIN_SIZE"> + <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/> + <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/> + </reg32> + + <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS"/> + <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8"> + <reg32 offset="0x0" name="CONFIG"> + <doc> + Configures the mapping between VSC_PIPE buffer and + bin, X/Y specify the bin index in the horiz/vert + direction (0,0 is upper left, 0,1 is leftmost bin + on second row, and so on). W/H specify the number + of bins assigned to this VSC_PIPE in the horiz/vert + dimension. + </doc> + <bitfield name="X" low="0" high="9" type="uint"/> + <bitfield name="Y" low="10" high="19" type="uint"/> + <bitfield name="W" low="20" high="23" type="uint"/> + <bitfield name="H" low="24" high="27" type="uint"/> + </reg32> + <reg32 offset="0x1" name="DATA_ADDRESS"/> + <reg32 offset="0x2" name="DATA_LENGTH"/> + </array> + <reg32 offset="0x0c3c" name="VSC_BIN_CONTROL"> + <doc>seems to be set to 0x00000001 during binning pass</doc> + <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x0c3d" name="UNKNOWN_0C3D"> + <doc>seems to be always set to 0x00000001</doc> + </reg32> + <reg32 offset="0x0c48" name="PC_PERFCOUNTER0_SELECT" type="a3xx_pc_perfcounter_select"/> + <reg32 offset="0x0c49" name="PC_PERFCOUNTER1_SELECT" type="a3xx_pc_perfcounter_select"/> + <reg32 offset="0x0c4a" name="PC_PERFCOUNTER2_SELECT" type="a3xx_pc_perfcounter_select"/> + <reg32 offset="0x0c4b" name="PC_PERFCOUNTER3_SELECT" type="a3xx_pc_perfcounter_select"/> + <reg32 offset="0x0c81" name="GRAS_TSE_DEBUG_ECO"> + <doc>seems to be always set to 0x00000001</doc> + </reg32> + + <reg32 offset="0x0c88" name="GRAS_PERFCOUNTER0_SELECT" type="a3xx_gras_tse_perfcounter_select"/> + <reg32 offset="0x0c89" name="GRAS_PERFCOUNTER1_SELECT" type="a3xx_gras_tse_perfcounter_select"/> + <reg32 offset="0x0c8a" name="GRAS_PERFCOUNTER2_SELECT" type="a3xx_gras_ras_perfcounter_select"/> + <reg32 offset="0x0c8b" name="GRAS_PERFCOUNTER3_SELECT" type="a3xx_gras_ras_perfcounter_select"/> + <array offset="0x0ca0" name="GRAS_CL_USER_PLANE" stride="4" length="6"> + <reg32 offset="0x0" name="X"/> + <reg32 offset="0x1" name="Y"/> + <reg32 offset="0x2" name="Z"/> + <reg32 offset="0x3" name="W"/> + </array> + <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/> + <reg32 offset="0x0cc1" name="RB_DEBUG_ECO_CONTROLS_ADDR"/> + <reg32 offset="0x0cc6" name="RB_PERFCOUNTER0_SELECT" type="a3xx_rb_perfcounter_select"/> + <reg32 offset="0x0cc7" name="RB_PERFCOUNTER1_SELECT" type="a3xx_rb_perfcounter_select"/> + <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION"> + <bitfield name="WIDTH" low="0" high="13" type="uint"/> + <bitfield name="HEIGHT" low="14" high="27" type="uint"/> + </reg32> + <reg32 offset="0x0e00" name="HLSQ_PERFCOUNTER0_SELECT" type="a3xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e01" name="HLSQ_PERFCOUNTER1_SELECT" type="a3xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e02" name="HLSQ_PERFCOUNTER2_SELECT" type="a3xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e03" name="HLSQ_PERFCOUNTER3_SELECT" type="a3xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e04" name="HLSQ_PERFCOUNTER4_SELECT" type="a3xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e05" name="HLSQ_PERFCOUNTER5_SELECT" type="a3xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e43" name="UNKNOWN_0E43"> + <doc>seems to be always set to 0x00000001</doc> + </reg32> + <reg32 offset="0x0e44" name="VFD_PERFCOUNTER0_SELECT" type="a3xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e45" name="VFD_PERFCOUNTER1_SELECT" type="a3xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e61" name="VPC_VPC_DEBUG_RAM_SEL"/> + <reg32 offset="0x0e62" name="VPC_VPC_DEBUG_RAM_READ"/> + <reg32 offset="0x0e64" name="VPC_PERFCOUNTER0_SELECT" type="a3xx_vpc_perfcounter_select"/> + <reg32 offset="0x0e65" name="VPC_PERFCOUNTER1_SELECT" type="a3xx_vpc_perfcounter_select"/> + <reg32 offset="0x0e82" name="UCHE_CACHE_MODE_CONTROL_REG"/> + <reg32 offset="0x0e84" name="UCHE_PERFCOUNTER0_SELECT" type="a3xx_uche_perfcounter_select"/> + <reg32 offset="0x0e85" name="UCHE_PERFCOUNTER1_SELECT" type="a3xx_uche_perfcounter_select"/> + <reg32 offset="0x0e86" name="UCHE_PERFCOUNTER2_SELECT" type="a3xx_uche_perfcounter_select"/> + <reg32 offset="0x0e87" name="UCHE_PERFCOUNTER3_SELECT" type="a3xx_uche_perfcounter_select"/> + <reg32 offset="0x0e88" name="UCHE_PERFCOUNTER4_SELECT" type="a3xx_uche_perfcounter_select"/> + <reg32 offset="0x0e89" name="UCHE_PERFCOUNTER5_SELECT" type="a3xx_uche_perfcounter_select"/> + <reg32 offset="0x0ea0" name="UCHE_CACHE_INVALIDATE0_REG"> + <!-- might be shifted right by 5, assuming 32byte cache line size.. --> + <bitfield name="ADDR" low="0" high="27" type="hex"/> + </reg32> + <reg32 offset="0x0ea1" name="UCHE_CACHE_INVALIDATE1_REG"> + <!-- might be shifted right by 5, assuming 32byte cache line size.. --> + <bitfield name="ADDR" low="0" high="27" type="hex"/> + <!-- I'd assume 2 bits, for FLUSH/INVALIDATE/CLEAN? --> + <bitfield name="OPCODE" low="28" high="29" type="a3xx_cache_opcode"/> + <bitfield name="ENTIRE_CACHE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x0ea6" name="UNKNOWN_0EA6"/> + <reg32 offset="0x0ec4" name="SP_PERFCOUNTER0_SELECT" type="a3xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec5" name="SP_PERFCOUNTER1_SELECT" type="a3xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec6" name="SP_PERFCOUNTER2_SELECT" type="a3xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec7" name="SP_PERFCOUNTER3_SELECT" type="a3xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec8" name="SP_PERFCOUNTER4_SELECT" type="a3xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec9" name="SP_PERFCOUNTER5_SELECT" type="a3xx_sp_perfcounter_select"/> + <reg32 offset="0x0eca" name="SP_PERFCOUNTER6_SELECT" type="a3xx_sp_perfcounter_select"/> + <reg32 offset="0x0ecb" name="SP_PERFCOUNTER7_SELECT" type="a3xx_sp_perfcounter_select"/> + <reg32 offset="0x0ee0" name="UNKNOWN_0EE0"> + <doc>seems to be always set to 0x00000003</doc> + </reg32> + <reg32 offset="0x0f03" name="UNKNOWN_0F03"> + <doc>seems to be always set to 0x00000001</doc> + </reg32> + <reg32 offset="0x0f04" name="TP_PERFCOUNTER0_SELECT" type="a3xx_tp_perfcounter_select"/> + <reg32 offset="0x0f05" name="TP_PERFCOUNTER1_SELECT" type="a3xx_tp_perfcounter_select"/> + <reg32 offset="0x0f06" name="TP_PERFCOUNTER2_SELECT" type="a3xx_tp_perfcounter_select"/> + <reg32 offset="0x0f07" name="TP_PERFCOUNTER3_SELECT" type="a3xx_tp_perfcounter_select"/> + <reg32 offset="0x0f08" name="TP_PERFCOUNTER4_SELECT" type="a3xx_tp_perfcounter_select"/> + <reg32 offset="0x0f09" name="TP_PERFCOUNTER5_SELECT" type="a3xx_tp_perfcounter_select"/> + + <!-- this seems to be the register that CP_RUN_OPENCL writes: --> + <reg32 offset="0x21f0" name="VGT_CL_INITIATOR"/> + + <!-- seems to be same as a2xx according to fwdump.. --> + <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/> + <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/> + <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/> +</domain> + +<domain name="A3XX_TEX_SAMP" width="32"> + <doc>Texture sampler dwords</doc> + <enum name="a3xx_tex_filter"> + <value name="A3XX_TEX_NEAREST" value="0"/> + <value name="A3XX_TEX_LINEAR" value="1"/> + <value name="A3XX_TEX_ANISO" value="2"/> + </enum> + <enum name="a3xx_tex_clamp"> + <value name="A3XX_TEX_REPEAT" value="0"/> + <value name="A3XX_TEX_CLAMP_TO_EDGE" value="1"/> + <value name="A3XX_TEX_MIRROR_REPEAT" value="2"/> + <value name="A3XX_TEX_CLAMP_TO_BORDER" value="3"/> + <value name="A3XX_TEX_MIRROR_CLAMP" value="4"/> + </enum> + <enum name="a3xx_tex_aniso"> + <value name="A3XX_TEX_ANISO_1" value="0"/> + <value name="A3XX_TEX_ANISO_2" value="1"/> + <value name="A3XX_TEX_ANISO_4" value="2"/> + <value name="A3XX_TEX_ANISO_8" value="3"/> + <value name="A3XX_TEX_ANISO_16" value="4"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="CLAMPENABLE" pos="0" type="boolean"/> + <bitfield name="MIPFILTER_LINEAR" pos="1" type="boolean"/> + <bitfield name="XY_MAG" low="2" high="3" type="a3xx_tex_filter"/> + <bitfield name="XY_MIN" low="4" high="5" type="a3xx_tex_filter"/> + <bitfield name="WRAP_S" low="6" high="8" type="a3xx_tex_clamp"/> + <bitfield name="WRAP_T" low="9" high="11" type="a3xx_tex_clamp"/> + <bitfield name="WRAP_R" low="12" high="14" type="a3xx_tex_clamp"/> + <bitfield name="ANISO" low="15" high="17" type="a3xx_tex_aniso"/> + <bitfield name="COMPARE_FUNC" low="20" high="22" type="adreno_compare_func"/> + <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="24" type="boolean"/> + <!-- UNNORM_COORDS == CLK_NORMALIZED_COORDS_FALSE --> + <bitfield name="UNNORM_COORDS" pos="31" type="boolean"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="LOD_BIAS" low="0" high="10" type="fixed" radix="6"/> + <bitfield name="MAX_LOD" low="12" high="21" type="ufixed" radix="6"/> + <bitfield name="MIN_LOD" low="22" high="31" type="ufixed" radix="6"/> + </reg32> +</domain> + +<domain name="A3XX_TEX_CONST" width="32"> + <doc>Texture constant dwords</doc> + <enum name="a3xx_tex_swiz"> + <!-- same as a2xx? --> + <value name="A3XX_TEX_X" value="0"/> + <value name="A3XX_TEX_Y" value="1"/> + <value name="A3XX_TEX_Z" value="2"/> + <value name="A3XX_TEX_W" value="3"/> + <value name="A3XX_TEX_ZERO" value="4"/> + <value name="A3XX_TEX_ONE" value="5"/> + </enum> + <enum name="a3xx_tex_type"> + <value name="A3XX_TEX_1D" value="0"/> + <value name="A3XX_TEX_2D" value="1"/> + <value name="A3XX_TEX_CUBE" value="2"/> + <value name="A3XX_TEX_3D" value="3"/> + </enum> + <enum name="a3xx_tex_msaa"> + <value name="A3XX_TPL1_MSAA1X" value="0"/> + <value name="A3XX_TPL1_MSAA2X" value="1"/> + <value name="A3XX_TPL1_MSAA4X" value="2"/> + <value name="A3XX_TPL1_MSAA8X" value="3"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="TILE_MODE" low="0" high="1" type="a3xx_tile_mode"/> + <bitfield name="SRGB" pos="2" type="boolean"/> + <bitfield name="SWIZ_X" low="4" high="6" type="a3xx_tex_swiz"/> + <bitfield name="SWIZ_Y" low="7" high="9" type="a3xx_tex_swiz"/> + <bitfield name="SWIZ_Z" low="10" high="12" type="a3xx_tex_swiz"/> + <bitfield name="SWIZ_W" low="13" high="15" type="a3xx_tex_swiz"/> + <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> + <bitfield name="MSAATEX" low="20" high="21" type="a3xx_tex_msaa"/> + <bitfield name="FMT" low="22" high="28" type="a3xx_tex_fmt"/> + <bitfield name="NOCONVERT" pos="29" type="boolean"/> + <bitfield name="TYPE" low="30" high="31" type="a3xx_tex_type"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="HEIGHT" low="0" high="13" type="uint"/> + <bitfield name="WIDTH" low="14" high="27" type="uint"/> + <bitfield name="FETCHSIZE" low="28" high="31" type="a3xx_tex_fetchsize"/> + </reg32> + <reg32 offset="2" name="2"> + <doc>INDX is index of texture address(es) in MIPMAP state block</doc> + <bitfield name="INDX" low="0" high="8" type="uint"/> + <doc>Pitch in bytes (so actually stride)</doc> + <bitfield name="PITCH" low="12" high="29" type="uint"/> + <doc>SWAP bit is set for BGRA instead of RGBA</doc> + <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> + </reg32> + <reg32 offset="3" name="3"> + <!-- + Update: the two LAYERSZn seem not to be the same thing. + According to Ilia's experimentation the first one goes up + to at *least* bit 14.. + --> + <bitfield name="LAYERSZ1" low="0" high="16" shr="12" type="uint"/> + <bitfield name="DEPTH" low="17" high="27" type="uint"/> + <bitfield name="LAYERSZ2" low="28" high="31" shr="12" type="uint"/> + </reg32> +</domain> + +</database> diff --git a/src/freedreno/registers/a3xx.xml.h b/src/freedreno/registers/a3xx.xml.h deleted file mode 100644 index 70cc5ea5ed9..00000000000 --- a/src/freedreno/registers/a3xx.xml.h +++ /dev/null @@ -1,3246 +0,0 @@ -#ifndef A3XX_XML -#define A3XX_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2019 by the following authors: -- Rob Clark <[email protected]> (robclark) -- Ilia Mirkin <[email protected]> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum a3xx_tile_mode { - LINEAR = 0, - TILE_4X4 = 1, - TILE_32X32 = 2, - TILE_4X2 = 3, -}; - -enum a3xx_state_block_id { - HLSQ_BLOCK_ID_TP_TEX = 2, - HLSQ_BLOCK_ID_TP_MIPMAP = 3, - HLSQ_BLOCK_ID_SP_VS = 4, - HLSQ_BLOCK_ID_SP_FS = 6, -}; - -enum a3xx_cache_opcode { - INVALIDATE = 1, -}; - -enum a3xx_vtx_fmt { - VFMT_32_FLOAT = 0, - VFMT_32_32_FLOAT = 1, - VFMT_32_32_32_FLOAT = 2, - VFMT_32_32_32_32_FLOAT = 3, - VFMT_16_FLOAT = 4, - VFMT_16_16_FLOAT = 5, - VFMT_16_16_16_FLOAT = 6, - VFMT_16_16_16_16_FLOAT = 7, - VFMT_32_FIXED = 8, - VFMT_32_32_FIXED = 9, - VFMT_32_32_32_FIXED = 10, - VFMT_32_32_32_32_FIXED = 11, - VFMT_16_SINT = 16, - VFMT_16_16_SINT = 17, - VFMT_16_16_16_SINT = 18, - VFMT_16_16_16_16_SINT = 19, - VFMT_16_UINT = 20, - VFMT_16_16_UINT = 21, - VFMT_16_16_16_UINT = 22, - VFMT_16_16_16_16_UINT = 23, - VFMT_16_SNORM = 24, - VFMT_16_16_SNORM = 25, - VFMT_16_16_16_SNORM = 26, - VFMT_16_16_16_16_SNORM = 27, - VFMT_16_UNORM = 28, - VFMT_16_16_UNORM = 29, - VFMT_16_16_16_UNORM = 30, - VFMT_16_16_16_16_UNORM = 31, - VFMT_32_UINT = 32, - VFMT_32_32_UINT = 33, - VFMT_32_32_32_UINT = 34, - VFMT_32_32_32_32_UINT = 35, - VFMT_32_SINT = 36, - VFMT_32_32_SINT = 37, - VFMT_32_32_32_SINT = 38, - VFMT_32_32_32_32_SINT = 39, - VFMT_8_UINT = 40, - VFMT_8_8_UINT = 41, - VFMT_8_8_8_UINT = 42, - VFMT_8_8_8_8_UINT = 43, - VFMT_8_UNORM = 44, - VFMT_8_8_UNORM = 45, - VFMT_8_8_8_UNORM = 46, - VFMT_8_8_8_8_UNORM = 47, - VFMT_8_SINT = 48, - VFMT_8_8_SINT = 49, - VFMT_8_8_8_SINT = 50, - VFMT_8_8_8_8_SINT = 51, - VFMT_8_SNORM = 52, - VFMT_8_8_SNORM = 53, - VFMT_8_8_8_SNORM = 54, - VFMT_8_8_8_8_SNORM = 55, - VFMT_10_10_10_2_UINT = 56, - VFMT_10_10_10_2_UNORM = 57, - VFMT_10_10_10_2_SINT = 58, - VFMT_10_10_10_2_SNORM = 59, - VFMT_2_10_10_10_UINT = 60, - VFMT_2_10_10_10_UNORM = 61, - VFMT_2_10_10_10_SINT = 62, - VFMT_2_10_10_10_SNORM = 63, -}; - -enum a3xx_tex_fmt { - TFMT_5_6_5_UNORM = 4, - TFMT_5_5_5_1_UNORM = 5, - TFMT_4_4_4_4_UNORM = 7, - TFMT_Z16_UNORM = 9, - TFMT_X8Z24_UNORM = 10, - TFMT_Z32_FLOAT = 11, - TFMT_UV_64X32 = 16, - TFMT_VU_64X32 = 17, - TFMT_Y_64X32 = 18, - TFMT_NV12_64X32 = 19, - TFMT_UV_LINEAR = 20, - TFMT_VU_LINEAR = 21, - TFMT_Y_LINEAR = 22, - TFMT_NV12_LINEAR = 23, - TFMT_I420_Y = 24, - TFMT_I420_U = 26, - TFMT_I420_V = 27, - TFMT_ATC_RGB = 32, - TFMT_ATC_RGBA_EXPLICIT = 33, - TFMT_ETC1 = 34, - TFMT_ATC_RGBA_INTERPOLATED = 35, - TFMT_DXT1 = 36, - TFMT_DXT3 = 37, - TFMT_DXT5 = 38, - TFMT_2_10_10_10_UNORM = 40, - TFMT_10_10_10_2_UNORM = 41, - TFMT_9_9_9_E5_FLOAT = 42, - TFMT_11_11_10_FLOAT = 43, - TFMT_A8_UNORM = 44, - TFMT_L8_UNORM = 45, - TFMT_L8_A8_UNORM = 47, - TFMT_8_UNORM = 48, - TFMT_8_8_UNORM = 49, - TFMT_8_8_8_UNORM = 50, - TFMT_8_8_8_8_UNORM = 51, - TFMT_8_SNORM = 52, - TFMT_8_8_SNORM = 53, - TFMT_8_8_8_SNORM = 54, - TFMT_8_8_8_8_SNORM = 55, - TFMT_8_UINT = 56, - TFMT_8_8_UINT = 57, - TFMT_8_8_8_UINT = 58, - TFMT_8_8_8_8_UINT = 59, - TFMT_8_SINT = 60, - TFMT_8_8_SINT = 61, - TFMT_8_8_8_SINT = 62, - TFMT_8_8_8_8_SINT = 63, - TFMT_16_FLOAT = 64, - TFMT_16_16_FLOAT = 65, - TFMT_16_16_16_16_FLOAT = 67, - TFMT_16_UINT = 68, - TFMT_16_16_UINT = 69, - TFMT_16_16_16_16_UINT = 71, - TFMT_16_SINT = 72, - TFMT_16_16_SINT = 73, - TFMT_16_16_16_16_SINT = 75, - TFMT_16_UNORM = 76, - TFMT_16_16_UNORM = 77, - TFMT_16_16_16_16_UNORM = 79, - TFMT_16_SNORM = 80, - TFMT_16_16_SNORM = 81, - TFMT_16_16_16_16_SNORM = 83, - TFMT_32_FLOAT = 84, - TFMT_32_32_FLOAT = 85, - TFMT_32_32_32_32_FLOAT = 87, - TFMT_32_UINT = 88, - TFMT_32_32_UINT = 89, - TFMT_32_32_32_32_UINT = 91, - TFMT_32_SINT = 92, - TFMT_32_32_SINT = 93, - TFMT_32_32_32_32_SINT = 95, - TFMT_2_10_10_10_UINT = 96, - TFMT_10_10_10_2_UINT = 97, - TFMT_ETC2_RG11_SNORM = 112, - TFMT_ETC2_RG11_UNORM = 113, - TFMT_ETC2_R11_SNORM = 114, - TFMT_ETC2_R11_UNORM = 115, - TFMT_ETC2_RGBA8 = 116, - TFMT_ETC2_RGB8A1 = 117, - TFMT_ETC2_RGB8 = 118, -}; - -enum a3xx_tex_fetchsize { - TFETCH_DISABLE = 0, - TFETCH_1_BYTE = 1, - TFETCH_2_BYTE = 2, - TFETCH_4_BYTE = 3, - TFETCH_8_BYTE = 4, - TFETCH_16_BYTE = 5, -}; - -enum a3xx_color_fmt { - RB_R5G6B5_UNORM = 0, - RB_R5G5B5A1_UNORM = 1, - RB_R4G4B4A4_UNORM = 3, - RB_R8G8B8_UNORM = 4, - RB_R8G8B8A8_UNORM = 8, - RB_R8G8B8A8_SNORM = 9, - RB_R8G8B8A8_UINT = 10, - RB_R8G8B8A8_SINT = 11, - RB_R8G8_UNORM = 12, - RB_R8G8_SNORM = 13, - RB_R8_UINT = 14, - RB_R8_SINT = 15, - RB_R10G10B10A2_UNORM = 16, - RB_A2R10G10B10_UNORM = 17, - RB_R10G10B10A2_UINT = 18, - RB_A2R10G10B10_UINT = 19, - RB_A8_UNORM = 20, - RB_R8_UNORM = 21, - RB_R16_FLOAT = 24, - RB_R16G16_FLOAT = 25, - RB_R16G16B16A16_FLOAT = 27, - RB_R11G11B10_FLOAT = 28, - RB_R16_SNORM = 32, - RB_R16G16_SNORM = 33, - RB_R16G16B16A16_SNORM = 35, - RB_R16_UNORM = 36, - RB_R16G16_UNORM = 37, - RB_R16G16B16A16_UNORM = 39, - RB_R16_SINT = 40, - RB_R16G16_SINT = 41, - RB_R16G16B16A16_SINT = 43, - RB_R16_UINT = 44, - RB_R16G16_UINT = 45, - RB_R16G16B16A16_UINT = 47, - RB_R32_FLOAT = 48, - RB_R32G32_FLOAT = 49, - RB_R32G32B32A32_FLOAT = 51, - RB_R32_SINT = 52, - RB_R32G32_SINT = 53, - RB_R32G32B32A32_SINT = 55, - RB_R32_UINT = 56, - RB_R32G32_UINT = 57, - RB_R32G32B32A32_UINT = 59, -}; - -enum a3xx_cp_perfcounter_select { - CP_ALWAYS_COUNT = 0, - CP_AHB_PFPTRANS_WAIT = 3, - CP_AHB_NRTTRANS_WAIT = 6, - CP_CSF_NRT_READ_WAIT = 8, - CP_CSF_I1_FIFO_FULL = 9, - CP_CSF_I2_FIFO_FULL = 10, - CP_CSF_ST_FIFO_FULL = 11, - CP_RESERVED_12 = 12, - CP_CSF_RING_ROQ_FULL = 13, - CP_CSF_I1_ROQ_FULL = 14, - CP_CSF_I2_ROQ_FULL = 15, - CP_CSF_ST_ROQ_FULL = 16, - CP_RESERVED_17 = 17, - CP_MIU_TAG_MEM_FULL = 18, - CP_MIU_NRT_WRITE_STALLED = 22, - CP_MIU_NRT_READ_STALLED = 23, - CP_ME_REGS_RB_DONE_FIFO_FULL = 26, - CP_ME_REGS_VS_EVENT_FIFO_FULL = 27, - CP_ME_REGS_PS_EVENT_FIFO_FULL = 28, - CP_ME_REGS_CF_EVENT_FIFO_FULL = 29, - CP_ME_MICRO_RB_STARVED = 30, - CP_AHB_RBBM_DWORD_SENT = 40, - CP_ME_BUSY_CLOCKS = 41, - CP_ME_WAIT_CONTEXT_AVAIL = 42, - CP_PFP_TYPE0_PACKET = 43, - CP_PFP_TYPE3_PACKET = 44, - CP_CSF_RB_WPTR_NEQ_RPTR = 45, - CP_CSF_I1_SIZE_NEQ_ZERO = 46, - CP_CSF_I2_SIZE_NEQ_ZERO = 47, - CP_CSF_RBI1I2_FETCHING = 48, -}; - -enum a3xx_gras_tse_perfcounter_select { - GRAS_TSEPERF_INPUT_PRIM = 0, - GRAS_TSEPERF_INPUT_NULL_PRIM = 1, - GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2, - GRAS_TSEPERF_CLIPPED_PRIM = 3, - GRAS_TSEPERF_NEW_PRIM = 4, - GRAS_TSEPERF_ZERO_AREA_PRIM = 5, - GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6, - GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7, - GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8, - GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9, - GRAS_TSEPERF_PRE_CLIP_PRIM = 10, - GRAS_TSEPERF_POST_CLIP_PRIM = 11, - GRAS_TSEPERF_WORKING_CYCLES = 12, - GRAS_TSEPERF_PC_STARVE = 13, - GRAS_TSERASPERF_STALL = 14, -}; - -enum a3xx_gras_ras_perfcounter_select { - GRAS_RASPERF_16X16_TILES = 0, - GRAS_RASPERF_8X8_TILES = 1, - GRAS_RASPERF_4X4_TILES = 2, - GRAS_RASPERF_WORKING_CYCLES = 3, - GRAS_RASPERF_STALL_CYCLES_BY_RB = 4, - GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5, - GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6, -}; - -enum a3xx_hlsq_perfcounter_select { - HLSQ_PERF_SP_VS_CONSTANT = 0, - HLSQ_PERF_SP_VS_INSTRUCTIONS = 1, - HLSQ_PERF_SP_FS_CONSTANT = 2, - HLSQ_PERF_SP_FS_INSTRUCTIONS = 3, - HLSQ_PERF_TP_STATE = 4, - HLSQ_PERF_QUADS = 5, - HLSQ_PERF_PIXELS = 6, - HLSQ_PERF_VERTICES = 7, - HLSQ_PERF_FS8_THREADS = 8, - HLSQ_PERF_FS16_THREADS = 9, - HLSQ_PERF_FS32_THREADS = 10, - HLSQ_PERF_VS8_THREADS = 11, - HLSQ_PERF_VS16_THREADS = 12, - HLSQ_PERF_SP_VS_DATA_BYTES = 13, - HLSQ_PERF_SP_FS_DATA_BYTES = 14, - HLSQ_PERF_ACTIVE_CYCLES = 15, - HLSQ_PERF_STALL_CYCLES_SP_STATE = 16, - HLSQ_PERF_STALL_CYCLES_SP_VS = 17, - HLSQ_PERF_STALL_CYCLES_SP_FS = 18, - HLSQ_PERF_STALL_CYCLES_UCHE = 19, - HLSQ_PERF_RBBM_LOAD_CYCLES = 20, - HLSQ_PERF_DI_TO_VS_START_SP0 = 21, - HLSQ_PERF_DI_TO_FS_START_SP0 = 22, - HLSQ_PERF_VS_START_TO_DONE_SP0 = 23, - HLSQ_PERF_FS_START_TO_DONE_SP0 = 24, - HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25, - HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26, - HLSQ_PERF_UCHE_LATENCY_CYCLES = 27, - HLSQ_PERF_UCHE_LATENCY_COUNT = 28, -}; - -enum a3xx_pc_perfcounter_select { - PC_PCPERF_VISIBILITY_STREAMS = 0, - PC_PCPERF_TOTAL_INSTANCES = 1, - PC_PCPERF_PRIMITIVES_PC_VPC = 2, - PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3, - PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4, - PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5, - PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6, - PC_PCPERF_VERTICES_TO_VFD = 7, - PC_PCPERF_REUSED_VERTICES = 8, - PC_PCPERF_CYCLES_STALLED_BY_VFD = 9, - PC_PCPERF_CYCLES_STALLED_BY_TSE = 10, - PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11, - PC_PCPERF_CYCLES_IS_WORKING = 12, -}; - -enum a3xx_rb_perfcounter_select { - RB_RBPERF_ACTIVE_CYCLES_ANY = 0, - RB_RBPERF_ACTIVE_CYCLES_ALL = 1, - RB_RBPERF_STARVE_CYCLES_BY_SP = 2, - RB_RBPERF_STARVE_CYCLES_BY_RAS = 3, - RB_RBPERF_STARVE_CYCLES_BY_MARB = 4, - RB_RBPERF_STALL_CYCLES_BY_MARB = 5, - RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6, - RB_RBPERF_RB_MARB_DATA = 7, - RB_RBPERF_SP_RB_QUAD = 8, - RB_RBPERF_RAS_EARLY_Z_QUADS = 9, - RB_RBPERF_GMEM_CH0_READ = 10, - RB_RBPERF_GMEM_CH1_READ = 11, - RB_RBPERF_GMEM_CH0_WRITE = 12, - RB_RBPERF_GMEM_CH1_WRITE = 13, - RB_RBPERF_CP_CONTEXT_DONE = 14, - RB_RBPERF_CP_CACHE_FLUSH = 15, - RB_RBPERF_CP_ZPASS_DONE = 16, -}; - -enum a3xx_rbbm_perfcounter_select { - RBBM_ALAWYS_ON = 0, - RBBM_VBIF_BUSY = 1, - RBBM_TSE_BUSY = 2, - RBBM_RAS_BUSY = 3, - RBBM_PC_DCALL_BUSY = 4, - RBBM_PC_VSD_BUSY = 5, - RBBM_VFD_BUSY = 6, - RBBM_VPC_BUSY = 7, - RBBM_UCHE_BUSY = 8, - RBBM_VSC_BUSY = 9, - RBBM_HLSQ_BUSY = 10, - RBBM_ANY_RB_BUSY = 11, - RBBM_ANY_TEX_BUSY = 12, - RBBM_ANY_USP_BUSY = 13, - RBBM_ANY_MARB_BUSY = 14, - RBBM_ANY_ARB_BUSY = 15, - RBBM_AHB_STATUS_BUSY = 16, - RBBM_AHB_STATUS_STALLED = 17, - RBBM_AHB_STATUS_TXFR = 18, - RBBM_AHB_STATUS_TXFR_SPLIT = 19, - RBBM_AHB_STATUS_TXFR_ERROR = 20, - RBBM_AHB_STATUS_LONG_STALL = 21, - RBBM_RBBM_STATUS_MASKED = 22, -}; - -enum a3xx_sp_perfcounter_select { - SP_LM_LOAD_INSTRUCTIONS = 0, - SP_LM_STORE_INSTRUCTIONS = 1, - SP_LM_ATOMICS = 2, - SP_UCHE_LOAD_INSTRUCTIONS = 3, - SP_UCHE_STORE_INSTRUCTIONS = 4, - SP_UCHE_ATOMICS = 5, - SP_VS_TEX_INSTRUCTIONS = 6, - SP_VS_CFLOW_INSTRUCTIONS = 7, - SP_VS_EFU_INSTRUCTIONS = 8, - SP_VS_FULL_ALU_INSTRUCTIONS = 9, - SP_VS_HALF_ALU_INSTRUCTIONS = 10, - SP_FS_TEX_INSTRUCTIONS = 11, - SP_FS_CFLOW_INSTRUCTIONS = 12, - SP_FS_EFU_INSTRUCTIONS = 13, - SP_FS_FULL_ALU_INSTRUCTIONS = 14, - SP_FS_HALF_ALU_INSTRUCTIONS = 15, - SP_FS_BARY_INSTRUCTIONS = 16, - SP_VS_INSTRUCTIONS = 17, - SP_FS_INSTRUCTIONS = 18, - SP_ADDR_LOCK_COUNT = 19, - SP_UCHE_READ_TRANS = 20, - SP_UCHE_WRITE_TRANS = 21, - SP_EXPORT_VPC_TRANS = 22, - SP_EXPORT_RB_TRANS = 23, - SP_PIXELS_KILLED = 24, - SP_ICL1_REQUESTS = 25, - SP_ICL1_MISSES = 26, - SP_ICL0_REQUESTS = 27, - SP_ICL0_MISSES = 28, - SP_ALU_ACTIVE_CYCLES = 29, - SP_EFU_ACTIVE_CYCLES = 30, - SP_STALL_CYCLES_BY_VPC = 31, - SP_STALL_CYCLES_BY_TP = 32, - SP_STALL_CYCLES_BY_UCHE = 33, - SP_STALL_CYCLES_BY_RB = 34, - SP_ACTIVE_CYCLES_ANY = 35, - SP_ACTIVE_CYCLES_ALL = 36, -}; - -enum a3xx_tp_perfcounter_select { - TPL1_TPPERF_L1_REQUESTS = 0, - TPL1_TPPERF_TP0_L1_REQUESTS = 1, - TPL1_TPPERF_TP0_L1_MISSES = 2, - TPL1_TPPERF_TP1_L1_REQUESTS = 3, - TPL1_TPPERF_TP1_L1_MISSES = 4, - TPL1_TPPERF_TP2_L1_REQUESTS = 5, - TPL1_TPPERF_TP2_L1_MISSES = 6, - TPL1_TPPERF_TP3_L1_REQUESTS = 7, - TPL1_TPPERF_TP3_L1_MISSES = 8, - TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9, - TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10, - TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11, - TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12, - TPL1_TPPERF_BILINEAR_OPS = 13, - TPL1_TPPERF_QUADSQUADS_OFFSET = 14, - TPL1_TPPERF_QUADQUADS_SHADOW = 15, - TPL1_TPPERF_QUADS_ARRAY = 16, - TPL1_TPPERF_QUADS_PROJECTION = 17, - TPL1_TPPERF_QUADS_GRADIENT = 18, - TPL1_TPPERF_QUADS_1D2D = 19, - TPL1_TPPERF_QUADS_3DCUBE = 20, - TPL1_TPPERF_ZERO_LOD = 21, - TPL1_TPPERF_OUTPUT_TEXELS = 22, - TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23, - TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24, - TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25, - TPL1_TPPERF_LATENCY = 26, - TPL1_TPPERF_LATENCY_TRANS = 27, -}; - -enum a3xx_vfd_perfcounter_select { - VFD_PERF_UCHE_BYTE_FETCHED = 0, - VFD_PERF_UCHE_TRANS = 1, - VFD_PERF_VPC_BYPASS_COMPONENTS = 2, - VFD_PERF_FETCH_INSTRUCTIONS = 3, - VFD_PERF_DECODE_INSTRUCTIONS = 4, - VFD_PERF_ACTIVE_CYCLES = 5, - VFD_PERF_STALL_CYCLES_UCHE = 6, - VFD_PERF_STALL_CYCLES_HLSQ = 7, - VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8, - VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9, -}; - -enum a3xx_vpc_perfcounter_select { - VPC_PERF_SP_LM_PRIMITIVES = 0, - VPC_PERF_COMPONENTS_FROM_SP = 1, - VPC_PERF_SP_LM_COMPONENTS = 2, - VPC_PERF_ACTIVE_CYCLES = 3, - VPC_PERF_STALL_CYCLES_LM = 4, - VPC_PERF_STALL_CYCLES_RAS = 5, -}; - -enum a3xx_uche_perfcounter_select { - UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0, - UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1, - UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2, - UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3, - UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4, - UCHE_UCHEPERF_READ_REQUESTS_TP = 8, - UCHE_UCHEPERF_READ_REQUESTS_VFD = 9, - UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10, - UCHE_UCHEPERF_READ_REQUESTS_MARB = 11, - UCHE_UCHEPERF_READ_REQUESTS_SP = 12, - UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13, - UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14, - UCHE_UCHEPERF_TAG_CHECK_FAILS = 15, - UCHE_UCHEPERF_EVICTS = 16, - UCHE_UCHEPERF_FLUSHES = 17, - UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18, - UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19, - UCHE_UCHEPERF_ACTIVE_CYCLES = 20, -}; - -enum a3xx_intp_mode { - SMOOTH = 0, - FLAT = 1, - ZERO = 2, - ONE = 3, -}; - -enum a3xx_repl_mode { - S = 1, - T = 2, - ONE_T = 3, -}; - -enum a3xx_tex_filter { - A3XX_TEX_NEAREST = 0, - A3XX_TEX_LINEAR = 1, - A3XX_TEX_ANISO = 2, -}; - -enum a3xx_tex_clamp { - A3XX_TEX_REPEAT = 0, - A3XX_TEX_CLAMP_TO_EDGE = 1, - A3XX_TEX_MIRROR_REPEAT = 2, - A3XX_TEX_CLAMP_TO_BORDER = 3, - A3XX_TEX_MIRROR_CLAMP = 4, -}; - -enum a3xx_tex_aniso { - A3XX_TEX_ANISO_1 = 0, - A3XX_TEX_ANISO_2 = 1, - A3XX_TEX_ANISO_4 = 2, - A3XX_TEX_ANISO_8 = 3, - A3XX_TEX_ANISO_16 = 4, -}; - -enum a3xx_tex_swiz { - A3XX_TEX_X = 0, - A3XX_TEX_Y = 1, - A3XX_TEX_Z = 2, - A3XX_TEX_W = 3, - A3XX_TEX_ZERO = 4, - A3XX_TEX_ONE = 5, -}; - -enum a3xx_tex_type { - A3XX_TEX_1D = 0, - A3XX_TEX_2D = 1, - A3XX_TEX_CUBE = 2, - A3XX_TEX_3D = 3, -}; - -enum a3xx_tex_msaa { - A3XX_TPL1_MSAA1X = 0, - A3XX_TPL1_MSAA2X = 1, - A3XX_TPL1_MSAA4X = 2, - A3XX_TPL1_MSAA8X = 3, -}; - -#define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 -#define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 -#define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 -#define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 -#define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 -#define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 -#define A3XX_INT0_VFD_ERROR 0x00000040 -#define A3XX_INT0_CP_SW_INT 0x00000080 -#define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 -#define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 -#define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 -#define A3XX_INT0_CP_HW_FAULT 0x00000800 -#define A3XX_INT0_CP_DMA 0x00001000 -#define A3XX_INT0_CP_IB2_INT 0x00002000 -#define A3XX_INT0_CP_IB1_INT 0x00004000 -#define A3XX_INT0_CP_RB_INT 0x00008000 -#define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 -#define A3XX_INT0_CP_RB_DONE_TS 0x00020000 -#define A3XX_INT0_CP_VS_DONE_TS 0x00040000 -#define A3XX_INT0_CP_PS_DONE_TS 0x00080000 -#define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 -#define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 -#define A3XX_INT0_MISC_HANG_DETECT 0x01000000 -#define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 -#define REG_A3XX_RBBM_HW_VERSION 0x00000000 - -#define REG_A3XX_RBBM_HW_RELEASE 0x00000001 - -#define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 - -#define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 - -#define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 - -#define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 - -#define REG_A3XX_RBBM_AHB_CTL0 0x00000020 - -#define REG_A3XX_RBBM_AHB_CTL1 0x00000021 - -#define REG_A3XX_RBBM_AHB_CMD 0x00000022 - -#define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 - -#define REG_A3XX_RBBM_GPR0_CTL 0x0000002e - -#define REG_A3XX_RBBM_STATUS 0x00000030 -#define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 -#define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 -#define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 -#define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 -#define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 -#define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 -#define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 -#define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 -#define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 -#define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 -#define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 -#define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 -#define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 -#define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 -#define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 -#define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 -#define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 -#define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 -#define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 -#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 -#define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 - -#define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 - -#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 - -#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 - -#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 - -#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 - -#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 - -#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a - -#define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 - -#define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 - -#define REG_A3XX_RBBM_INT_0_MASK 0x00000063 - -#define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 - -#define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 -#define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 - -#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 - -#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 - -#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 - -#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 - -#define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 - -#define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 - -#define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 - -#define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 - -#define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 - -#define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 - -#define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 - -#define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 - -#define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 - -#define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 - -#define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 - -#define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 - -#define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 - -#define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a - -#define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b - -#define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c - -#define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d - -#define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e - -#define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f - -#define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 - -#define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac - -#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad - -#define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae - -#define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af - -#define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 - -#define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 - -#define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 - -#define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 - -#define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 - -#define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 - -#define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 - -#define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 - -#define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 - -#define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 - -#define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba - -#define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb - -#define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc - -#define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd - -#define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be - -#define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf - -#define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 - -#define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 - -#define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 - -#define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 - -#define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 - -#define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 - -#define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 - -#define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 - -#define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 - -#define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 - -#define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca - -#define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb - -#define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc - -#define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd - -#define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce - -#define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf - -#define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 - -#define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 - -#define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 - -#define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 - -#define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 - -#define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 - -#define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 - -#define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 - -#define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 - -#define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 - -#define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da - -#define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db - -#define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc - -#define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd - -#define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de - -#define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df - -#define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 - -#define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 - -#define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 - -#define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 - -#define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 - -#define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 - -#define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea - -#define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb - -#define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec - -#define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed - -#define REG_A3XX_RBBM_RBBM_CTL 0x00000100 - -#define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 - -#define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 - -#define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 - -#define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca - -#define REG_A3XX_CP_ROQ_ADDR 0x000001cc - -#define REG_A3XX_CP_ROQ_DATA 0x000001cd - -#define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 - -#define REG_A3XX_CP_MERCIU_DATA 0x000001d2 - -#define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 - -#define REG_A3XX_CP_MEQ_ADDR 0x000001da - -#define REG_A3XX_CP_MEQ_DATA 0x000001db - -#define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5 - -#define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d - -#define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 - -#define REG_A3XX_CP_HW_FAULT 0x0000045c - -#define REG_A3XX_CP_PROTECT_CTRL 0x0000045e - -#define REG_A3XX_CP_PROTECT_STATUS 0x0000045f - -static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } - -static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } - -#define REG_A3XX_CP_AHB_FAULT 0x0000054d - -#define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00 - -#define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02 - -#define REG_A3XX_TP0_CHICKEN 0x00000e1e - -#define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22 - -#define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23 - -#define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 -#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 -#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 -#define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 -#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 -#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 -#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 -#define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 -#define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 -#define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 -#define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 -#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK 0x1c000000 -#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26 -static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) -{ - return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK; -} - -#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 -#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff -#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 -static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) -{ - return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; -} -#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 -#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 -static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) -{ - return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; -} - -#define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 -#define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff -#define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 -static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) -{ - return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; -} - -#define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 -#define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff -#define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 -static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) -{ - return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; -} - -#define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a -#define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff -#define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 -static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) -{ - return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; -} - -#define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b -#define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff -#define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 -static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) -{ - return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; -} - -#define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c -#define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff -#define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 -static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) -{ - return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; -} - -#define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d -#define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff -#define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 -static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) -{ - return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; -} - -#define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 -#define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff -#define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 -static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) -{ - return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; -} -#define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 -#define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 -static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) -{ - return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; -} - -#define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 -#define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff -#define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0 -static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) -{ - return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; -} - -#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c -#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff -#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 -static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) -{ - return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; -} - -#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d -#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff -#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 -static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) -{ - return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; -} - -#define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 -#define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 -#define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 -#define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 -#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 -#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 -static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) -{ - return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; -} -#define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 - -#define REG_A3XX_GRAS_SC_CONTROL 0x00002072 -#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 -#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 -static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) -{ - return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; -} -#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 -#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 -static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; -} -#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 -#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 -static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) -{ - return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; -} - -#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 -#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff -#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 -static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) -{ - return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; -} -#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 -#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 -static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) -{ - return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; -} - -#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 -#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff -#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 -static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) -{ - return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; -} -#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 -#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 -static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) -{ - return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; -} - -#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 -#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff -#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 -static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) -{ - return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; -} -#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 -#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 -static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) -{ - return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; -} - -#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a -#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff -#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 -static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) -{ - return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; -} -#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 -#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 -static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) -{ - return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; -} - -#define REG_A3XX_RB_MODE_CONTROL 0x000020c0 -#define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 -#define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 -#define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 -static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) -{ - return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; -} -#define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000 -#define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12 -static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) -{ - return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK; -} -#define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 -#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 - -#define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 -#define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE 0x00000001 -#define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE 0x00000002 -#define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE 0x00000004 -#define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 -#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 -#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 -static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; -} -#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 -#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 -#define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000 -#define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000 -#define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000 -#define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000 -#define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000 -#define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000 -#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 -#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 -#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 -static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) -{ - return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; -} -#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE 0x40000000 -#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE 0x80000000 - -#define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 -#define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 -#define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 -#define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 -static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; -} -#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 -#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 -static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) -{ - return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; -} - -#define REG_A3XX_RB_ALPHA_REF 0x000020c3 -#define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 -#define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 -static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) -{ - return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; -} -#define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 -#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 -static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; -} - -static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } - -static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } -#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 -#define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 -#define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 -#define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 -#define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 -static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) -{ - return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; -} -#define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 -#define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 -static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) -{ - return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; -} -#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 -#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 -static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) -{ - return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; -} - -static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } -#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f -#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) -{ - return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; -} -#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 -#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 -static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) -{ - return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; -} -#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 -static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; -} -#define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000 -#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 -#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 -static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; -} - -static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } -#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 -#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 -static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; -} - -static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } -#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f -#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 -static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; -} -#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 -#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 -static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; -} -#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 -#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 -static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; -} -#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 -#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 -static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; -} -#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 -#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 -static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; -} -#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 -#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 -static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; -} -#define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 - -#define REG_A3XX_RB_BLEND_RED 0x000020e4 -#define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff -#define A3XX_RB_BLEND_RED_UINT__SHIFT 0 -static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) -{ - return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; -} -#define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 -#define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 -static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; -} - -#define REG_A3XX_RB_BLEND_GREEN 0x000020e5 -#define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff -#define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 -static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) -{ - return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; -} -#define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 -#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 -static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; -} - -#define REG_A3XX_RB_BLEND_BLUE 0x000020e6 -#define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff -#define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 -static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) -{ - return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; -} -#define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 -#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 -static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; -} - -#define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 -#define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff -#define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 -static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) -{ - return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; -} -#define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 -#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 -static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; -} - -#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 - -#define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 - -#define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea - -#define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb - -#define REG_A3XX_RB_COPY_CONTROL 0x000020ec -#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 -#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 -static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) -{ - return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; -} -#define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008 -#define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 -#define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 -static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) -{ - return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; -} -#define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE 0x00000080 -#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 -#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 -static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) -{ - return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; -} -#define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE 0x00001000 -#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 -#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 -static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) -{ - assert(!(val & 0x3fff)); - return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; -} - -#define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed -#define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 -#define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 -static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; -} - -#define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee -#define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff -#define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 -static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; -} - -#define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef -#define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 -#define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 -static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) -{ - return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; -} -#define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc -#define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 -static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) -{ - return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; -} -#define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 -#define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 -static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; -} -#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 -#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 -static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) -{ - return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; -} -#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 -#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 -static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) -{ - return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; -} -#define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 -#define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 -static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) -{ - return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; -} - -#define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 -#define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 -#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 -#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 -#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 -#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 -#define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 -static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) -{ - return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; -} -#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 -#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 - -#define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 - -#define REG_A3XX_RB_DEPTH_INFO 0x00002102 -#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 -#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 -static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) -{ - return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; -} -#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 -#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 -static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; -} - -#define REG_A3XX_RB_DEPTH_PITCH 0x00002103 -#define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff -#define A3XX_RB_DEPTH_PITCH__SHIFT 0 -static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) -{ - assert(!(val & 0x7)); - return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; -} - -#define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 -#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 -#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 -#define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 -#define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 -#define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 -static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) -{ - return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; -} -#define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 -#define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 -static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) -{ - return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; -} -#define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 -#define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 -static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) -{ - return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; -} -#define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 -#define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 -static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) -{ - return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; -} -#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 -#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 -static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) -{ - return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; -} -#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 -#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 -static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; -} -#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 -#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 -static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) -{ - return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; -} -#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 -#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 -static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; -} - -#define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 - -#define REG_A3XX_RB_STENCIL_INFO 0x00002106 -#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800 -#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11 -static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; -} - -#define REG_A3XX_RB_STENCIL_PITCH 0x00002107 -#define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff -#define A3XX_RB_STENCIL_PITCH__SHIFT 0 -static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) -{ - assert(!(val & 0x7)); - return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; -} - -#define REG_A3XX_RB_STENCILREFMASK 0x00002108 -#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff -#define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 -static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) -{ - return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; -} -#define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 -#define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 -static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) -{ - return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; -} -#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 -#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 -static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) -{ - return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; -} - -#define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 -#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff -#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 -static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) -{ - return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; -} -#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 -#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 -static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) -{ - return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; -} -#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 -#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 -static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) -{ - return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; -} - -#define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c -#define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 - -#define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e -#define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff -#define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 -static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) -{ - return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; -} -#define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 -#define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 -static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) -{ - return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 -#define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001 -#define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 - -#define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 - -#define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 - -#define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 - -#define REG_A3XX_VGT_BIN_BASE 0x000021e1 - -#define REG_A3XX_VGT_BIN_SIZE 0x000021e2 - -#define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 -#define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 -#define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 -static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) -{ - return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; -} -#define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 -#define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22 -static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) -{ - return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; -} - -#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea - -#define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec -#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f -#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 -static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) -{ - return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; -} -#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 -#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 -static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; -} -#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 -#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 -static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; -} -#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000 -#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 -#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 -#define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 - -#define REG_A3XX_PC_RESTART_INDEX 0x000021ed - -#define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 -#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030 -#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 -static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; -} -#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 -#define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100 -#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 -#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 -#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000 -#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12 -static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK; -} -#define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000 -#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 -#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 -#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 -static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; -} -#define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 -#define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 -#define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 -#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 - -#define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 -#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0 -#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 -static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; -} -#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 -#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000 -#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16 -static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK; -} -#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000 -#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24 -static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK; -} - -#define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 -#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc -#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2 -static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK; -} -#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000 -#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18 -static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK; -} -#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 -#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 -static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; -} - -#define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 -#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff -#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 -static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK; -} - -#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 -#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff -#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 -static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) -{ - return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; -} -#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 -#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 -static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) -{ - return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; -} -#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 -#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 -static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) -{ - return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; -} - -#define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 -#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff -#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 -static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) -{ - return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; -} -#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 -#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 -static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) -{ - return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; -} -#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 -#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 -static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) -{ - return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; -} - -#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 -#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff -#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 -static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; -} -#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 -#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 -static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; -} - -#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 -#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff -#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 -static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; -} -#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 -#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 -static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; -} - -#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a -#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003 -#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0 -static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; -} -#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc -#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2 -static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; -} -#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000 -#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12 -static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; -} -#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000 -#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22 -static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) -{ - return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; -} - -static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } - -static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } - -static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } - -#define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 - -#define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 - -#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 - -static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } - -static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } - -#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 - -#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 - -#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a - -#define REG_A3XX_VFD_CONTROL_0 0x00002240 -#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff -#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 -static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) -{ - return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; -} -#define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 -#define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 -static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) -{ - return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; -} -#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 -#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 -static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) -{ - return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; -} -#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 -#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 -static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) -{ - return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; -} - -#define REG_A3XX_VFD_CONTROL_1 0x00002241 -#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f -#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 -static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) -{ - return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; -} -#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0 -#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4 -static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) -{ - return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK; -} -#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00 -#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8 -static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) -{ - return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK; -} -#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 -#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 -static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) -{ - return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; -} -#define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 -#define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 -static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) -{ - return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; -} - -#define REG_A3XX_VFD_INDEX_MIN 0x00002242 - -#define REG_A3XX_VFD_INDEX_MAX 0x00002243 - -#define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 - -#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 - -#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 - -static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } - -static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } -#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f -#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 -static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) -{ - return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; -} -#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80 -#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 -static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) -{ - return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; -} -#define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000 -#define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 -#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 -#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 -static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) -{ - return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; -} -#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 -#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 -static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) -{ - return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; -} - -static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } - -static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } - -static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } -#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f -#define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 -static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) -{ - return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; -} -#define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 -#define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 -#define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 -static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) -{ - return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; -} -#define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 -#define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 -static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) -{ - return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; -} -#define A3XX_VFD_DECODE_INSTR_INT 0x00100000 -#define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 -#define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 -static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; -} -#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 -#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 -static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) -{ - return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; -} -#define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 -#define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 - -#define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e -#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f -#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 -static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) -{ - return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; -} -#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 -#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 -static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) -{ - return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; -} - -#define REG_A3XX_VPC_ATTR 0x00002280 -#define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff -#define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 -static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) -{ - return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; -} -#define A3XX_VPC_ATTR_PSIZE 0x00000200 -#define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 -#define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 -static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) -{ - return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; -} -#define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 -#define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 -static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) -{ - return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; -} - -#define REG_A3XX_VPC_PACK 0x00002281 -#define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 -#define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 -static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) -{ - return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; -} -#define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 -#define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 -static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) -{ - return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; -} - -static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } - -static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } -#define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003 -#define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c -#define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030 -#define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0 -#define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300 -#define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00 -#define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000 -#define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000 -#define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000 -#define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000 -#define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000 -#define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000 -#define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000 -#define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000 -#define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000 -#define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; -} -#define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000 -#define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30 -static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) -{ - return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; -} - -static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } - -static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } -#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003 -#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c -#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030 -#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0 -#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300 -#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00 -#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK; -} -#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000 -#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30 -static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) -{ - return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK; -} - -#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a - -#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b - -#define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 -#define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 -#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 -#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 -static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) -{ - return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; -} -#define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 -#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 -#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 -static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) -{ - return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; -} -#define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000 -#define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22 -static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) -{ - return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; -} - -#define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 -#define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; -} -#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 -#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 -static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; -} -#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 -#define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008 -#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; -} -#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 -#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 -#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 -static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; -} - -#define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 -#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff -#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 -static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; -} -#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 -#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 -static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; -} -#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 -#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 -static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; -} - -#define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 -#define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff -#define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 -static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) -{ - return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; -} -#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 -#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 -static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) -{ - return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; -} -#define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000 -#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000 -#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 -static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) -{ - return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; -} - -static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } - -static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } -#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff -#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 -static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) -{ - return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; -} -#define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100 -#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 -#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 -static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) -{ - return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; -} -#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 -#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 -static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) -{ - return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; -} -#define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000 -#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 -#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 -static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) -{ - return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; -} - -static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } - -static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) -{ - return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00 -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) -{ - return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000 -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) -{ - return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000 -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) -{ - return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 -#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff -#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 -static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) -{ - return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; -} -#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 -#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 -static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; -} -#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 -#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 -static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; -} - -#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 - -#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 -#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff -#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 -static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) -{ - return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; -} -#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 -#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 -static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) -{ - return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; -} -#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 -#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 -static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) -{ - return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; -} - -#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 -#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f -#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 -static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) -{ - return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; -} -#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 -#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 -static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; -} - -#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 - -#define REG_A3XX_SP_VS_LENGTH_REG 0x000022df -#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff -#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 -static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) -{ - return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; -} - -#define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 -#define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; -} -#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 -#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 -static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; -} -#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 -#define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008 -#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000 -#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000 -#define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000 -#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; -} -#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 -#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 -#define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000 -#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 -#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 -static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; -} - -#define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 -#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff -#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 -static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; -} -#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 -#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 -static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; -} -#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 -#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 -static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; -} -#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000 -#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 -static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; -} - -#define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 -#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff -#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 -static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) -{ - return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; -} -#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 -#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 -static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; -} -#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 -#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 -static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; -} - -#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 - -#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 -#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff -#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 -static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) -{ - return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; -} -#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 -#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 -static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) -{ - return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; -} -#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 -#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 -static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) -{ - return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; -} - -#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 -#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f -#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 -static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) -{ - return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; -} -#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 -#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 -static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; -} - -#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 - -#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 - -#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 - -#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec -#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003 -#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 -static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) -{ - return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK; -} -#define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 -#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 -#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 -static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) -{ - return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; -} - -static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } - -static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } -#define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff -#define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 -static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) -{ - return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; -} -#define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 -#define A3XX_SP_FS_MRT_REG_SINT 0x00000400 -#define A3XX_SP_FS_MRT_REG_UINT 0x00000800 - -static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } - -static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } -#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f -#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 -static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) -{ - return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; -} - -#define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff -#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff -#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 -static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) -{ - return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; -} - -#define REG_A3XX_PA_SC_AA_CONFIG 0x00002301 - -#define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 -#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff -#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 -static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) -{ - return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; -} -#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 -#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 -static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) -{ - return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; -} -#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 -#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 -static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) -{ - return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; -} - -#define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 - -#define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 -#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff -#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 -static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) -{ - return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; -} -#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 -#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 -static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) -{ - return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; -} -#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 -#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 -static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) -{ - return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; -} - -#define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 - -#define REG_A3XX_VBIF_CLKON 0x00003001 - -#define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c - -#define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d - -#define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e - -#define REG_A3XX_VBIF_ABIT_SORT 0x0000301c - -#define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d - -#define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a - -#define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c - -#define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d - -#define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 - -#define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 - -#define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 - -#define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 - -#define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 - -#define REG_A3XX_VBIF_ARB_CTL 0x0000303c - -#define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 - -#define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 - -#define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e - -#define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f - -#define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070 -#define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001 -#define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002 -#define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004 -#define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008 -#define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010 - -#define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071 -#define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001 -#define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002 -#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004 -#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008 -#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010 - -#define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072 - -#define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073 - -#define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074 - -#define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075 - -#define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076 - -#define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077 - -#define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078 - -#define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079 - -#define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a - -#define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b - -#define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c - -#define REG_A3XX_VSC_BIN_SIZE 0x00000c01 -#define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f -#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 -static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; -} -#define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 -#define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 -static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; -} - -#define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 - -static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } - -static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } -#define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff -#define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 -static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) -{ - return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; -} -#define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 -#define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 -static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) -{ - return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; -} -#define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 -#define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 -static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) -{ - return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; -} -#define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 -#define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 -static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) -{ - return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; -} - -static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } - -static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } - -#define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c -#define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 - -#define REG_A3XX_UNKNOWN_0C3D 0x00000c3d - -#define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 - -#define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 - -#define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a - -#define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b - -#define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 - -#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 - -#define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 - -#define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a - -#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b - -static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } - -static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } - -static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } - -static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } - -static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } - -#define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 - -#define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 - -#define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 - -#define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 - -#define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 -#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff -#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 -static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) -{ - return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; -} -#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 -#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 -static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) -{ - return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; -} - -#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 - -#define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 - -#define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 - -#define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 - -#define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 - -#define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 - -#define REG_A3XX_UNKNOWN_0E43 0x00000e43 - -#define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 - -#define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 - -#define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 - -#define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 - -#define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 - -#define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 - -#define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 - -#define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 - -#define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 - -#define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 - -#define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 - -#define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 - -#define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 - -#define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 -#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff -#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 -static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) -{ - return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; -} - -#define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 -#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff -#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 -static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) -{ - return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; -} -#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 -#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 -static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) -{ - return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; -} -#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 - -#define REG_A3XX_UNKNOWN_0EA6 0x00000ea6 - -#define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 - -#define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 - -#define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 - -#define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 - -#define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 - -#define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 - -#define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca - -#define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb - -#define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 - -#define REG_A3XX_UNKNOWN_0F03 0x00000f03 - -#define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 - -#define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 - -#define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 - -#define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 - -#define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 - -#define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 - -#define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 - -#define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 - -#define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc -#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f -#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 -static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; -} -#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 -#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 -static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; -} -#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 -#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 -static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; -} -#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 -#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 -static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) -{ - return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; -} -#define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 -#define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 -#define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 -#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 -#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 -static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) -{ - return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; -} - -#define REG_A3XX_VGT_IMMED_DATA 0x000021fd - -#define REG_A3XX_TEX_SAMP_0 0x00000000 -#define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001 -#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 -#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c -#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 -static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) -{ - return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; -} -#define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 -#define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 -static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) -{ - return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; -} -#define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 -#define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 -static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) -{ - return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; -} -#define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 -#define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 -static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) -{ - return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; -} -#define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 -#define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 -static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) -{ - return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; -} -#define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000 -#define A3XX_TEX_SAMP_0_ANISO__SHIFT 15 -static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) -{ - return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK; -} -#define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000 -#define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20 -static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) -{ - return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; -} -#define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000 -#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 - -#define REG_A3XX_TEX_SAMP_1 0x00000001 -#define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff -#define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0 -static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) -{ - return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; -} -#define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 -#define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 -static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) -{ - return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; -} -#define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 -#define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 -static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) -{ - return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; -} - -#define REG_A3XX_TEX_CONST_0 0x00000000 -#define A3XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 -#define A3XX_TEX_CONST_0_TILE_MODE__SHIFT 0 -static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val) -{ - return ((val) << A3XX_TEX_CONST_0_TILE_MODE__SHIFT) & A3XX_TEX_CONST_0_TILE_MODE__MASK; -} -#define A3XX_TEX_CONST_0_SRGB 0x00000004 -#define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 -#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 -static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) -{ - return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; -} -#define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 -#define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 -static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) -{ - return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; -} -#define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 -#define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 -static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) -{ - return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; -} -#define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 -#define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 -static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) -{ - return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; -} -#define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 -#define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 -static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) -{ - return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; -} -#define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000 -#define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20 -static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) -{ - return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK; -} -#define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 -#define A3XX_TEX_CONST_0_FMT__SHIFT 22 -static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) -{ - return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; -} -#define A3XX_TEX_CONST_0_NOCONVERT 0x20000000 -#define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 -#define A3XX_TEX_CONST_0_TYPE__SHIFT 30 -static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) -{ - return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; -} - -#define REG_A3XX_TEX_CONST_1 0x00000001 -#define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff -#define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 -static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) -{ - return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; -} -#define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 -#define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 -static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) -{ - return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; -} -#define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000 -#define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28 -static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) -{ - return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; -} - -#define REG_A3XX_TEX_CONST_2 0x00000002 -#define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff -#define A3XX_TEX_CONST_2_INDX__SHIFT 0 -static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) -{ - return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; -} -#define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 -#define A3XX_TEX_CONST_2_PITCH__SHIFT 12 -static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) -{ - return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; -} -#define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 -#define A3XX_TEX_CONST_2_SWAP__SHIFT 30 -static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; -} - -#define REG_A3XX_TEX_CONST_3 0x00000003 -#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff -#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 -static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; -} -#define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 -#define A3XX_TEX_CONST_3_DEPTH__SHIFT 17 -static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) -{ - return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; -} -#define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000 -#define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 -static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; -} - - -#endif /* A3XX_XML */ diff --git a/src/freedreno/registers/a4xx.xml b/src/freedreno/registers/a4xx.xml new file mode 100644 index 00000000000..5012e1bd332 --- /dev/null +++ b/src/freedreno/registers/a4xx.xml @@ -0,0 +1,2391 @@ +<?xml version="1.0" encoding="UTF-8"?> +<database xmlns="http://nouveau.freedesktop.org/" +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" +xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> +<import file="freedreno_copyright.xml"/> +<import file="adreno/adreno_common.xml"/> +<import file="adreno/adreno_pm4.xml"/> + +<enum name="a4xx_color_fmt"> + <value name="RB4_A8_UNORM" value="0x01"/> + <value name="RB4_R8_UNORM" value="0x02"/> + <value name="RB4_R8_SNORM" value="0x03"/> + <value name="RB4_R8_UINT" value="0x04"/> + <value name="RB4_R8_SINT" value="0x05"/> + + <value name="RB4_R4G4B4A4_UNORM" value="0x08"/> + <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/> + <value name="RB4_R5G6B5_UNORM" value="0x0e"/> + <value name="RB4_R8G8_UNORM" value="0x0f"/> + <value name="RB4_R8G8_SNORM" value="0x10"/> + <value name="RB4_R8G8_UINT" value="0x11"/> + <value name="RB4_R8G8_SINT" value="0x12"/> + <value name="RB4_R16_UNORM" value="0x13"/> + <value name="RB4_R16_SNORM" value="0x14"/> + <value name="RB4_R16_FLOAT" value="0x15"/> + <value name="RB4_R16_UINT" value="0x16"/> + <value name="RB4_R16_SINT" value="0x17"/> + + <value name="RB4_R8G8B8_UNORM" value="0x19"/> + + <value name="RB4_R8G8B8A8_UNORM" value="0x1a"/> + <value name="RB4_R8G8B8A8_SNORM" value="0x1c"/> + <value name="RB4_R8G8B8A8_UINT" value="0x1d"/> + <value name="RB4_R8G8B8A8_SINT" value="0x1e"/> + <value name="RB4_R10G10B10A2_UNORM" value="0x1f"/> + <value name="RB4_R10G10B10A2_UINT" value="0x22"/> + <value name="RB4_R11G11B10_FLOAT" value="0x27"/> + <value name="RB4_R16G16_UNORM" value="0x28"/> + <value name="RB4_R16G16_SNORM" value="0x29"/> + <value name="RB4_R16G16_FLOAT" value="0x2a"/> + <value name="RB4_R16G16_UINT" value="0x2b"/> + <value name="RB4_R16G16_SINT" value="0x2c"/> + <value name="RB4_R32_FLOAT" value="0x2d"/> + <value name="RB4_R32_UINT" value="0x2e"/> + <value name="RB4_R32_SINT" value="0x2f"/> + + <value name="RB4_R16G16B16A16_UNORM" value="0x34"/> + <value name="RB4_R16G16B16A16_SNORM" value="0x35"/> + <value name="RB4_R16G16B16A16_FLOAT" value="0x36"/> + <value name="RB4_R16G16B16A16_UINT" value="0x37"/> + <value name="RB4_R16G16B16A16_SINT" value="0x38"/> + <value name="RB4_R32G32_FLOAT" value="0x39"/> + <value name="RB4_R32G32_UINT" value="0x3a"/> + <value name="RB4_R32G32_SINT" value="0x3b"/> + + <value name="RB4_R32G32B32A32_FLOAT" value="0x3c"/> + <value name="RB4_R32G32B32A32_UINT" value="0x3d"/> + <value name="RB4_R32G32B32A32_SINT" value="0x3e"/> +</enum> + +<enum name="a4xx_tile_mode"> + <value name="TILE4_LINEAR" value="0"/> + <value name="TILE4_2" value="2"/> + <value name="TILE4_3" value="3"/> +</enum> + +<enum name="a4xx_vtx_fmt" prefix="chipset"> + <!-- hmm, shifted one compared to a3xx?!? --> + <value name="VFMT4_32_FLOAT" value="0x1"/> + <value name="VFMT4_32_32_FLOAT" value="0x2"/> + <value name="VFMT4_32_32_32_FLOAT" value="0x3"/> + <value name="VFMT4_32_32_32_32_FLOAT" value="0x4"/> + + <value name="VFMT4_16_FLOAT" value="0x5"/> + <value name="VFMT4_16_16_FLOAT" value="0x6"/> + <value name="VFMT4_16_16_16_FLOAT" value="0x7"/> + <value name="VFMT4_16_16_16_16_FLOAT" value="0x8"/> + + <value name="VFMT4_32_FIXED" value="0x9"/> + <value name="VFMT4_32_32_FIXED" value="0xa"/> + <value name="VFMT4_32_32_32_FIXED" value="0xb"/> + <value name="VFMT4_32_32_32_32_FIXED" value="0xc"/> + + <value name="VFMT4_11_11_10_FLOAT" value="0xd"/> + + <!-- beyond here it does not appear to be shifted --> + <value name="VFMT4_16_SINT" value="0x10"/> + <value name="VFMT4_16_16_SINT" value="0x11"/> + <value name="VFMT4_16_16_16_SINT" value="0x12"/> + <value name="VFMT4_16_16_16_16_SINT" value="0x13"/> + <value name="VFMT4_16_UINT" value="0x14"/> + <value name="VFMT4_16_16_UINT" value="0x15"/> + <value name="VFMT4_16_16_16_UINT" value="0x16"/> + <value name="VFMT4_16_16_16_16_UINT" value="0x17"/> + <value name="VFMT4_16_SNORM" value="0x18"/> + <value name="VFMT4_16_16_SNORM" value="0x19"/> + <value name="VFMT4_16_16_16_SNORM" value="0x1a"/> + <value name="VFMT4_16_16_16_16_SNORM" value="0x1b"/> + <value name="VFMT4_16_UNORM" value="0x1c"/> + <value name="VFMT4_16_16_UNORM" value="0x1d"/> + <value name="VFMT4_16_16_16_UNORM" value="0x1e"/> + <value name="VFMT4_16_16_16_16_UNORM" value="0x1f"/> + + <value name="VFMT4_32_UINT" value="0x20"/> + <value name="VFMT4_32_32_UINT" value="0x21"/> + <value name="VFMT4_32_32_32_UINT" value="0x22"/> + <value name="VFMT4_32_32_32_32_UINT" value="0x23"/> + <value name="VFMT4_32_SINT" value="0x24"/> + <value name="VFMT4_32_32_SINT" value="0x25"/> + <value name="VFMT4_32_32_32_SINT" value="0x26"/> + <value name="VFMT4_32_32_32_32_SINT" value="0x27"/> + + <value name="VFMT4_8_UINT" value="0x28"/> + <value name="VFMT4_8_8_UINT" value="0x29"/> + <value name="VFMT4_8_8_8_UINT" value="0x2a"/> + <value name="VFMT4_8_8_8_8_UINT" value="0x2b"/> + <value name="VFMT4_8_UNORM" value="0x2c"/> + <value name="VFMT4_8_8_UNORM" value="0x2d"/> + <value name="VFMT4_8_8_8_UNORM" value="0x2e"/> + <value name="VFMT4_8_8_8_8_UNORM" value="0x2f"/> + <value name="VFMT4_8_SINT" value="0x30"/> + <value name="VFMT4_8_8_SINT" value="0x31"/> + <value name="VFMT4_8_8_8_SINT" value="0x32"/> + <value name="VFMT4_8_8_8_8_SINT" value="0x33"/> + <value name="VFMT4_8_SNORM" value="0x34"/> + <value name="VFMT4_8_8_SNORM" value="0x35"/> + <value name="VFMT4_8_8_8_SNORM" value="0x36"/> + <value name="VFMT4_8_8_8_8_SNORM" value="0x37"/> + + <value name="VFMT4_10_10_10_2_UINT" value="0x38"/> + <value name="VFMT4_10_10_10_2_UNORM" value="0x39"/> + <value name="VFMT4_10_10_10_2_SINT" value="0x3a"/> + <value name="VFMT4_10_10_10_2_SNORM" value="0x3b"/> + <value name="VFMT4_2_10_10_10_UINT" value="0x3c"/> + <value name="VFMT4_2_10_10_10_UNORM" value="0x3d"/> + <value name="VFMT4_2_10_10_10_SINT" value="0x3e"/> + <value name="VFMT4_2_10_10_10_SNORM" value="0x3f"/> +</enum> + +<enum name="a4xx_tex_fmt"> + <!-- 0x00 .. 0x02 --> + + <!-- 8-bit formats --> + <value name="TFMT4_A8_UNORM" value="0x03"/> + <value name="TFMT4_8_UNORM" value="0x04"/> + <value name="TFMT4_8_SNORM" value="0x05"/> + <value name="TFMT4_8_UINT" value="0x06"/> + <value name="TFMT4_8_SINT" value="0x07"/> + + <!-- 16-bit formats --> + <value name="TFMT4_4_4_4_4_UNORM" value="0x08"/> + <value name="TFMT4_5_5_5_1_UNORM" value="0x09"/> + <!-- 0x0a --> + <value name="TFMT4_5_6_5_UNORM" value="0x0b"/> + + <!-- 0x0c --> + + <value name="TFMT4_L8_A8_UNORM" value="0x0d"/> + <value name="TFMT4_8_8_UNORM" value="0x0e"/> + <value name="TFMT4_8_8_SNORM" value="0x0f"/> + <value name="TFMT4_8_8_UINT" value="0x10"/> + <value name="TFMT4_8_8_SINT" value="0x11"/> + + <value name="TFMT4_16_UNORM" value="0x12"/> + <value name="TFMT4_16_SNORM" value="0x13"/> + <value name="TFMT4_16_FLOAT" value="0x14"/> + <value name="TFMT4_16_UINT" value="0x15"/> + <value name="TFMT4_16_SINT" value="0x16"/> + + <!-- 0x17 .. 0x1b --> + + <!-- 32-bit formats --> + <value name="TFMT4_8_8_8_8_UNORM" value="0x1c"/> + <value name="TFMT4_8_8_8_8_SNORM" value="0x1d"/> + <value name="TFMT4_8_8_8_8_UINT" value="0x1e"/> + <value name="TFMT4_8_8_8_8_SINT" value="0x1f"/> + + <value name="TFMT4_9_9_9_E5_FLOAT" value="0x20"/> + <value name="TFMT4_10_10_10_2_UNORM" value="0x21"/> + <value name="TFMT4_10_10_10_2_UINT" value="0x22"/> + <!-- 0x23 .. 0x24 --> + <value name="TFMT4_11_11_10_FLOAT" value="0x25"/> + + <value name="TFMT4_16_16_UNORM" value="0x26"/> + <value name="TFMT4_16_16_SNORM" value="0x27"/> + <value name="TFMT4_16_16_FLOAT" value="0x28"/> + <value name="TFMT4_16_16_UINT" value="0x29"/> + <value name="TFMT4_16_16_SINT" value="0x2a"/> + + <value name="TFMT4_32_FLOAT" value="0x2b"/> + <value name="TFMT4_32_UINT" value="0x2c"/> + <value name="TFMT4_32_SINT" value="0x2d"/> + + <!-- 0x2e .. 0x32 --> + + <!-- 64-bit formats --> + <value name="TFMT4_16_16_16_16_UNORM" value="0x33"/> + <value name="TFMT4_16_16_16_16_SNORM" value="0x34"/> + <value name="TFMT4_16_16_16_16_FLOAT" value="0x35"/> + <value name="TFMT4_16_16_16_16_UINT" value="0x36"/> + <value name="TFMT4_16_16_16_16_SINT" value="0x37"/> + + <value name="TFMT4_32_32_FLOAT" value="0x38"/> + <value name="TFMT4_32_32_UINT" value="0x39"/> + <value name="TFMT4_32_32_SINT" value="0x3a"/> + + <!-- 96-bit formats --> + <value name="TFMT4_32_32_32_FLOAT" value="0x3b"/> + <value name="TFMT4_32_32_32_UINT" value="0x3c"/> + <value name="TFMT4_32_32_32_SINT" value="0x3d"/> + + <!-- 0x3e --> + + <!-- 128-bit formats --> + <value name="TFMT4_32_32_32_32_FLOAT" value="0x3f"/> + <value name="TFMT4_32_32_32_32_UINT" value="0x40"/> + <value name="TFMT4_32_32_32_32_SINT" value="0x41"/> + + <!-- 0x42 .. 0x46 --> + <value name="TFMT4_X8Z24_UNORM" value="0x47"/> + <!-- 0x48 .. 0x55 --> + + <!-- compressed formats --> + <value name="TFMT4_DXT1" value="0x56"/> + <value name="TFMT4_DXT3" value="0x57"/> + <value name="TFMT4_DXT5" value="0x58"/> + <!-- 0x59 --> + <value name="TFMT4_RGTC1_UNORM" value="0x5a"/> + <value name="TFMT4_RGTC1_SNORM" value="0x5b"/> + <!-- 0x5c .. 0x5d --> + <value name="TFMT4_RGTC2_UNORM" value="0x5e"/> + <value name="TFMT4_RGTC2_SNORM" value="0x5f"/> + <!-- 0x60 --> + <value name="TFMT4_BPTC_UFLOAT" value="0x61"/> + <value name="TFMT4_BPTC_FLOAT" value="0x62"/> + <value name="TFMT4_BPTC" value="0x63"/> + <value name="TFMT4_ATC_RGB" value="0x64"/> + <value name="TFMT4_ATC_RGBA_EXPLICIT" value="0x65"/> + <value name="TFMT4_ATC_RGBA_INTERPOLATED" value="0x66"/> + <value name="TFMT4_ETC2_RG11_UNORM" value="0x67"/> + <value name="TFMT4_ETC2_RG11_SNORM" value="0x68"/> + <value name="TFMT4_ETC2_R11_UNORM" value="0x69"/> + <value name="TFMT4_ETC2_R11_SNORM" value="0x6a"/> + <value name="TFMT4_ETC1" value="0x6b"/> + <value name="TFMT4_ETC2_RGB8" value="0x6c"/> + <value name="TFMT4_ETC2_RGBA8" value="0x6d"/> + <value name="TFMT4_ETC2_RGB8A1" value="0x6e"/> + <value name="TFMT4_ASTC_4x4" value="0x6f"/> + <value name="TFMT4_ASTC_5x4" value="0x70"/> + <value name="TFMT4_ASTC_5x5" value="0x71"/> + <value name="TFMT4_ASTC_6x5" value="0x72"/> + <value name="TFMT4_ASTC_6x6" value="0x73"/> + <value name="TFMT4_ASTC_8x5" value="0x74"/> + <value name="TFMT4_ASTC_8x6" value="0x75"/> + <value name="TFMT4_ASTC_8x8" value="0x76"/> + <value name="TFMT4_ASTC_10x5" value="0x77"/> + <value name="TFMT4_ASTC_10x6" value="0x78"/> + <value name="TFMT4_ASTC_10x8" value="0x79"/> + <value name="TFMT4_ASTC_10x10" value="0x7a"/> + <value name="TFMT4_ASTC_12x10" value="0x7b"/> + <value name="TFMT4_ASTC_12x12" value="0x7c"/> + <!-- 0x7d .. 0x7f --> +</enum> + +<enum name="a4xx_tex_fetchsize"> + <doc> + Size pixel to fetch, in bytes. Doesn't seem to be required, setting + it to 0x0 seems to work ok, but may be less optimal. + </doc> + <value name="TFETCH4_1_BYTE" value="0"/> + <value name="TFETCH4_2_BYTE" value="1"/> + <value name="TFETCH4_4_BYTE" value="2"/> + <value name="TFETCH4_8_BYTE" value="3"/> + <value name="TFETCH4_16_BYTE" value="4"/> +</enum> + +<enum name="a4xx_depth_format"> + <value name="DEPTH4_NONE" value="0"/> + <value name="DEPTH4_16" value="1"/> + <value name="DEPTH4_24_8" value="2"/> + <value name="DEPTH4_32" value="3"/> +</enum> + +<!-- +NOTE counters extracted from test-perf log with the following awful +script: +################## +#!/bin/bash + +log=$1 + +grep -F "counter +countable +group" $log | grep -v gl > shortlist.txt + +countable="" +IFS=$'\n'; for line in $(cat shortlist.txt); do + # parse ######### group[$n]: $name + l=${line########### group} + if [ $l != $line ]; then + group=`echo $line | awk '{print $3}'` + echo "Group: $group" + continue + fi + # parse ######### counter[$n]: $name + l=${line########### counter} + if [ $l != $line ]; then + countable=`echo $line | awk '{print $3}'` + #echo " Countable: $countable" + continue + fi + # parse countable: + l=${line## countable:} + if [ $l != $line ]; then + val=`echo $line | awk '{print $2}'` + echo "<value value=\"$val\" name=\"$countable\"/>" + fi + +done +################## + --> +<enum name="a4xx_ccu_perfcounter_select"> + <value value="0" name="CCU_BUSY_CYCLES"/> + <value value="2" name="CCU_RB_DEPTH_RETURN_STALL"/> + <value value="3" name="CCU_RB_COLOR_RETURN_STALL"/> + <value value="6" name="CCU_DEPTH_BLOCKS"/> + <value value="7" name="CCU_COLOR_BLOCKS"/> + <value value="8" name="CCU_DEPTH_BLOCK_HIT"/> + <value value="9" name="CCU_COLOR_BLOCK_HIT"/> + <value value="10" name="CCU_DEPTH_FLAG1_COUNT"/> + <value value="11" name="CCU_DEPTH_FLAG2_COUNT"/> + <value value="12" name="CCU_DEPTH_FLAG3_COUNT"/> + <value value="13" name="CCU_DEPTH_FLAG4_COUNT"/> + <value value="14" name="CCU_COLOR_FLAG1_COUNT"/> + <value value="15" name="CCU_COLOR_FLAG2_COUNT"/> + <value value="16" name="CCU_COLOR_FLAG3_COUNT"/> + <value value="17" name="CCU_COLOR_FLAG4_COUNT"/> + <value value="18" name="CCU_PARTIAL_BLOCK_READ"/> +</enum> + +<!-- +NOTE other than CP_ALWAYS_COUNT (which is the only one we use so far), +on a3xx the countable #'s from AMD_performance_monitor disagreed with +TRM. All these #'s for a4xx come from AMD_performance_monitor, so +perhaps they should be taken with a grain of salt +--> +<enum name="a4xx_cp_perfcounter_select"> + <!-- first ctr at least seems same as a3xx, so we can measure freq --> + <value value="0" name="CP_ALWAYS_COUNT"/> + <value value="1" name="CP_BUSY"/> + <value value="2" name="CP_PFP_IDLE"/> + <value value="3" name="CP_PFP_BUSY_WORKING"/> + <value value="4" name="CP_PFP_STALL_CYCLES_ANY"/> + <value value="5" name="CP_PFP_STARVE_CYCLES_ANY"/> + <value value="6" name="CP_PFP_STARVED_PER_LOAD_ADDR"/> + <value value="7" name="CP_PFP_STALLED_PER_STORE_ADDR"/> + <value value="8" name="CP_PFP_PC_PROFILE"/> + <value value="9" name="CP_PFP_MATCH_PM4_PKT_PROFILE"/> + <value value="10" name="CP_PFP_COND_INDIRECT_DISCARDED"/> + <value value="11" name="CP_LONG_RESUMPTIONS"/> + <value value="12" name="CP_RESUME_CYCLES"/> + <value value="13" name="CP_RESUME_TO_BOUNDARY_CYCLES"/> + <value value="14" name="CP_LONG_PREEMPTIONS"/> + <value value="15" name="CP_PREEMPT_CYCLES"/> + <value value="16" name="CP_PREEMPT_TO_BOUNDARY_CYCLES"/> + <value value="17" name="CP_ME_FIFO_EMPTY_PFP_IDLE"/> + <value value="18" name="CP_ME_FIFO_EMPTY_PFP_BUSY"/> + <value value="19" name="CP_ME_FIFO_NOT_EMPTY_NOT_FULL"/> + <value value="20" name="CP_ME_FIFO_FULL_ME_BUSY"/> + <value value="21" name="CP_ME_FIFO_FULL_ME_NON_WORKING"/> + <value value="22" name="CP_ME_WAITING_FOR_PACKETS"/> + <value value="23" name="CP_ME_BUSY_WORKING"/> + <value value="24" name="CP_ME_STARVE_CYCLES_ANY"/> + <value value="25" name="CP_ME_STARVE_CYCLES_PER_PROFILE"/> + <value value="26" name="CP_ME_STALL_CYCLES_PER_PROFILE"/> + <value value="27" name="CP_ME_PC_PROFILE"/> + <value value="28" name="CP_RCIU_FIFO_EMPTY"/> + <value value="29" name="CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL"/> + <value value="30" name="CP_RCIU_FIFO_FULL"/> + <value value="31" name="CP_RCIU_FIFO_FULL_NO_CONTEXT"/> + <value value="32" name="CP_RCIU_FIFO_FULL_AHB_MASTER"/> + <value value="33" name="CP_RCIU_FIFO_FULL_OTHER"/> + <value value="34" name="CP_AHB_IDLE"/> + <value value="35" name="CP_AHB_STALL_ON_GRANT_NO_SPLIT"/> + <value value="36" name="CP_AHB_STALL_ON_GRANT_SPLIT"/> + <value value="37" name="CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE"/> + <value value="38" name="CP_AHB_BUSY_WORKING"/> + <value value="39" name="CP_AHB_BUSY_STALL_ON_HRDY"/> + <value value="40" name="CP_AHB_BUSY_STALL_ON_HRDY_PROFILE"/> +</enum> + +<enum name="a4xx_gras_ras_perfcounter_select"> + <value value="0" name="RAS_SUPER_TILES"/> + <value value="1" name="RAS_8X8_TILES"/> + <value value="2" name="RAS_4X4_TILES"/> + <value value="3" name="RAS_BUSY_CYCLES"/> + <value value="4" name="RAS_STALL_CYCLES_BY_RB"/> + <value value="5" name="RAS_STALL_CYCLES_BY_VSC"/> + <value value="6" name="RAS_STARVE_CYCLES_BY_TSE"/> + <value value="7" name="RAS_SUPERTILE_CYCLES"/> + <value value="8" name="RAS_TILE_CYCLES"/> + <value value="9" name="RAS_FULLY_COVERED_SUPER_TILES"/> + <value value="10" name="RAS_FULLY_COVERED_8X8_TILES"/> + <value value="11" name="RAS_4X4_PRIM"/> + <value value="12" name="RAS_8X4_4X8_PRIM"/> + <value value="13" name="RAS_8X8_PRIM"/> +</enum> + +<enum name="a4xx_gras_tse_perfcounter_select"> + <value value="0" name="TSE_INPUT_PRIM"/> + <value value="1" name="TSE_INPUT_NULL_PRIM"/> + <value value="2" name="TSE_TRIVAL_REJ_PRIM"/> + <value value="3" name="TSE_CLIPPED_PRIM"/> + <value value="4" name="TSE_NEW_PRIM"/> + <value value="5" name="TSE_ZERO_AREA_PRIM"/> + <value value="6" name="TSE_FACENESS_CULLED_PRIM"/> + <value value="7" name="TSE_ZERO_PIXEL_PRIM"/> + <value value="8" name="TSE_OUTPUT_NULL_PRIM"/> + <value value="9" name="TSE_OUTPUT_VISIBLE_PRIM"/> + <value value="10" name="TSE_PRE_CLIP_PRIM"/> + <value value="11" name="TSE_POST_CLIP_PRIM"/> + <value value="12" name="TSE_BUSY_CYCLES"/> + <value value="13" name="TSE_PC_STARVE"/> + <value value="14" name="TSE_RAS_STALL"/> + <value value="15" name="TSE_STALL_BARYPLANE_FIFO_FULL"/> + <value value="16" name="TSE_STALL_ZPLANE_FIFO_FULL"/> +</enum> + +<enum name="a4xx_hlsq_perfcounter_select"> + <value value="0" name="HLSQ_SP_VS_STAGE_CONSTANT"/> + <value value="1" name="HLSQ_SP_VS_STAGE_INSTRUCTIONS"/> + <value value="2" name="HLSQ_SP_FS_STAGE_CONSTANT"/> + <value value="3" name="HLSQ_SP_FS_STAGE_INSTRUCTIONS"/> + <value value="4" name="HLSQ_TP_STATE"/> + <value value="5" name="HLSQ_QUADS"/> + <value value="6" name="HLSQ_PIXELS"/> + <value value="7" name="HLSQ_VERTICES"/> + <value value="13" name="HLSQ_SP_VS_STAGE_DATA_BYTES"/> + <value value="14" name="HLSQ_SP_FS_STAGE_DATA_BYTES"/> + <value value="15" name="HLSQ_BUSY_CYCLES"/> + <value value="16" name="HLSQ_STALL_CYCLES_SP_STATE"/> + <value value="17" name="HLSQ_STALL_CYCLES_SP_VS_STAGE"/> + <value value="18" name="HLSQ_STALL_CYCLES_SP_FS_STAGE"/> + <value value="19" name="HLSQ_STALL_CYCLES_UCHE"/> + <value value="20" name="HLSQ_RBBM_LOAD_CYCLES"/> + <value value="21" name="HLSQ_DI_TO_VS_START_SP"/> + <value value="22" name="HLSQ_DI_TO_FS_START_SP"/> + <value value="23" name="HLSQ_VS_STAGE_START_TO_DONE_SP"/> + <value value="24" name="HLSQ_FS_STAGE_START_TO_DONE_SP"/> + <value value="25" name="HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE"/> + <value value="26" name="HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE"/> + <value value="27" name="HLSQ_UCHE_LATENCY_CYCLES"/> + <value value="28" name="HLSQ_UCHE_LATENCY_COUNT"/> + <value value="29" name="HLSQ_STARVE_CYCLES_VFD"/> +</enum> + +<enum name="a4xx_pc_perfcounter_select"> + <value value="0" name="PC_VIS_STREAMS_LOADED"/> + <value value="2" name="PC_VPC_PRIMITIVES"/> + <value value="3" name="PC_DEAD_PRIM"/> + <value value="4" name="PC_LIVE_PRIM"/> + <value value="5" name="PC_DEAD_DRAWCALLS"/> + <value value="6" name="PC_LIVE_DRAWCALLS"/> + <value value="7" name="PC_VERTEX_MISSES"/> + <value value="9" name="PC_STALL_CYCLES_VFD"/> + <value value="10" name="PC_STALL_CYCLES_TSE"/> + <value value="11" name="PC_STALL_CYCLES_UCHE"/> + <value value="12" name="PC_WORKING_CYCLES"/> + <value value="13" name="PC_IA_VERTICES"/> + <value value="14" name="PC_GS_PRIMITIVES"/> + <value value="15" name="PC_HS_INVOCATIONS"/> + <value value="16" name="PC_DS_INVOCATIONS"/> + <value value="17" name="PC_DS_PRIMITIVES"/> + <value value="20" name="PC_STARVE_CYCLES_FOR_INDEX"/> + <value value="21" name="PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> + <value value="22" name="PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> + <value value="23" name="PC_STALL_CYCLES_TESS"/> + <value value="24" name="PC_STARVE_CYCLES_FOR_POSITION"/> + <value value="25" name="PC_MODE0_DRAWCALL"/> + <value value="26" name="PC_MODE1_DRAWCALL"/> + <value value="27" name="PC_MODE2_DRAWCALL"/> + <value value="28" name="PC_MODE3_DRAWCALL"/> + <value value="29" name="PC_MODE4_DRAWCALL"/> + <value value="30" name="PC_PREDICATED_DEAD_DRAWCALL"/> + <value value="31" name="PC_STALL_CYCLES_BY_TSE_ONLY"/> + <value value="32" name="PC_STALL_CYCLES_BY_VPC_ONLY"/> + <value value="33" name="PC_VPC_POS_DATA_TRANSACTION"/> + <value value="34" name="PC_BUSY_CYCLES"/> + <value value="35" name="PC_STARVE_CYCLES_DI"/> + <value value="36" name="PC_STALL_CYCLES_VPC"/> + <value value="37" name="TESS_WORKING_CYCLES"/> + <value value="38" name="TESS_NUM_CYCLES_SETUP_WORKING"/> + <value value="39" name="TESS_NUM_CYCLES_PTGEN_WORKING"/> + <value value="40" name="TESS_NUM_CYCLES_CONNGEN_WORKING"/> + <value value="41" name="TESS_BUSY_CYCLES"/> + <value value="42" name="TESS_STARVE_CYCLES_PC"/> + <value value="43" name="TESS_STALL_CYCLES_PC"/> +</enum> + +<enum name="a4xx_pwr_perfcounter_select"> + <!-- NOTE not actually used.. see RBBM_RBBM_CTL.RESET_PWR_CTR0/1 --> + <value value="0" name="PWR_CORE_CLOCK_CYCLES"/> + <value value="1" name="PWR_BUSY_CLOCK_CYCLES"/> +</enum> + +<enum name="a4xx_rb_perfcounter_select"> + <value value="0" name="RB_BUSY_CYCLES"/> + <value value="1" name="RB_BUSY_CYCLES_BINNING"/> + <value value="2" name="RB_BUSY_CYCLES_RENDERING"/> + <value value="3" name="RB_BUSY_CYCLES_RESOLVE"/> + <value value="4" name="RB_STARVE_CYCLES_BY_SP"/> + <value value="5" name="RB_STARVE_CYCLES_BY_RAS"/> + <value value="6" name="RB_STARVE_CYCLES_BY_MARB"/> + <value value="7" name="RB_STALL_CYCLES_BY_MARB"/> + <value value="8" name="RB_STALL_CYCLES_BY_HLSQ"/> + <value value="9" name="RB_RB_RB_MARB_DATA"/> + <value value="10" name="RB_SP_RB_QUAD"/> + <value value="11" name="RB_RAS_RB_Z_QUADS"/> + <value value="12" name="RB_GMEM_CH0_READ"/> + <value value="13" name="RB_GMEM_CH1_READ"/> + <value value="14" name="RB_GMEM_CH0_WRITE"/> + <value value="15" name="RB_GMEM_CH1_WRITE"/> + <value value="16" name="RB_CP_CONTEXT_DONE"/> + <value value="17" name="RB_CP_CACHE_FLUSH"/> + <value value="18" name="RB_CP_ZPASS_DONE"/> + <value value="19" name="RB_STALL_FIFO0_FULL"/> + <value value="20" name="RB_STALL_FIFO1_FULL"/> + <value value="21" name="RB_STALL_FIFO2_FULL"/> + <value value="22" name="RB_STALL_FIFO3_FULL"/> + <value value="23" name="RB_RB_HLSQ_TRANSACTIONS"/> + <value value="24" name="RB_Z_READ"/> + <value value="25" name="RB_Z_WRITE"/> + <value value="26" name="RB_C_READ"/> + <value value="27" name="RB_C_WRITE"/> + <value value="28" name="RB_C_READ_LATENCY"/> + <value value="29" name="RB_Z_READ_LATENCY"/> + <value value="30" name="RB_STALL_BY_UCHE"/> + <value value="31" name="RB_MARB_UCHE_TRANSACTIONS"/> + <value value="32" name="RB_CACHE_STALL_MISS"/> + <value value="33" name="RB_CACHE_STALL_FIFO_FULL"/> + <value value="34" name="RB_8BIT_BLENDER_UNITS_ACTIVE"/> + <value value="35" name="RB_16BIT_BLENDER_UNITS_ACTIVE"/> + <value value="36" name="RB_SAMPLER_UNITS_ACTIVE"/> + <value value="38" name="RB_TOTAL_PASS"/> + <value value="39" name="RB_Z_PASS"/> + <value value="40" name="RB_Z_FAIL"/> + <value value="41" name="RB_S_FAIL"/> + <value value="42" name="RB_POWER0"/> + <value value="43" name="RB_POWER1"/> + <value value="44" name="RB_POWER2"/> + <value value="45" name="RB_POWER3"/> + <value value="46" name="RB_POWER4"/> + <value value="47" name="RB_POWER5"/> + <value value="48" name="RB_POWER6"/> + <value value="49" name="RB_POWER7"/> +</enum> + +<enum name="a4xx_rbbm_perfcounter_select"> + <value value="0" name="RBBM_ALWAYS_ON"/> + <value value="1" name="RBBM_VBIF_BUSY"/> + <value value="2" name="RBBM_TSE_BUSY"/> + <value value="3" name="RBBM_RAS_BUSY"/> + <value value="4" name="RBBM_PC_DCALL_BUSY"/> + <value value="5" name="RBBM_PC_VSD_BUSY"/> + <value value="6" name="RBBM_VFD_BUSY"/> + <value value="7" name="RBBM_VPC_BUSY"/> + <value value="8" name="RBBM_UCHE_BUSY"/> + <value value="9" name="RBBM_VSC_BUSY"/> + <value value="10" name="RBBM_HLSQ_BUSY"/> + <value value="11" name="RBBM_ANY_RB_BUSY"/> + <value value="12" name="RBBM_ANY_TPL1_BUSY"/> + <value value="13" name="RBBM_ANY_SP_BUSY"/> + <value value="14" name="RBBM_ANY_MARB_BUSY"/> + <value value="15" name="RBBM_ANY_ARB_BUSY"/> + <value value="16" name="RBBM_AHB_STATUS_BUSY"/> + <value value="17" name="RBBM_AHB_STATUS_STALLED"/> + <value value="18" name="RBBM_AHB_STATUS_TXFR"/> + <value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/> + <value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/> + <value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/> + <value value="22" name="RBBM_STATUS_MASKED"/> + <value value="23" name="RBBM_CP_BUSY_GFX_CORE_IDLE"/> + <value value="24" name="RBBM_TESS_BUSY"/> + <value value="25" name="RBBM_COM_BUSY"/> + <value value="32" name="RBBM_DCOM_BUSY"/> + <value value="33" name="RBBM_ANY_CCU_BUSY"/> + <value value="34" name="RBBM_DPM_BUSY"/> +</enum> + +<enum name="a4xx_sp_perfcounter_select"> + <value value="0" name="SP_LM_LOAD_INSTRUCTIONS"/> + <value value="1" name="SP_LM_STORE_INSTRUCTIONS"/> + <value value="2" name="SP_LM_ATOMICS"/> + <value value="3" name="SP_GM_LOAD_INSTRUCTIONS"/> + <value value="4" name="SP_GM_STORE_INSTRUCTIONS"/> + <value value="5" name="SP_GM_ATOMICS"/> + <value value="6" name="SP_VS_STAGE_TEX_INSTRUCTIONS"/> + <value value="7" name="SP_VS_STAGE_CFLOW_INSTRUCTIONS"/> + <value value="8" name="SP_VS_STAGE_EFU_INSTRUCTIONS"/> + <value value="9" name="SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> + <value value="10" name="SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> + <value value="11" name="SP_FS_STAGE_TEX_INSTRUCTIONS"/> + <value value="12" name="SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> + <value value="13" name="SP_FS_STAGE_EFU_INSTRUCTIONS"/> + <value value="14" name="SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> + <value value="15" name="SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> + <value value="17" name="SP_VS_INSTRUCTIONS"/> + <value value="18" name="SP_FS_INSTRUCTIONS"/> + <value value="19" name="SP_ADDR_LOCK_COUNT"/> + <value value="20" name="SP_UCHE_READ_TRANS"/> + <value value="21" name="SP_UCHE_WRITE_TRANS"/> + <value value="22" name="SP_EXPORT_VPC_TRANS"/> + <value value="23" name="SP_EXPORT_RB_TRANS"/> + <value value="24" name="SP_PIXELS_KILLED"/> + <value value="25" name="SP_ICL1_REQUESTS"/> + <value value="26" name="SP_ICL1_MISSES"/> + <value value="27" name="SP_ICL0_REQUESTS"/> + <value value="28" name="SP_ICL0_MISSES"/> + <value value="29" name="SP_ALU_WORKING_CYCLES"/> + <value value="30" name="SP_EFU_WORKING_CYCLES"/> + <value value="31" name="SP_STALL_CYCLES_BY_VPC"/> + <value value="32" name="SP_STALL_CYCLES_BY_TP"/> + <value value="33" name="SP_STALL_CYCLES_BY_UCHE"/> + <value value="34" name="SP_STALL_CYCLES_BY_RB"/> + <value value="35" name="SP_BUSY_CYCLES"/> + <value value="36" name="SP_HS_INSTRUCTIONS"/> + <value value="37" name="SP_DS_INSTRUCTIONS"/> + <value value="38" name="SP_GS_INSTRUCTIONS"/> + <value value="39" name="SP_CS_INSTRUCTIONS"/> + <value value="40" name="SP_SCHEDULER_NON_WORKING"/> + <value value="41" name="SP_WAVE_CONTEXTS"/> + <value value="42" name="SP_WAVE_CONTEXT_CYCLES"/> + <value value="43" name="SP_POWER0"/> + <value value="44" name="SP_POWER1"/> + <value value="45" name="SP_POWER2"/> + <value value="46" name="SP_POWER3"/> + <value value="47" name="SP_POWER4"/> + <value value="48" name="SP_POWER5"/> + <value value="49" name="SP_POWER6"/> + <value value="50" name="SP_POWER7"/> + <value value="51" name="SP_POWER8"/> + <value value="52" name="SP_POWER9"/> + <value value="53" name="SP_POWER10"/> + <value value="54" name="SP_POWER11"/> + <value value="55" name="SP_POWER12"/> + <value value="56" name="SP_POWER13"/> + <value value="57" name="SP_POWER14"/> + <value value="58" name="SP_POWER15"/> +</enum> + +<enum name="a4xx_tp_perfcounter_select"> + <value value="0" name="TP_L1_REQUESTS"/> + <value value="1" name="TP_L1_MISSES"/> + <value value="8" name="TP_QUADS_OFFSET"/> + <value value="9" name="TP_QUAD_SHADOW"/> + <value value="10" name="TP_QUADS_ARRAY"/> + <value value="11" name="TP_QUADS_GRADIENT"/> + <value value="12" name="TP_QUADS_1D2D"/> + <value value="13" name="TP_QUADS_3DCUBE"/> + <value value="16" name="TP_BUSY_CYCLES"/> + <value value="17" name="TP_STALL_CYCLES_BY_ARB"/> + <value value="20" name="TP_STATE_CACHE_REQUESTS"/> + <value value="21" name="TP_STATE_CACHE_MISSES"/> + <value value="22" name="TP_POWER0"/> + <value value="23" name="TP_POWER1"/> + <value value="24" name="TP_POWER2"/> + <value value="25" name="TP_POWER3"/> + <value value="26" name="TP_POWER4"/> + <value value="27" name="TP_POWER5"/> + <value value="28" name="TP_POWER6"/> + <value value="29" name="TP_POWER7"/> +</enum> + +<enum name="a4xx_uche_perfcounter_select"> + <value value="0" name="UCHE_VBIF_READ_BEATS_TP"/> + <value value="1" name="UCHE_VBIF_READ_BEATS_VFD"/> + <value value="2" name="UCHE_VBIF_READ_BEATS_HLSQ"/> + <value value="3" name="UCHE_VBIF_READ_BEATS_MARB"/> + <value value="4" name="UCHE_VBIF_READ_BEATS_SP"/> + <value value="5" name="UCHE_READ_REQUESTS_TP"/> + <value value="6" name="UCHE_READ_REQUESTS_VFD"/> + <value value="7" name="UCHE_READ_REQUESTS_HLSQ"/> + <value value="8" name="UCHE_READ_REQUESTS_MARB"/> + <value value="9" name="UCHE_READ_REQUESTS_SP"/> + <value value="10" name="UCHE_WRITE_REQUESTS_MARB"/> + <value value="11" name="UCHE_WRITE_REQUESTS_SP"/> + <value value="12" name="UCHE_TAG_CHECK_FAILS"/> + <value value="13" name="UCHE_EVICTS"/> + <value value="14" name="UCHE_FLUSHES"/> + <value value="15" name="UCHE_VBIF_LATENCY_CYCLES"/> + <value value="16" name="UCHE_VBIF_LATENCY_SAMPLES"/> + <value value="17" name="UCHE_BUSY_CYCLES"/> + <value value="18" name="UCHE_VBIF_READ_BEATS_PC"/> + <value value="19" name="UCHE_READ_REQUESTS_PC"/> + <value value="20" name="UCHE_WRITE_REQUESTS_VPC"/> + <value value="21" name="UCHE_STALL_BY_VBIF"/> + <value value="22" name="UCHE_WRITE_REQUESTS_VSC"/> + <value value="23" name="UCHE_POWER0"/> + <value value="24" name="UCHE_POWER1"/> + <value value="25" name="UCHE_POWER2"/> + <value value="26" name="UCHE_POWER3"/> + <value value="27" name="UCHE_POWER4"/> + <value value="28" name="UCHE_POWER5"/> + <value value="29" name="UCHE_POWER6"/> + <value value="30" name="UCHE_POWER7"/> +</enum> + +<enum name="a4xx_vbif_perfcounter_select"> + <value value="0" name="AXI_READ_REQUESTS_ID_0"/> + <value value="1" name="AXI_READ_REQUESTS_ID_1"/> + <value value="2" name="AXI_READ_REQUESTS_ID_2"/> + <value value="3" name="AXI_READ_REQUESTS_ID_3"/> + <value value="4" name="AXI_READ_REQUESTS_ID_4"/> + <value value="5" name="AXI_READ_REQUESTS_ID_5"/> + <value value="6" name="AXI_READ_REQUESTS_ID_6"/> + <value value="7" name="AXI_READ_REQUESTS_ID_7"/> + <value value="8" name="AXI_READ_REQUESTS_ID_8"/> + <value value="9" name="AXI_READ_REQUESTS_ID_9"/> + <value value="10" name="AXI_READ_REQUESTS_ID_10"/> + <value value="11" name="AXI_READ_REQUESTS_ID_11"/> + <value value="12" name="AXI_READ_REQUESTS_ID_12"/> + <value value="13" name="AXI_READ_REQUESTS_ID_13"/> + <value value="14" name="AXI_READ_REQUESTS_ID_14"/> + <value value="15" name="AXI_READ_REQUESTS_ID_15"/> + <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/> + <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/> + <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/> + <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/> + <value value="20" name="AXI_READ_REQUESTS_TOTAL"/> + <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/> + <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/> + <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/> + <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/> + <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/> + <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/> + <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/> + <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/> + <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/> + <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/> + <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/> + <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/> + <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/> + <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/> + <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/> + <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/> + <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/> + <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/> + <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/> + <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/> + <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/> + <value value="42" name="AXI_TOTAL_REQUESTS"/> + <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/> + <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/> + <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/> + <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/> + <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/> + <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/> + <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/> + <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/> + <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/> + <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/> + <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/> + <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/> + <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/> + <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/> + <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/> + <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/> + <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/> + <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/> + <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/> + <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/> + <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/> + <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/> + <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/> + <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/> + <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/> + <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/> + <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/> + <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/> + <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/> + <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/> + <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/> + <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/> + <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/> + <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/> + <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/> + <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/> + <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/> + <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/> + <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/> + <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/> + <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/> + <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/> + <value value="85" name="AXI_DATA_BEATS_TOTAL"/> + <value value="86" name="CYCLES_HELD_OFF_ID_0"/> + <value value="87" name="CYCLES_HELD_OFF_ID_1"/> + <value value="88" name="CYCLES_HELD_OFF_ID_2"/> + <value value="89" name="CYCLES_HELD_OFF_ID_3"/> + <value value="90" name="CYCLES_HELD_OFF_ID_4"/> + <value value="91" name="CYCLES_HELD_OFF_ID_5"/> + <value value="92" name="CYCLES_HELD_OFF_ID_6"/> + <value value="93" name="CYCLES_HELD_OFF_ID_7"/> + <value value="94" name="CYCLES_HELD_OFF_ID_8"/> + <value value="95" name="CYCLES_HELD_OFF_ID_9"/> + <value value="96" name="CYCLES_HELD_OFF_ID_10"/> + <value value="97" name="CYCLES_HELD_OFF_ID_11"/> + <value value="98" name="CYCLES_HELD_OFF_ID_12"/> + <value value="99" name="CYCLES_HELD_OFF_ID_13"/> + <value value="100" name="CYCLES_HELD_OFF_ID_14"/> + <value value="101" name="CYCLES_HELD_OFF_ID_15"/> + <value value="102" name="AXI_READ_REQUEST_HELD_OFF"/> + <value value="103" name="AXI_WRITE_REQUEST_HELD_OFF"/> + <value value="104" name="AXI_REQUEST_HELD_OFF"/> + <value value="105" name="AXI_WRITE_DATA_HELD_OFF"/> + <value value="106" name="OCMEM_AXI_READ_REQUEST_HELD_OFF"/> + <value value="107" name="OCMEM_AXI_WRITE_REQUEST_HELD_OFF"/> + <value value="108" name="OCMEM_AXI_REQUEST_HELD_OFF"/> + <value value="109" name="OCMEM_AXI_WRITE_DATA_HELD_OFF"/> + <value value="110" name="ELAPSED_CYCLES_DDR"/> + <value value="111" name="ELAPSED_CYCLES_OCMEM"/> +</enum> + +<enum name="a4xx_vfd_perfcounter_select"> + <value value="0" name="VFD_UCHE_BYTE_FETCHED"/> + <value value="1" name="VFD_UCHE_TRANS"/> + <value value="3" name="VFD_FETCH_INSTRUCTIONS"/> + <value value="5" name="VFD_BUSY_CYCLES"/> + <value value="6" name="VFD_STALL_CYCLES_UCHE"/> + <value value="7" name="VFD_STALL_CYCLES_HLSQ"/> + <value value="8" name="VFD_STALL_CYCLES_VPC_BYPASS"/> + <value value="9" name="VFD_STALL_CYCLES_VPC_ALLOC"/> + <value value="13" name="VFD_MODE_0_FIBERS"/> + <value value="14" name="VFD_MODE_1_FIBERS"/> + <value value="15" name="VFD_MODE_2_FIBERS"/> + <value value="16" name="VFD_MODE_3_FIBERS"/> + <value value="17" name="VFD_MODE_4_FIBERS"/> + <value value="18" name="VFD_BFIFO_STALL"/> + <value value="19" name="VFD_NUM_VERTICES_TOTAL"/> + <value value="20" name="VFD_PACKER_FULL"/> + <value value="21" name="VFD_UCHE_REQUEST_FIFO_FULL"/> + <value value="22" name="VFD_STARVE_CYCLES_PC"/> + <value value="23" name="VFD_STARVE_CYCLES_UCHE"/> +</enum> + +<enum name="a4xx_vpc_perfcounter_select"> + <value value="2" name="VPC_SP_LM_COMPONENTS"/> + <value value="3" name="VPC_SP0_LM_BYTES"/> + <value value="4" name="VPC_SP1_LM_BYTES"/> + <value value="5" name="VPC_SP2_LM_BYTES"/> + <value value="6" name="VPC_SP3_LM_BYTES"/> + <value value="7" name="VPC_WORKING_CYCLES"/> + <value value="8" name="VPC_STALL_CYCLES_LM"/> + <value value="9" name="VPC_STARVE_CYCLES_RAS"/> + <value value="10" name="VPC_STREAMOUT_CYCLES"/> + <value value="12" name="VPC_UCHE_TRANSACTIONS"/> + <value value="13" name="VPC_STALL_CYCLES_UCHE"/> + <value value="14" name="VPC_BUSY_CYCLES"/> + <value value="15" name="VPC_STARVE_CYCLES_SP"/> +</enum> + +<enum name="a4xx_vsc_perfcounter_select"> + <value value="0" name="VSC_BUSY_CYCLES"/> + <value value="1" name="VSC_WORKING_CYCLES"/> + <value value="2" name="VSC_STALL_CYCLES_UCHE"/> + <value value="3" name="VSC_STARVE_CYCLES_RAS"/> + <value value="4" name="VSC_EOT_NUM"/> +</enum> + +<domain name="A4XX" width="32"> + <!-- RB registers --> + <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/> + <reg32 offset="0x0cc7" name="RB_PERFCTR_RB_SEL_0" type="a4xx_rb_perfcounter_select"/> + <reg32 offset="0x0cc8" name="RB_PERFCTR_RB_SEL_1" type="a4xx_rb_perfcounter_select"/> + <reg32 offset="0x0cc9" name="RB_PERFCTR_RB_SEL_2" type="a4xx_rb_perfcounter_select"/> + <reg32 offset="0x0cca" name="RB_PERFCTR_RB_SEL_3" type="a4xx_rb_perfcounter_select"/> + <reg32 offset="0x0ccb" name="RB_PERFCTR_RB_SEL_4" type="a4xx_rb_perfcounter_select"/> + <reg32 offset="0x0ccc" name="RB_PERFCTR_RB_SEL_5" type="a4xx_rb_perfcounter_select"/> + <reg32 offset="0x0ccd" name="RB_PERFCTR_RB_SEL_6" type="a4xx_rb_perfcounter_select"/> + <reg32 offset="0x0cce" name="RB_PERFCTR_RB_SEL_7" type="a4xx_rb_perfcounter_select"/> + <reg32 offset="0x0ccf" name="RB_PERFCTR_CCU_SEL_0" type="a4xx_ccu_perfcounter_select"/> + <reg32 offset="0x0cd0" name="RB_PERFCTR_CCU_SEL_1" type="a4xx_ccu_perfcounter_select"/> + <reg32 offset="0x0cd1" name="RB_PERFCTR_CCU_SEL_2" type="a4xx_ccu_perfcounter_select"/> + <reg32 offset="0x0cd2" name="RB_PERFCTR_CCU_SEL_3" type="a4xx_ccu_perfcounter_select"/> + <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION"> + <bitfield name="WIDTH" low="0" high="13" type="uint"/> + <bitfield name="HEIGHT" low="16" high="29" type="uint"/> + </reg32> + <reg32 offset="0x20cc" name="RB_CLEAR_COLOR_DW0"/> + <reg32 offset="0x20cd" name="RB_CLEAR_COLOR_DW1"/> + <reg32 offset="0x20ce" name="RB_CLEAR_COLOR_DW2"/> + <reg32 offset="0x20cf" name="RB_CLEAR_COLOR_DW3"/> + <reg32 offset="0x20a0" name="RB_MODE_CONTROL"> + <!-- + for non-bypass mode, these are bin width/height.. although + possibly bigger bitfields to hold entire width/height for + gmem-bypass?? Either way, it appears to need to be multiple + of 32.. + --> + <bitfield name="WIDTH" low="0" high="5" shr="5" type="uint"/> + <bitfield name="HEIGHT" low="8" high="13" shr="5" type="uint"/> + <bitfield name="ENABLE_GMEM" pos="16" type="boolean"/> + </reg32> + <reg32 offset="0x20a1" name="RB_RENDER_CONTROL"> + <bitfield name="BINNING_PASS" pos="0" type="boolean"/> + <!-- nearly everything has bit3 set.. --> + <!-- bit5 set on resolve and tiling pass --> + <bitfield name="DISABLE_COLOR_PIPE" pos="5" type="boolean"/> + </reg32> + <reg32 offset="0x20a2" name="RB_MSAA_CONTROL"> + <bitfield name="DISABLE" pos="12" type="boolean"/> + <bitfield name="SAMPLES" low="13" high="15" type="uint"/> + </reg32> + <reg32 offset="0x20a3" name="RB_RENDER_CONTROL2"> + <bitfield name="XCOORD" pos="0" type="boolean"/> + <bitfield name="YCOORD" pos="1" type="boolean"/> + <!-- assuming zcoord/wcoord follows.. --> + <bitfield name="ZCOORD" pos="2" type="boolean"/> + <bitfield name="WCOORD" pos="3" type="boolean"/> + <bitfield name="SAMPLEMASK" pos="4" type="boolean"/> + <bitfield name="FACENESS" pos="5" type="boolean"/> + <bitfield name="SAMPLEID" pos="6" type="boolean"/> + <bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/> + <bitfield name="SAMPLEID_HR" pos="11" type="boolean"/> + <bitfield name="VARYING" pos="12" type="boolean"/> + </reg32> + <array offset="0x20a4" name="RB_MRT" stride="5" length="8"> + <reg32 offset="0x0" name="CONTROL"> + <bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/> + <!-- both these bits seem to get set when enabling GL_BLEND.. --> + <bitfield name="BLEND" pos="4" type="boolean"/> + <bitfield name="BLEND2" pos="5" type="boolean"/> + <bitfield name="ROP_ENABLE" pos="6" type="boolean"/> + <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/> + <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/> + </reg32> + <reg32 offset="0x1" name="BUF_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="5" type="a4xx_color_fmt"/> + <!-- + guestimate position of COLOR_TILE_MODE.. this works out if + common value is 2, like on a3xx.. + --> + <bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a4xx_tile_mode"/> + <bitfield name="DITHER_MODE" low="9" high="10" type="adreno_rb_dither_mode"/> + <bitfield name="COLOR_SWAP" low="11" high="12" type="a3xx_color_swap"/> + <bitfield name="COLOR_SRGB" pos="13" type="boolean"/> + <!-- note: possibly some # of lsb's aren't there: --> + <doc> + Pitch (actually, appears to be pitch in bytes, so really is a stride) + in GMEM, so pitch of the current tile. + </doc> + <bitfield name="COLOR_BUF_PITCH" low="14" high="31" shr="4" type="uint"/> + </reg32> + <reg32 offset="0x2" name="BASE"/> + <reg32 offset="0x3" name="CONTROL3"> + <!-- probably missing some lsb's.. and guessing upper size --> + <!-- pitch * cpp * msaa: --> + <bitfield name="STRIDE" low="3" high="25" type="uint"/> + </reg32> + <reg32 offset="0x4" name="BLEND_CONTROL"> + <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/> + <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/> + <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/> + <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/> + </reg32> + </array> + + <reg32 offset="0x20f0" name="RB_BLEND_RED"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="SINT" low="8" high="15" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0x20f1" name="RB_BLEND_RED_F32" type="float"/> + + <reg32 offset="0x20f2" name="RB_BLEND_GREEN"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="SINT" low="8" high="15" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0x20f3" name="RB_BLEND_GREEN_F32" type="float"/> + + <reg32 offset="0x20f4" name="RB_BLEND_BLUE"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="SINT" low="8" high="15" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0x20f5" name="RB_BLEND_BLUE_F32" type="float"/> + + <reg32 offset="0x20f6" name="RB_BLEND_ALPHA"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="SINT" low="8" high="15" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0x20f7" name="RB_BLEND_ALPHA_F32" type="float"/> + + <reg32 offset="0x20f8" name="RB_ALPHA_CONTROL"> + <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> + <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> + <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> + </reg32> + <reg32 offset="0x20f9" name="RB_FS_OUTPUT"> + <!-- per-mrt enable bit --> + <bitfield name="ENABLE_BLEND" low="0" high="7"/> + <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> + <!-- a guess? --> + <bitfield name="SAMPLE_MASK" low="16" high="31"/> + </reg32> + <reg32 offset="0x20fa" name="RB_SAMPLE_COUNT_CONTROL"> + <bitfield name="COPY" pos="1" type="boolean"/> + <bitfield name="ADDR" low="2" high="31" shr="2"/> + </reg32> + <!-- always 00000000 for binning pass, else 0000000f: --> + <reg32 offset="0x20fb" name="RB_RENDER_COMPONENTS"> + <bitfield name="RT0" low="0" high="3"/> + <bitfield name="RT1" low="4" high="7"/> + <bitfield name="RT2" low="8" high="11"/> + <bitfield name="RT3" low="12" high="15"/> + <bitfield name="RT4" low="16" high="19"/> + <bitfield name="RT5" low="20" high="23"/> + <bitfield name="RT6" low="24" high="27"/> + <bitfield name="RT7" low="28" high="31"/> + </reg32> + + <reg32 offset="0x20fc" name="RB_COPY_CONTROL"> + <!-- not sure # of bits --> + <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/> + <bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/> + <bitfield name="FASTCLEAR" low="8" high="11" type="hex"/> + <bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/> + </reg32> + <reg32 offset="0x20fd" name="RB_COPY_DEST_BASE"> + <bitfield name="BASE" low="5" high="31" shr="5" type="hex"/> + </reg32> + <reg32 offset="0x20fe" name="RB_COPY_DEST_PITCH"> + <doc>actually, appears to be pitch in bytes, so really is a stride</doc> + <!-- not actually sure about max pitch... --> + <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/> + </reg32> + <reg32 offset="0x20ff" name="RB_COPY_DEST_INFO"> + <bitfield name="FORMAT" low="2" high="7" type="a4xx_color_fmt"/> + <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/> + <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/> + <bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/> + <bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/> + <bitfield name="TILE" low="24" high="25" type="a4xx_tile_mode"/> + </reg32> + <reg32 offset="0x2100" name="RB_FS_OUTPUT_REG"> + <!-- bit0 set except for binning pass.. --> + <bitfield name="MRT" low="0" high="3" type="uint"/> + <bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/> + </reg32> + <reg32 offset="0x2101" name="RB_DEPTH_CONTROL"> + <!-- + guessing that this matches a2xx with the stencil fields + moved out into RB_STENCIL_CONTROL? + --> + <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/> + <bitfield name="Z_ENABLE" pos="1" type="boolean"/> + <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/> + <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/> + <bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/> + <bitfield name="EARLY_Z_DISABLE" pos="16" type="boolean"/> + <bitfield name="FORCE_FRAGZ_TO_FS" pos="17" type="boolean"/> + <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc> + <bitfield name="Z_TEST_ENABLE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x2102" name="RB_DEPTH_CLEAR"/> + <reg32 offset="0x2103" name="RB_DEPTH_INFO"> + <bitfield name="DEPTH_FORMAT" low="0" high="1" type="a4xx_depth_format"/> + <doc> + DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie + bin_w * bin_h / 1024 (possible rounded up to multiple of + something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes + 80.. so maybe it needs to be multiple of 8?? + </doc> + <bitfield name="DEPTH_BASE" low="12" high="31" shr="12" type="hex"/> + </reg32> + <reg32 offset="0x2104" name="RB_DEPTH_PITCH" shr="5" type="uint"> + <doc>stride of depth/stencil buffer</doc> + </reg32> + <reg32 offset="0x2105" name="RB_DEPTH_PITCH2" shr="5" type="uint"> + <doc>???</doc> + </reg32> + <reg32 offset="0x2106" name="RB_STENCIL_CONTROL"> + <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> + <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> + <!-- + set for stencil operations that require read from stencil + buffer, but not for example for stencil clear (which does + not require read).. so guessing this is analogous to + READ_DEST_ENABLE for color buffer.. + --> + <bitfield name="STENCIL_READ" pos="2" type="boolean"/> + <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/> + <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/> + <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/> + <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/> + <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/> + <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/> + <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> + <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> + </reg32> + <reg32 offset="0x2107" name="RB_STENCIL_CONTROL2"> + <!-- + This seems to be set by blob if there is a stencil buffer + at all in GMEM, regardless of whether it is enabled for + a particular draw (ie. RB_STENCIL_CONTROL). Not really + sure if that is required or just a quirk of the blob + --> + <bitfield name="STENCIL_BUFFER" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x2108" name="RB_STENCIL_INFO"> + <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> + <doc>Base address for stencil when not using interleaved depth/stencil</doc> + <bitfield name="STENCIL_BASE" low="12" high="31" shr="12" type="hex"/> + </reg32> + <reg32 offset="0x2109" name="RB_STENCIL_PITCH" shr="5" type="uint"> + <doc>pitch of stencil buffer when not using interleaved depth/stencil</doc> + </reg32> + + <reg32 offset="0x210b" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/> + <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/> + <reg32 offset="0x210d" name="RB_BIN_OFFSET" type="adreno_reg_xy"/> + <array offset="0x2120" name="RB_VPORT_Z_CLAMP" stride="2" length="16"> + <reg32 offset="0x0" name="MIN"/> + <reg32 offset="0x1" name="MAX"/> + </array> + + <!-- RBBM registers --> + <reg32 offset="0x0000" name="RBBM_HW_VERSION"/> + <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/> + <array offset="0x4" name="RBBM_CLOCK_CTL_TP" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x8" name="RBBM_CLOCK_CTL2_TP" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0xc" name="RBBM_CLOCK_HYST_TP" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x10" name="RBBM_CLOCK_DELAY_TP" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <reg32 offset="0x0014" name="RBBM_CLOCK_CTL_UCHE "/> + <reg32 offset="0x0015" name="RBBM_CLOCK_CTL2_UCHE"/> + <reg32 offset="0x0016" name="RBBM_CLOCK_CTL3_UCHE"/> + <reg32 offset="0x0017" name="RBBM_CLOCK_CTL4_UCHE"/> + <reg32 offset="0x0018" name="RBBM_CLOCK_HYST_UCHE"/> + <reg32 offset="0x0019" name="RBBM_CLOCK_DELAY_UCHE"/> + <reg32 offset="0x001a" name="RBBM_CLOCK_MODE_GPC"/> + <reg32 offset="0x001b" name="RBBM_CLOCK_DELAY_GPC"/> + <reg32 offset="0x001c" name="RBBM_CLOCK_HYST_GPC"/> + <reg32 offset="0x001d" name="RBBM_CLOCK_CTL_TSE_RAS_RBBM"/> + <reg32 offset="0x001e" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/> + <reg32 offset="0x001f" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/> + <reg32 offset="0x0020" name="RBBM_CLOCK_CTL"/> + <reg32 offset="0x0021" name="RBBM_SP_HYST_CNT"/> + <reg32 offset="0x0022" name="RBBM_SW_RESET_CMD"/> + <reg32 offset="0x0023" name="RBBM_AHB_CTL0"/> + <reg32 offset="0x0024" name="RBBM_AHB_CTL1"/> + <reg32 offset="0x0025" name="RBBM_AHB_CMD"/> + <reg32 offset="0x0026" name="RBBM_RB_SUB_BLOCK_SEL_CTL"/> + <reg32 offset="0x0028" name="RBBM_RAM_ACC_63_32"/> + <reg32 offset="0x002b" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/> + <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CTL"/> + <reg32 offset="0x0034" name="RBBM_INTERFACE_HANG_MASK_CTL4"/> + <reg32 offset="0x0036" name="RBBM_INT_CLEAR_CMD"/> + <reg32 offset="0x0037" name="RBBM_INT_0_MASK"/> + <reg32 offset="0x003e" name="RBBM_RBBM_CTL"/> + <reg32 offset="0x003f" name="RBBM_AHB_DEBUG_CTL"/> + <reg32 offset="0x0041" name="RBBM_VBIF_DEBUG_CTL"/> + <reg32 offset="0x0042" name="RBBM_CLOCK_CTL2"/> + <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/> + <reg32 offset="0x0047" name="RBBM_RESET_CYCLES"/> + <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CTL"/> + <reg32 offset="0x004a" name="RBBM_CFG_DEBBUS_SEL_A"/> + <reg32 offset="0x004b" name="RBBM_CFG_DEBBUS_SEL_B"/> + <reg32 offset="0x004c" name="RBBM_CFG_DEBBUS_SEL_C"/> + <reg32 offset="0x004d" name="RBBM_CFG_DEBBUS_SEL_D"/> + <reg32 offset="0x0098" name="RBBM_POWER_CNTL_IP"> + <bitfield name="SW_COLLAPSE" pos="0" type="boolean"/> + <bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/> + </reg32> + <reg32 offset="0x009c" name="RBBM_PERFCTR_CP_0_LO"/> + <reg32 offset="0x009d" name="RBBM_PERFCTR_CP_0_HI"/> + <reg32 offset="0x009e" name="RBBM_PERFCTR_CP_1_LO"/> + <reg32 offset="0x009f" name="RBBM_PERFCTR_CP_1_HI"/> + <reg32 offset="0x00a0" name="RBBM_PERFCTR_CP_2_LO"/> + <reg32 offset="0x00a1" name="RBBM_PERFCTR_CP_2_HI"/> + <reg32 offset="0x00a2" name="RBBM_PERFCTR_CP_3_LO"/> + <reg32 offset="0x00a3" name="RBBM_PERFCTR_CP_3_HI"/> + <reg32 offset="0x00a4" name="RBBM_PERFCTR_CP_4_LO"/> + <reg32 offset="0x00a5" name="RBBM_PERFCTR_CP_4_HI"/> + <reg32 offset="0x00a6" name="RBBM_PERFCTR_CP_5_LO"/> + <reg32 offset="0x00a7" name="RBBM_PERFCTR_CP_5_HI"/> + <reg32 offset="0x00a8" name="RBBM_PERFCTR_CP_6_LO"/> + <reg32 offset="0x00a9" name="RBBM_PERFCTR_CP_6_HI"/> + <reg32 offset="0x00aa" name="RBBM_PERFCTR_CP_7_LO"/> + <reg32 offset="0x00ab" name="RBBM_PERFCTR_CP_7_HI"/> + <reg32 offset="0x00ac" name="RBBM_PERFCTR_RBBM_0_LO"/> + <reg32 offset="0x00ad" name="RBBM_PERFCTR_RBBM_0_HI"/> + <reg32 offset="0x00ae" name="RBBM_PERFCTR_RBBM_1_LO"/> + <reg32 offset="0x00af" name="RBBM_PERFCTR_RBBM_1_HI"/> + <reg32 offset="0x00b0" name="RBBM_PERFCTR_RBBM_2_LO"/> + <reg32 offset="0x00b1" name="RBBM_PERFCTR_RBBM_2_HI"/> + <reg32 offset="0x00b2" name="RBBM_PERFCTR_RBBM_3_LO"/> + <reg32 offset="0x00b3" name="RBBM_PERFCTR_RBBM_3_HI"/> + <reg32 offset="0x00b4" name="RBBM_PERFCTR_PC_0_LO"/> + <reg32 offset="0x00b5" name="RBBM_PERFCTR_PC_0_HI"/> + <reg32 offset="0x00b6" name="RBBM_PERFCTR_PC_1_LO"/> + <reg32 offset="0x00b7" name="RBBM_PERFCTR_PC_1_HI"/> + <reg32 offset="0x00b8" name="RBBM_PERFCTR_PC_2_LO"/> + <reg32 offset="0x00b9" name="RBBM_PERFCTR_PC_2_HI"/> + <reg32 offset="0x00ba" name="RBBM_PERFCTR_PC_3_LO"/> + <reg32 offset="0x00bb" name="RBBM_PERFCTR_PC_3_HI"/> + <reg32 offset="0x00bc" name="RBBM_PERFCTR_PC_4_LO"/> + <reg32 offset="0x00bd" name="RBBM_PERFCTR_PC_4_HI"/> + <reg32 offset="0x00be" name="RBBM_PERFCTR_PC_5_LO"/> + <reg32 offset="0x00bf" name="RBBM_PERFCTR_PC_5_HI"/> + <reg32 offset="0x00c0" name="RBBM_PERFCTR_PC_6_LO"/> + <reg32 offset="0x00c1" name="RBBM_PERFCTR_PC_6_HI"/> + <reg32 offset="0x00c2" name="RBBM_PERFCTR_PC_7_LO"/> + <reg32 offset="0x00c3" name="RBBM_PERFCTR_PC_7_HI"/> + <reg32 offset="0x00c4" name="RBBM_PERFCTR_VFD_0_LO"/> + <reg32 offset="0x00c5" name="RBBM_PERFCTR_VFD_0_HI"/> + <reg32 offset="0x00c6" name="RBBM_PERFCTR_VFD_1_LO"/> + <reg32 offset="0x00c7" name="RBBM_PERFCTR_VFD_1_HI"/> + <reg32 offset="0x00c8" name="RBBM_PERFCTR_VFD_2_LO"/> + <reg32 offset="0x00c9" name="RBBM_PERFCTR_VFD_2_HI"/> + <reg32 offset="0x00ca" name="RBBM_PERFCTR_VFD_3_LO"/> + <reg32 offset="0x00cb" name="RBBM_PERFCTR_VFD_3_HI"/> + <reg32 offset="0x00cc" name="RBBM_PERFCTR_VFD_4_LO"/> + <reg32 offset="0x00cd" name="RBBM_PERFCTR_VFD_4_HI"/> + <reg32 offset="0x00ce" name="RBBM_PERFCTR_VFD_5_LO"/> + <reg32 offset="0x00cf" name="RBBM_PERFCTR_VFD_5_HI"/> + <reg32 offset="0x00d0" name="RBBM_PERFCTR_VFD_6_LO"/> + <reg32 offset="0x00d1" name="RBBM_PERFCTR_VFD_6_HI"/> + <reg32 offset="0x00d2" name="RBBM_PERFCTR_VFD_7_LO"/> + <reg32 offset="0x00d3" name="RBBM_PERFCTR_VFD_7_HI"/> + <reg32 offset="0x00d4" name="RBBM_PERFCTR_HLSQ_0_LO"/> + <reg32 offset="0x00d5" name="RBBM_PERFCTR_HLSQ_0_HI"/> + <reg32 offset="0x00d6" name="RBBM_PERFCTR_HLSQ_1_LO"/> + <reg32 offset="0x00d7" name="RBBM_PERFCTR_HLSQ_1_HI"/> + <reg32 offset="0x00d8" name="RBBM_PERFCTR_HLSQ_2_LO"/> + <reg32 offset="0x00d9" name="RBBM_PERFCTR_HLSQ_2_HI"/> + <reg32 offset="0x00da" name="RBBM_PERFCTR_HLSQ_3_LO"/> + <reg32 offset="0x00db" name="RBBM_PERFCTR_HLSQ_3_HI"/> + <reg32 offset="0x00dc" name="RBBM_PERFCTR_HLSQ_4_LO"/> + <reg32 offset="0x00dd" name="RBBM_PERFCTR_HLSQ_4_HI"/> + <reg32 offset="0x00de" name="RBBM_PERFCTR_HLSQ_5_LO"/> + <reg32 offset="0x00df" name="RBBM_PERFCTR_HLSQ_5_HI"/> + <reg32 offset="0x00e0" name="RBBM_PERFCTR_HLSQ_6_LO"/> + <reg32 offset="0x00e1" name="RBBM_PERFCTR_HLSQ_6_HI"/> + <reg32 offset="0x00e2" name="RBBM_PERFCTR_HLSQ_7_LO"/> + <reg32 offset="0x00e3" name="RBBM_PERFCTR_HLSQ_7_HI"/> + <reg32 offset="0x00e4" name="RBBM_PERFCTR_VPC_0_LO"/> + <reg32 offset="0x00e5" name="RBBM_PERFCTR_VPC_0_HI"/> + <reg32 offset="0x00e6" name="RBBM_PERFCTR_VPC_1_LO"/> + <reg32 offset="0x00e7" name="RBBM_PERFCTR_VPC_1_HI"/> + <reg32 offset="0x00e8" name="RBBM_PERFCTR_VPC_2_LO"/> + <reg32 offset="0x00e9" name="RBBM_PERFCTR_VPC_2_HI"/> + <reg32 offset="0x00ea" name="RBBM_PERFCTR_VPC_3_LO"/> + <reg32 offset="0x00eb" name="RBBM_PERFCTR_VPC_3_HI"/> + <reg32 offset="0x00ec" name="RBBM_PERFCTR_CCU_0_LO"/> + <reg32 offset="0x00ed" name="RBBM_PERFCTR_CCU_0_HI"/> + <reg32 offset="0x00ee" name="RBBM_PERFCTR_CCU_1_LO"/> + <reg32 offset="0x00ef" name="RBBM_PERFCTR_CCU_1_HI"/> + <reg32 offset="0x00f0" name="RBBM_PERFCTR_CCU_2_LO"/> + <reg32 offset="0x00f1" name="RBBM_PERFCTR_CCU_2_HI"/> + <reg32 offset="0x00f2" name="RBBM_PERFCTR_CCU_3_LO"/> + <reg32 offset="0x00f3" name="RBBM_PERFCTR_CCU_3_HI"/> + <reg32 offset="0x00f4" name="RBBM_PERFCTR_TSE_0_LO"/> + <reg32 offset="0x00f5" name="RBBM_PERFCTR_TSE_0_HI"/> + <reg32 offset="0x00f6" name="RBBM_PERFCTR_TSE_1_LO"/> + <reg32 offset="0x00f7" name="RBBM_PERFCTR_TSE_1_HI"/> + <reg32 offset="0x00f8" name="RBBM_PERFCTR_TSE_2_LO"/> + <reg32 offset="0x00f9" name="RBBM_PERFCTR_TSE_2_HI"/> + <reg32 offset="0x00fa" name="RBBM_PERFCTR_TSE_3_LO"/> + <reg32 offset="0x00fb" name="RBBM_PERFCTR_TSE_3_HI"/> + <reg32 offset="0x00fc" name="RBBM_PERFCTR_RAS_0_LO"/> + <reg32 offset="0x00fd" name="RBBM_PERFCTR_RAS_0_HI"/> + <reg32 offset="0x00fe" name="RBBM_PERFCTR_RAS_1_LO"/> + <reg32 offset="0x00ff" name="RBBM_PERFCTR_RAS_1_HI"/> + <reg32 offset="0x0100" name="RBBM_PERFCTR_RAS_2_LO"/> + <reg32 offset="0x0101" name="RBBM_PERFCTR_RAS_2_HI"/> + <reg32 offset="0x0102" name="RBBM_PERFCTR_RAS_3_LO"/> + <reg32 offset="0x0103" name="RBBM_PERFCTR_RAS_3_HI"/> + <reg32 offset="0x0104" name="RBBM_PERFCTR_UCHE_0_LO"/> + <reg32 offset="0x0105" name="RBBM_PERFCTR_UCHE_0_HI"/> + <reg32 offset="0x0106" name="RBBM_PERFCTR_UCHE_1_LO"/> + <reg32 offset="0x0107" name="RBBM_PERFCTR_UCHE_1_HI"/> + <reg32 offset="0x0108" name="RBBM_PERFCTR_UCHE_2_LO"/> + <reg32 offset="0x0109" name="RBBM_PERFCTR_UCHE_2_HI"/> + <reg32 offset="0x010a" name="RBBM_PERFCTR_UCHE_3_LO"/> + <reg32 offset="0x010b" name="RBBM_PERFCTR_UCHE_3_HI"/> + <reg32 offset="0x010c" name="RBBM_PERFCTR_UCHE_4_LO"/> + <reg32 offset="0x010d" name="RBBM_PERFCTR_UCHE_4_HI"/> + <reg32 offset="0x010e" name="RBBM_PERFCTR_UCHE_5_LO"/> + <reg32 offset="0x010f" name="RBBM_PERFCTR_UCHE_5_HI"/> + <reg32 offset="0x0110" name="RBBM_PERFCTR_UCHE_6_LO"/> + <reg32 offset="0x0111" name="RBBM_PERFCTR_UCHE_6_HI"/> + <reg32 offset="0x0112" name="RBBM_PERFCTR_UCHE_7_LO"/> + <reg32 offset="0x0113" name="RBBM_PERFCTR_UCHE_7_HI"/> + <reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/> + <reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/> + <reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/> + <reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/> + <reg32 offset="0x0116" name="RBBM_PERFCTR_TP_1_LO"/> + <reg32 offset="0x0117" name="RBBM_PERFCTR_TP_1_HI"/> + <reg32 offset="0x0118" name="RBBM_PERFCTR_TP_2_LO"/> + <reg32 offset="0x0119" name="RBBM_PERFCTR_TP_2_HI"/> + <reg32 offset="0x011a" name="RBBM_PERFCTR_TP_3_LO"/> + <reg32 offset="0x011b" name="RBBM_PERFCTR_TP_3_HI"/> + <reg32 offset="0x011c" name="RBBM_PERFCTR_TP_4_LO"/> + <reg32 offset="0x011d" name="RBBM_PERFCTR_TP_4_HI"/> + <reg32 offset="0x011e" name="RBBM_PERFCTR_TP_5_LO"/> + <reg32 offset="0x011f" name="RBBM_PERFCTR_TP_5_HI"/> + <reg32 offset="0x0120" name="RBBM_PERFCTR_TP_6_LO"/> + <reg32 offset="0x0121" name="RBBM_PERFCTR_TP_6_HI"/> + <reg32 offset="0x0122" name="RBBM_PERFCTR_TP_7_LO"/> + <reg32 offset="0x0123" name="RBBM_PERFCTR_TP_7_HI"/> + <reg32 offset="0x0124" name="RBBM_PERFCTR_SP_0_LO"/> + <reg32 offset="0x0125" name="RBBM_PERFCTR_SP_0_HI"/> + <reg32 offset="0x0126" name="RBBM_PERFCTR_SP_1_LO"/> + <reg32 offset="0x0127" name="RBBM_PERFCTR_SP_1_HI"/> + <reg32 offset="0x0128" name="RBBM_PERFCTR_SP_2_LO"/> + <reg32 offset="0x0129" name="RBBM_PERFCTR_SP_2_HI"/> + <reg32 offset="0x012a" name="RBBM_PERFCTR_SP_3_LO"/> + <reg32 offset="0x012b" name="RBBM_PERFCTR_SP_3_HI"/> + <reg32 offset="0x012c" name="RBBM_PERFCTR_SP_4_LO"/> + <reg32 offset="0x012d" name="RBBM_PERFCTR_SP_4_HI"/> + <reg32 offset="0x012e" name="RBBM_PERFCTR_SP_5_LO"/> + <reg32 offset="0x012f" name="RBBM_PERFCTR_SP_5_HI"/> + <reg32 offset="0x0130" name="RBBM_PERFCTR_SP_6_LO"/> + <reg32 offset="0x0131" name="RBBM_PERFCTR_SP_6_HI"/> + <reg32 offset="0x0132" name="RBBM_PERFCTR_SP_7_LO"/> + <reg32 offset="0x0133" name="RBBM_PERFCTR_SP_7_HI"/> + <reg32 offset="0x0134" name="RBBM_PERFCTR_SP_8_LO"/> + <reg32 offset="0x0135" name="RBBM_PERFCTR_SP_8_HI"/> + <reg32 offset="0x0136" name="RBBM_PERFCTR_SP_9_LO"/> + <reg32 offset="0x0137" name="RBBM_PERFCTR_SP_9_HI"/> + <reg32 offset="0x0138" name="RBBM_PERFCTR_SP_10_LO"/> + <reg32 offset="0x0139" name="RBBM_PERFCTR_SP_10_HI"/> + <reg32 offset="0x013a" name="RBBM_PERFCTR_SP_11_LO"/> + <reg32 offset="0x013b" name="RBBM_PERFCTR_SP_11_HI"/> + <reg32 offset="0x013c" name="RBBM_PERFCTR_RB_0_LO"/> + <reg32 offset="0x013d" name="RBBM_PERFCTR_RB_0_HI"/> + <reg32 offset="0x013e" name="RBBM_PERFCTR_RB_1_LO"/> + <reg32 offset="0x013f" name="RBBM_PERFCTR_RB_1_HI"/> + <reg32 offset="0x0140" name="RBBM_PERFCTR_RB_2_LO"/> + <reg32 offset="0x0141" name="RBBM_PERFCTR_RB_2_HI"/> + <reg32 offset="0x0142" name="RBBM_PERFCTR_RB_3_LO"/> + <reg32 offset="0x0143" name="RBBM_PERFCTR_RB_3_HI"/> + <reg32 offset="0x0144" name="RBBM_PERFCTR_RB_4_LO"/> + <reg32 offset="0x0145" name="RBBM_PERFCTR_RB_4_HI"/> + <reg32 offset="0x0146" name="RBBM_PERFCTR_RB_5_LO"/> + <reg32 offset="0x0147" name="RBBM_PERFCTR_RB_5_HI"/> + <reg32 offset="0x0148" name="RBBM_PERFCTR_RB_6_LO"/> + <reg32 offset="0x0149" name="RBBM_PERFCTR_RB_6_HI"/> + <reg32 offset="0x014a" name="RBBM_PERFCTR_RB_7_LO"/> + <reg32 offset="0x014b" name="RBBM_PERFCTR_RB_7_HI"/> + <reg32 offset="0x014c" name="RBBM_PERFCTR_VSC_0_LO"/> + <reg32 offset="0x014d" name="RBBM_PERFCTR_VSC_0_HI"/> + <reg32 offset="0x014e" name="RBBM_PERFCTR_VSC_1_LO"/> + <reg32 offset="0x014f" name="RBBM_PERFCTR_VSC_1_HI"/> + <reg32 offset="0x0166" name="RBBM_PERFCTR_PWR_0_LO"/> + <reg32 offset="0x0167" name="RBBM_PERFCTR_PWR_0_HI"/> + <reg32 offset="0x0168" name="RBBM_PERFCTR_PWR_1_LO"/> + <reg32 offset="0x0169" name="RBBM_PERFCTR_PWR_1_HI"/> + <reg32 offset="0x016e" name="RBBM_ALWAYSON_COUNTER_LO"/> + <reg32 offset="0x016f" name="RBBM_ALWAYSON_COUNTER_HI"/> + <array offset="0x0068" name="RBBM_CLOCK_CTL_SP" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x006c" name="RBBM_CLOCK_CTL2_SP" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x0070" name="RBBM_CLOCK_HYST_SP" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x0074" name="RBBM_CLOCK_DELAY_SP" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x0078" name="RBBM_CLOCK_CTL_RB" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x007c" name="RBBM_CLOCK_CTL2_RB" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x0082" name="RBBM_CLOCK_CTL_MARB_CCU" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x0086" name="RBBM_CLOCK_HYST_RB_MARB_CCU" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_COM_DCOM"/> + <reg32 offset="0x0081" name="RBBM_CLOCK_CTL_COM_DCOM"/> + <reg32 offset="0x008a" name="RBBM_CLOCK_CTL_HLSQ"/> + <reg32 offset="0x008b" name="RBBM_CLOCK_HYST_HLSQ"/> + <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_HLSQ"/> + <bitset name="A4XX_CGC_HLSQ"> + <bitfield name="EARLY_CYC" low="20" high="22" type="uint"/> + </bitset> + <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_COM_DCOM"/> + <array offset="0x008e" name="RBBM_CLOCK_DELAY_RB_MARB_CCU_L1" stride="1" length="4"> + <reg32 offset="0x0" name="REG"/> + </array> + <bitset name="A4XX_INT0"> + <bitfield name="RBBM_GPU_IDLE" pos="0"/> + <bitfield name="RBBM_AHB_ERROR" pos="1"/> + <bitfield name="RBBM_REG_TIMEOUT" pos="2"/> + <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/> + <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/> + <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5"/> + <bitfield name="VFD_ERROR" pos="6"/> + <bitfield name="CP_SW_INT" pos="7"/> + <bitfield name="CP_T0_PACKET_IN_IB" pos="8"/> + <bitfield name="CP_OPCODE_ERROR" pos="9"/> + <bitfield name="CP_RESERVED_BIT_ERROR" pos="10"/> + <bitfield name="CP_HW_FAULT" pos="11"/> + <bitfield name="CP_DMA" pos="12"/> + <bitfield name="CP_IB2_INT" pos="13"/> + <bitfield name="CP_IB1_INT" pos="14"/> + <bitfield name="CP_RB_INT" pos="15"/> + <bitfield name="CP_REG_PROTECT_FAULT" pos="16"/> + <bitfield name="CP_RB_DONE_TS" pos="17"/> + <bitfield name="CP_VS_DONE_TS" pos="18"/> + <bitfield name="CP_PS_DONE_TS" pos="19"/> + <bitfield name="CACHE_FLUSH_TS" pos="20"/> + <bitfield name="CP_AHB_ERROR_HALT" pos="21"/> + <bitfield name="MISC_HANG_DETECT" pos="24"/> + <bitfield name="UCHE_OOB_ACCESS" pos="25"/> + </bitset> + + <reg32 offset="0x0099" name="RBBM_SP_REGFILE_SLEEP_CNTL_0"/> + <reg32 offset="0x009a" name="RBBM_SP_REGFILE_SLEEP_CNTL_1"/> + <reg32 offset="0x0168" name="RBBM_PERFCTR_PWR_1_LO"/> + <reg32 offset="0x0170" name="RBBM_PERFCTR_CTL"/> + <reg32 offset="0x0171" name="RBBM_PERFCTR_LOAD_CMD0"/> + <reg32 offset="0x0172" name="RBBM_PERFCTR_LOAD_CMD1"/> + <reg32 offset="0x0173" name="RBBM_PERFCTR_LOAD_CMD2"/> + <reg32 offset="0x0174" name="RBBM_PERFCTR_LOAD_VALUE_LO"/> + <reg32 offset="0x0175" name="RBBM_PERFCTR_LOAD_VALUE_HI"/> + <reg32 offset="0x0176" name="RBBM_PERFCTR_RBBM_SEL_0" type="a4xx_rbbm_perfcounter_select"/> + <reg32 offset="0x0177" name="RBBM_PERFCTR_RBBM_SEL_1" type="a4xx_rbbm_perfcounter_select"/> + <reg32 offset="0x0178" name="RBBM_PERFCTR_RBBM_SEL_2" type="a4xx_rbbm_perfcounter_select"/> + <reg32 offset="0x0179" name="RBBM_PERFCTR_RBBM_SEL_3" type="a4xx_rbbm_perfcounter_select"/> + <reg32 offset="0x017a" name="RBBM_GPU_BUSY_MASKED"/> + <reg32 offset="0x017d" name="RBBM_INT_0_STATUS"/> + <reg32 offset="0x0182" name="RBBM_CLOCK_STATUS"/> + <reg32 offset="0x0189" name="RBBM_AHB_STATUS"/> + <reg32 offset="0x018c" name="RBBM_AHB_ME_SPLIT_STATUS"/> + <reg32 offset="0x018d" name="RBBM_AHB_PFP_SPLIT_STATUS"/> + <reg32 offset="0x018f" name="RBBM_AHB_ERROR_STATUS"/> + <reg32 offset="0x0191" name="RBBM_STATUS"> + <bitfield name="HI_BUSY" pos="0" type="boolean"/> + <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/> + <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/> + <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/> + <bitfield name="VBIF_BUSY" pos="15" type="boolean"/> + <bitfield name="TSE_BUSY" pos="16" type="boolean"/> + <bitfield name="RAS_BUSY" pos="17" type="boolean"/> + <bitfield name="RB_BUSY" pos="18" type="boolean"/> + <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/> + <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/> + <bitfield name="VFD_BUSY" pos="21" type="boolean"/> + <bitfield name="VPC_BUSY" pos="22" type="boolean"/> + <bitfield name="UCHE_BUSY" pos="23" type="boolean"/> + <bitfield name="SP_BUSY" pos="24" type="boolean"/> + <bitfield name="TPL1_BUSY" pos="25" type="boolean"/> + <bitfield name="MARB_BUSY" pos="26" type="boolean"/> + <bitfield name="VSC_BUSY" pos="27" type="boolean"/> + <bitfield name="ARB_BUSY" pos="28" type="boolean"/> + <bitfield name="HLSQ_BUSY" pos="29" type="boolean"/> + <bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/> + <bitfield name="GPU_BUSY" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x019f" name="RBBM_INTERFACE_RRDY_STATUS5"/> + <reg32 offset="0x01b0" name="RBBM_POWER_STATUS"> + <bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/> + </reg32> + <reg32 offset="0x01b8" name="RBBM_WAIT_IDLE_CLOCKS_CTL2"/> + + <!-- CP registers --> + <reg32 offset="0x0228" name="CP_SCRATCH_UMASK"/> + <reg32 offset="0x0229" name="CP_SCRATCH_ADDR"/> + <reg32 offset="0x0200" name="CP_RB_BASE"/> + <reg32 offset="0x0201" name="CP_RB_CNTL"/> + <reg32 offset="0x0205" name="CP_RB_WPTR"/> + <reg32 offset="0x0203" name="CP_RB_RPTR_ADDR"/> + <reg32 offset="0x0204" name="CP_RB_RPTR"/> + <reg32 offset="0x0206" name="CP_IB1_BASE"/> + <reg32 offset="0x0207" name="CP_IB1_BUFSZ"/> + <reg32 offset="0x0208" name="CP_IB2_BASE"/> + <reg32 offset="0x0209" name="CP_IB2_BUFSZ"/> + <reg32 offset="0x020c" name="CP_ME_NRT_ADDR"/> + <reg32 offset="0x020d" name="CP_ME_NRT_DATA"/> + <reg32 offset="0x0217" name="CP_ME_RB_DONE_DATA"/> + <reg32 offset="0x0219" name="CP_QUEUE_THRESH2"/> + <reg32 offset="0x021b" name="CP_MERCIU_SIZE"/> + <reg32 offset="0x021c" name="CP_ROQ_ADDR"/> + <reg32 offset="0x021d" name="CP_ROQ_DATA"/> + <reg32 offset="0x021e" name="CP_MEQ_ADDR"/> + <reg32 offset="0x021f" name="CP_MEQ_DATA"/> + <reg32 offset="0x0220" name="CP_MERCIU_ADDR"/> + <reg32 offset="0x0221" name="CP_MERCIU_DATA"/> + <reg32 offset="0x0222" name="CP_MERCIU_DATA2"/> + <reg32 offset="0x0223" name="CP_PFP_UCODE_ADDR"/> + <reg32 offset="0x0224" name="CP_PFP_UCODE_DATA"/> + <reg32 offset="0x0225" name="CP_ME_RAM_WADDR"/> + <reg32 offset="0x0226" name="CP_ME_RAM_RADDR"/> + <reg32 offset="0x0227" name="CP_ME_RAM_DATA"/> + <reg32 offset="0x022a" name="CP_PREEMPT"/> + <reg32 offset="0x022c" name="CP_CNTL"/> + <reg32 offset="0x022d" name="CP_ME_CNTL"/> + <reg32 offset="0x022e" name="CP_DEBUG"/> + <reg32 offset="0x0231" name="CP_DEBUG_ECO_CONTROL"/> + <reg32 offset="0x0232" name="CP_DRAW_STATE_ADDR"/> + <array offset="0x0240" name="CP_PROTECT" stride="1" length="16"> + <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/> + </array> + <reg32 offset="0x0250" name="CP_PROTECT_CTRL"/> + <reg32 offset="0x04c0" name="CP_ST_BASE"/> + <reg32 offset="0x04ce" name="CP_STQ_AVAIL"/> + <reg32 offset="0x04d0" name="CP_MERCIU_STAT"/> + <reg32 offset="0x04d2" name="CP_WFI_PEND_CTR"/> + <reg32 offset="0x04d8" name="CP_HW_FAULT"/> + <reg32 offset="0x04da" name="CP_PROTECT_STATUS"/> + <reg32 offset="0x04dd" name="CP_EVENTS_IN_FLIGHT"/> + <reg32 offset="0x0500" name="CP_PERFCTR_CP_SEL_0" type="a4xx_cp_perfcounter_select"/> + <reg32 offset="0x0501" name="CP_PERFCTR_CP_SEL_1" type="a4xx_cp_perfcounter_select"/> + <reg32 offset="0x0502" name="CP_PERFCTR_CP_SEL_2" type="a4xx_cp_perfcounter_select"/> + <reg32 offset="0x0503" name="CP_PERFCTR_CP_SEL_3" type="a4xx_cp_perfcounter_select"/> + <reg32 offset="0x0504" name="CP_PERFCTR_CP_SEL_4" type="a4xx_cp_perfcounter_select"/> + <reg32 offset="0x0505" name="CP_PERFCTR_CP_SEL_5" type="a4xx_cp_perfcounter_select"/> + <reg32 offset="0x0506" name="CP_PERFCTR_CP_SEL_6" type="a4xx_cp_perfcounter_select"/> + <reg32 offset="0x0507" name="CP_PERFCTR_CP_SEL_7" type="a4xx_cp_perfcounter_select"/> + <reg32 offset="0x050b" name="CP_PERFCOMBINER_SELECT"/> + <array offset="0x0578" name="CP_SCRATCH" stride="1" length="23"> + <reg32 offset="0x0" name="REG"/> + </array> + + + <!-- SP registers --> + <reg32 offset="0x0ec0" name="SP_VS_STATUS"/> + <reg32 offset="0x0ec3" name="SP_MODE_CONTROL"/> + + <reg32 offset="0x0ec4" name="SP_PERFCTR_SP_SEL_0" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec5" name="SP_PERFCTR_SP_SEL_1" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec6" name="SP_PERFCTR_SP_SEL_2" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec7" name="SP_PERFCTR_SP_SEL_3" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec8" name="SP_PERFCTR_SP_SEL_4" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ec9" name="SP_PERFCTR_SP_SEL_5" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0eca" name="SP_PERFCTR_SP_SEL_6" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ecb" name="SP_PERFCTR_SP_SEL_7" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ecc" name="SP_PERFCTR_SP_SEL_8" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ecd" name="SP_PERFCTR_SP_SEL_9" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ece" name="SP_PERFCTR_SP_SEL_10" type="a4xx_sp_perfcounter_select"/> + <reg32 offset="0x0ecf" name="SP_PERFCTR_SP_SEL_11" type="a4xx_sp_perfcounter_select"/> + + <reg32 offset="0x22c0" name="SP_SP_CTRL_REG"> + <bitfield name="BINNING_PASS" pos="19" type="boolean"/> + </reg32> + <reg32 offset="0x22c1" name="SP_INSTR_CACHE_CTRL"> + <!-- set when VS in buffer mode: --> + <bitfield name="VS_BUFFER" pos="7" type="boolean"/> + <!-- set when FS in buffer mode: --> + <bitfield name="FS_BUFFER" pos="8" type="boolean"/> + <!-- set when both VS or FS in buffer mode: --> + <bitfield name="INSTR_BUFFER" pos="10" type="boolean"/> + <!-- TODO other bits probably matter when other stages active? --> + </reg32> + + <bitset name="a4xx_sp_vs_fs_ctrl_reg0" inline="yes"> + <!-- + NOTE that SP_{VS,FS}_CTRL_REG1 are different, but so far REG0 + appears to be the same.. + --> + <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> + <!-- VARYING bit only for FS.. think it controls emitting (ei) flag? --> + <bitfield name="VARYING" pos="1" type="boolean"/> + <!-- maybe CACHEINVALID is two bits?? --> + <bitfield name="CACHEINVALID" pos="2" type="boolean"/> + <doc> + The full/half register footprint is in units of four components, + so if r0.x is used, that counts as all of r0.[xyzw] as used. + There are separate full/half register footprint values as the + full and half registers are independent (not overlapping). + Presumably the thread scheduler hardware allocates the full/half + register names from the actual physical register file and + handles the register renaming. + </doc> + <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/> + <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/> + <!-- maybe INOUTREGOVERLAP is a bitflag? --> + <bitfield name="INOUTREGOVERLAP" low="18" high="19" type="uint"/> + <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/> + <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/> + <bitfield name="PIXLODENABLE" pos="22" type="boolean"/> + </bitset> + + <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/> + <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1"> + <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/> + <bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/> + </reg32> + <reg32 offset="0x22c6" name="SP_VS_PARAM_REG"> + <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/> + <bitfield name="TOTALVSOUTVAR" low="20" high="31" type="uint"/> + </reg32> + <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="16"> + <reg32 offset="0x0" name="REG"> + <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/> + <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/> + <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/> + <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/> + </reg32> + </array> + <array offset="0x22d8" name="SP_VS_VPC_DST" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <doc> + These seem to be offsets for storage of the varyings. + Always seems to start from 8, possibly loc 0 and 4 + are for gl_Position and gl_PointSize? + </doc> + <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> + <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> + <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> + <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> + </reg32> + </array> + + <reg32 offset="0x22e0" name="SP_VS_OBJ_OFFSET_REG"> + <!-- always 00000000: --> + <doc> + From register spec: + SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object + start offset in on chip RAM, + 128bit aligned + </doc> + <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/> + <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/> + </reg32> + <reg32 offset="0x22e1" name="SP_VS_OBJ_START"/> + <reg32 offset="0x22e2" name="SP_VS_PVT_MEM_PARAM"/>" + <reg32 offset="0x22e3" name="SP_VS_PVT_MEM_ADDR"/> + <reg32 offset="0x22e5" name="SP_VS_LENGTH_REG" type="uint"/> + <reg32 offset="0x22e8" name="SP_FS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/> + <reg32 offset="0x22e9" name="SP_FS_CTRL_REG1"> + <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/> + <bitfield name="FACENESS" pos="19" type="boolean"/> + <bitfield name="VARYING" pos="20" type="boolean"/> + <bitfield name="FRAGCOORD" pos="21" type="boolean"/> + </reg32> + <reg32 offset="0x22ea" name="SP_FS_OBJ_OFFSET_REG"> + <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/> + <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/> + </reg32> + <reg32 offset="0x22eb" name="SP_FS_OBJ_START"/> + <reg32 offset="0x22ec" name="SP_FS_PVT_MEM_PARAM"/>" + <reg32 offset="0x22ed" name="SP_FS_PVT_MEM_ADDR"/> + <reg32 offset="0x22ef" name="SP_FS_LENGTH_REG" type="uint"/> + <reg32 offset="0x22f0" name="SP_FS_OUTPUT_REG"> + <bitfield name="MRT" low="0" high="3" type="uint"/> + <bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/> + <!-- TODO double check.. for now assume same as a3xx --> + <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> + <bitfield name="SAMPLEMASK_REGID" low="24" high="31" type="a3xx_regid"/> + </reg32> + <array offset="0x22f1" name="SP_FS_MRT" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="HALF_PRECISION" pos="8" type="boolean"/> + <bitfield name="MRTFORMAT" low="12" high="17" type="a4xx_color_fmt"/> + <bitfield name="COLOR_SRGB" pos="18" type="boolean"/> + </reg32> + </array> + <reg32 offset="0x2300" name="SP_CS_CTRL_REG0"/> + <reg32 offset="0x2301" name="SP_CS_OBJ_OFFSET_REG"/> + <reg32 offset="0x2302" name="SP_CS_OBJ_START"/> + <reg32 offset="0x2303" name="SP_CS_PVT_MEM_PARAM"/> + <reg32 offset="0x2304" name="SP_CS_PVT_MEM_ADDR"/> + <reg32 offset="0x2305" name="SP_CS_PVT_MEM_SIZE"/> + <reg32 offset="0x2306" name="SP_CS_LENGTH_REG" type="uint"/> + <reg32 offset="0x230d" name="SP_HS_OBJ_OFFSET_REG"> + <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/> + <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/> + </reg32> + <reg32 offset="0x230e" name="SP_HS_OBJ_START"/> + <reg32 offset="0x230f" name="SP_HS_PVT_MEM_PARAM"/>" + <reg32 offset="0x2310" name="SP_HS_PVT_MEM_ADDR"/> + <reg32 offset="0x2312" name="SP_HS_LENGTH_REG" type="uint"/> + + <reg32 offset="0x231a" name="SP_DS_PARAM_REG"> + <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/> + </reg32> + <array offset="0x231b" name="SP_DS_OUT" stride="1" length="16"> + <reg32 offset="0x0" name="REG"> + <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/> + <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/> + <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/> + <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/> + </reg32> + </array> + <array offset="0x232c" name="SP_DS_VPC_DST" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <doc> + These seem to be offsets for storage of the varyings. + Always seems to start from 8, possibly loc 0 and 4 + are for gl_Position and gl_PointSize? + </doc> + <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> + <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> + <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> + <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> + </reg32> + </array> + <reg32 offset="0x2334" name="SP_DS_OBJ_OFFSET_REG"> + <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/> + <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2335" name="SP_DS_OBJ_START"/> + <reg32 offset="0x2336" name="SP_DS_PVT_MEM_PARAM"/>" + <reg32 offset="0x2337" name="SP_DS_PVT_MEM_ADDR"/> + <reg32 offset="0x2339" name="SP_DS_LENGTH_REG" type="uint"/> + + <reg32 offset="0x2341" name="SP_GS_PARAM_REG"> + <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="PRIMREGID" low="8" high="15" type="a3xx_regid"/> + <bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/> + </reg32> + <array offset="0x2342" name="SP_GS_OUT" stride="1" length="16"> + <reg32 offset="0x0" name="REG"> + <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/> + <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/> + <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/> + <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/> + </reg32> + </array> + <array offset="0x2353" name="SP_GS_VPC_DST" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <doc> + These seem to be offsets for storage of the varyings. + Always seems to start from 8, possibly loc 0 and 4 + are for gl_Position and gl_PointSize? + </doc> + <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> + <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> + <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> + <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> + </reg32> + </array> + <reg32 offset="0x235b" name="SP_GS_OBJ_OFFSET_REG"> + <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/> + <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/> + </reg32> + <reg32 offset="0x235c" name="SP_GS_OBJ_START"/> + <reg32 offset="0x235d" name="SP_GS_PVT_MEM_PARAM"/>" + <reg32 offset="0x235e" name="SP_GS_PVT_MEM_ADDR"/> + <reg32 offset="0x2360" name="SP_GS_LENGTH_REG" type="uint"/> + + <!-- VPC registers --> + <reg32 offset="0x0e60" name="VPC_DEBUG_RAM_SEL"/> + <reg32 offset="0x0e61" name="VPC_DEBUG_RAM_READ"/> + <reg32 offset="0x0e64" name="VPC_DEBUG_ECO_CONTROL"/> + <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_0" type="a4xx_vpc_perfcounter_select"/> + <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_1" type="a4xx_vpc_perfcounter_select"/> + <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_2" type="a4xx_vpc_perfcounter_select"/> + <reg32 offset="0x0e68" name="VPC_PERFCTR_VPC_SEL_3" type="a4xx_vpc_perfcounter_select"/> + <reg32 offset="0x2140" name="VPC_ATTR"> + <bitfield name="TOTALATTR" low="0" high="8" type="uint"/> + <!-- PSIZE bit set if gl_PointSize written: --> + <bitfield name="PSIZE" pos="9" type="boolean"/> + <bitfield name="THRDASSIGN" low="12" high="13" type="uint"/> + <bitfield name="ENABLE" pos="25" type="boolean"/> + </reg32> + <reg32 offset="0x2141" name="VPC_PACK"> + <bitfield name="NUMBYPASSVAR" low="0" high="7" type="uint"/> + <bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/> + <bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/> + </reg32> + <array offset="0x2142" name="VPC_VARYING_INTERP" stride="1" length="8"> + <reg32 offset="0x0" name="MODE"/> + </array> + <array offset="0x214a" name="VPC_VARYING_PS_REPL" stride="1" length="8"> + <reg32 offset="0x0" name="MODE"/> + </array> + + <reg32 offset="0x216e" name="VPC_SO_FLUSH_WADDR_3"/> + + <!-- VSC registers --> + <reg32 offset="0x0c00" name="VSC_BIN_SIZE"> + <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/> + <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/> + </reg32> + <reg32 offset="0x0c01" name="VSC_SIZE_ADDRESS"/> + <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS2"/> + <reg32 offset="0x0c03" name="VSC_DEBUG_ECO_CONTROL"/> + <array offset="0x0c08" name="VSC_PIPE_CONFIG" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <doc> + Configures the mapping between VSC_PIPE buffer and + bin, X/Y specify the bin index in the horiz/vert + direction (0,0 is upper left, 0,1 is leftmost bin + on second row, and so on). W/H specify the number + of bins assigned to this VSC_PIPE in the horiz/vert + dimension. + </doc> + <bitfield name="X" low="0" high="9" type="uint"/> + <bitfield name="Y" low="10" high="19" type="uint"/> + <bitfield name="W" low="20" high="23" type="uint"/> + <bitfield name="H" low="24" high="27" type="uint"/> + </reg32> + </array> + <array offset="0x0c10" name="VSC_PIPE_DATA_ADDRESS" stride="1" length="8"> + <reg32 offset="0x0" name="REG"/> + </array> + <array offset="0x0c18" name="VSC_PIPE_DATA_LENGTH" stride="1" length="8"> + <reg32 offset="0x0" name="REG"/> + </array> + <reg32 offset="0x0c41" name="VSC_PIPE_PARTIAL_POSN_1"/> + <reg32 offset="0x0c50" name="VSC_PERFCTR_VSC_SEL_0" type="a4xx_vsc_perfcounter_select"/> + <reg32 offset="0x0c51" name="VSC_PERFCTR_VSC_SEL_1" type="a4xx_vsc_perfcounter_select"/> + + <!-- VFD registers --> + <reg32 offset="0x0e40" name="VFD_DEBUG_CONTROL"/> + <reg32 offset="0x0e43" name="VFD_PERFCTR_VFD_SEL_0" type="a4xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e44" name="VFD_PERFCTR_VFD_SEL_1" type="a4xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e45" name="VFD_PERFCTR_VFD_SEL_2" type="a4xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e46" name="VFD_PERFCTR_VFD_SEL_3" type="a4xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e47" name="VFD_PERFCTR_VFD_SEL_4" type="a4xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e48" name="VFD_PERFCTR_VFD_SEL_5" type="a4xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e49" name="VFD_PERFCTR_VFD_SEL_6" type="a4xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e4a" name="VFD_PERFCTR_VFD_SEL_7" type="a4xx_vfd_perfcounter_select"/> + <reg32 offset="0x21d0" name="VGT_CL_INITIATOR"/> + <reg32 offset="0x21d9" name="VGT_EVENT_INITIATOR"/> + <reg32 offset="0x2200" name="VFD_CONTROL_0"> + <doc> + TOTALATTRTOVS is # of attributes to vertex shader, in register + slots (ie. vec4+vec3 -> 7) + </doc> + <bitfield name="TOTALATTRTOVS" low="0" high="7" type="uint"/> + <doc> + BYPASSATTROVS seems to count varyings that are just directly + assigned from attributes (ie, "vFoo = aFoo;") + </doc> + <bitfield name="BYPASSATTROVS" low="9" high="16" type="uint"/> + <doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc> + <bitfield name="STRMDECINSTRCNT" low="20" high="25" type="uint"/> + <doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc> + <bitfield name="STRMFETCHINSTRCNT" low="26" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2201" name="VFD_CONTROL_1"> + <doc>MAXSTORAGE could be # of attributes/vbo's</doc> + <bitfield name="MAXSTORAGE" low="0" high="15" type="uint"/> + <bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/> + <bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0x2202" name="VFD_CONTROL_2"/> + <reg32 offset="0x2203" name="VFD_CONTROL_3"> + <bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/> + <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> + <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0x2204" name="VFD_CONTROL_4"/> + <reg32 offset="0x2208" name="VFD_INDEX_OFFSET"/> + <array offset="0x220a" name="VFD_FETCH" stride="4" length="32"> + <reg32 offset="0x0" name="INSTR_0"> + <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/> + <bitfield name="BUFSTRIDE" low="7" high="16" type="uint"/> + <bitfield name="SWITCHNEXT" pos="19" type="boolean"/> + <bitfield name="INSTANCED" pos="20" type="boolean"/> + </reg32> + <reg32 offset="0x1" name="INSTR_1"/> + <reg32 offset="0x2" name="INSTR_2"> + <bitfield name="SIZE" low="0" high="31"/> + </reg32> + <reg32 offset="0x3" name="INSTR_3"> + <!-- might well be bigger.. --> + <bitfield name="STEPRATE" low="0" high="8" type="uint"/> + </reg32> + </array> + <array offset="0x228a" name="VFD_DECODE" stride="1" length="32"> + <reg32 offset="0x0" name="INSTR"> + <bitfield name="WRITEMASK" low="0" high="3" type="hex"/> + <!-- not sure if this is a bit flag and another flag above it, or?? --> + <bitfield name="CONSTFILL" pos="4" type="boolean"/> + <bitfield name="FORMAT" low="6" high="11" type="a4xx_vtx_fmt"/> + <bitfield name="REGID" low="12" high="19" type="a3xx_regid"/> + <bitfield name="INT" pos="20" type="boolean"/> + <doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc> + <bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/> + <bitfield name="SHIFTCNT" low="24" high="28" type="uint"/> + <bitfield name="LASTCOMPVALID" pos="29" type="boolean"/> + <bitfield name="SWITCHNEXT" pos="30" type="boolean"/> + </reg32> + </array> + + <!-- TPL1 registers --> + <reg32 offset="0x0f00" name="TPL1_DEBUG_ECO_CONTROL"/> + <!-- always 0000003a: --> + <reg32 offset="0x0f03" name="TPL1_TP_MODE_CONTROL"/> + <reg32 offset="0x0f04" name="TPL1_PERFCTR_TP_SEL_0" type="a4xx_tp_perfcounter_select"/> + <reg32 offset="0x0f05" name="TPL1_PERFCTR_TP_SEL_1" type="a4xx_tp_perfcounter_select"/> + <reg32 offset="0x0f06" name="TPL1_PERFCTR_TP_SEL_2" type="a4xx_tp_perfcounter_select"/> + <reg32 offset="0x0f07" name="TPL1_PERFCTR_TP_SEL_3" type="a4xx_tp_perfcounter_select"/> + <reg32 offset="0x0f08" name="TPL1_PERFCTR_TP_SEL_4" type="a4xx_tp_perfcounter_select"/> + <reg32 offset="0x0f09" name="TPL1_PERFCTR_TP_SEL_5" type="a4xx_tp_perfcounter_select"/> + <reg32 offset="0x0f0a" name="TPL1_PERFCTR_TP_SEL_6" type="a4xx_tp_perfcounter_select"/> + <reg32 offset="0x0f0b" name="TPL1_PERFCTR_TP_SEL_7" type="a4xx_tp_perfcounter_select"/> + <reg32 offset="0x2380" name="TPL1_TP_TEX_OFFSET"/> + <reg32 offset="0x2381" name="TPL1_TP_TEX_COUNT"> + <bitfield name="VS" low="0" high="7" type="uint"/> + <bitfield name="HS" low="8" high="15" type="uint"/> + <bitfield name="DS" low="16" high="23" type="uint"/> + <bitfield name="GS" low="24" high="31" type="uint"/> + </reg32> + <reg32 offset="0x2384" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/> + <reg32 offset="0x2387" name="TPL1_TP_HS_BORDER_COLOR_BASE_ADDR"/> + <reg32 offset="0x238a" name="TPL1_TP_DS_BORDER_COLOR_BASE_ADDR"/> + <reg32 offset="0x238d" name="TPL1_TP_GS_BORDER_COLOR_BASE_ADDR"/> + <reg32 offset="0x23a0" name="TPL1_TP_FS_TEX_COUNT"/> + <reg32 offset="0x23a1" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/> + <reg32 offset="0x23a4" name="TPL1_TP_CS_BORDER_COLOR_BASE_ADDR"/> + <reg32 offset="0x23a5" name="TPL1_TP_CS_SAMPLER_BASE_ADDR"/> + <reg32 offset="0x23a6" name="TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR"/> + + <!-- GRAS registers --> + <reg32 offset="0x0c80" name="GRAS_TSE_STATUS"/> + <reg32 offset="0x0c81" name="GRAS_DEBUG_ECO_CONTROL"/> + <reg32 offset="0x0c88" name="GRAS_PERFCTR_TSE_SEL_0" type="a4xx_gras_tse_perfcounter_select"/> + <reg32 offset="0x0c89" name="GRAS_PERFCTR_TSE_SEL_1" type="a4xx_gras_tse_perfcounter_select"/> + <reg32 offset="0x0c8a" name="GRAS_PERFCTR_TSE_SEL_2" type="a4xx_gras_tse_perfcounter_select"/> + <reg32 offset="0x0c8b" name="GRAS_PERFCTR_TSE_SEL_3" type="a4xx_gras_tse_perfcounter_select"/> + <reg32 offset="0x0c8c" name="GRAS_PERFCTR_RAS_SEL_0" type="a4xx_gras_ras_perfcounter_select"/> + <reg32 offset="0x0c8d" name="GRAS_PERFCTR_RAS_SEL_1" type="a4xx_gras_ras_perfcounter_select"/> + <reg32 offset="0x0c8e" name="GRAS_PERFCTR_RAS_SEL_2" type="a4xx_gras_ras_perfcounter_select"/> + <reg32 offset="0x0c8f" name="GRAS_PERFCTR_RAS_SEL_3" type="a4xx_gras_ras_perfcounter_select"/> + <reg32 offset="0x2000" name="GRAS_CL_CLIP_CNTL"> + <bitfield name="CLIP_DISABLE" pos="15" type="boolean"/> + <bitfield name="ZNEAR_CLIP_DISABLE" pos="16" type="boolean"/> + <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/> + <bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean"/> + </reg32> + <reg32 offset="0x2003" name="GRAS_CLEAR_CNTL"> + <!-- probably not the right name, but.. --> + <!-- bit0 set for everything *but* fastclear --> + <bitfield name="NOT_FASTCLEAR" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x2004" name="GRAS_CL_GB_CLIP_ADJ"> + <bitfield name="HORZ" low="0" high="9" type="uint"/> + <bitfield name="VERT" low="10" high="19" type="uint"/> + </reg32> + <reg32 offset="0x2008" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/> + <reg32 offset="0x2009" name="GRAS_CL_VPORT_XSCALE_0" type="float"/> + <reg32 offset="0x200a" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/> + <reg32 offset="0x200b" name="GRAS_CL_VPORT_YSCALE_0" type="float"/> + <reg32 offset="0x200c" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/> + <reg32 offset="0x200d" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/> + <reg32 offset="0x2070" name="GRAS_SU_POINT_MINMAX"> + <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> + <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> + </reg32> + <reg32 offset="0x2071" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/> + <reg32 offset="0x2073" name="GRAS_ALPHA_CONTROL"> + <bitfield name="ALPHA_TEST_ENABLE" pos="2" type="boolean"/> + <bitfield name="FORCE_FRAGZ_TO_FS" pos="3" type="boolean"/> + </reg32> + <reg32 offset="0x2074" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/> + <reg32 offset="0x2075" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/> + <reg32 offset="0x2076" name="GRAS_SU_POLY_OFFSET_CLAMP" type="float"/> + <reg32 offset="0x2077" name="GRAS_DEPTH_CONTROL"> + <!-- guestimating that this is GRAS based on addr --> + <bitfield name="FORMAT" low="0" high="1" type="a4xx_depth_format"/> + </reg32> + <reg32 offset="0x2078" name="GRAS_SU_MODE_CONTROL"> + <bitfield name="CULL_FRONT" pos="0" type="boolean"/> + <bitfield name="CULL_BACK" pos="1" type="boolean"/> + <bitfield name="FRONT_CW" pos="2" type="boolean"/> + <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/> + <bitfield name="POLY_OFFSET" pos="11" type="boolean"/> + <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/> + <!-- bit20 set whenever RENDER_MODE = RB_RENDERING_PASS --> + <bitfield name="RENDERING_PASS" pos="20" type="boolean"/> + </reg32> + <reg32 offset="0x207b" name="GRAS_SC_CONTROL"> + <!-- complete wild-ass-guess for sizes of these bitfields.. --> + <bitfield name="RENDER_MODE" low="2" high="3" type="a3xx_render_mode"/> + <bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/> + <bitfield name="MSAA_DISABLE" pos="11" type="boolean"/> + <bitfield name="RASTER_MODE" low="12" high="15"/> + </reg32> + <reg32 offset="0x207c" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/> + <reg32 offset="0x207d" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/> + <reg32 offset="0x209c" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/> + <reg32 offset="0x209d" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/> + <reg32 offset="0x209e" name="GRAS_SC_EXTENT_WINDOW_BR" type="adreno_reg_xy"/> + <reg32 offset="0x209f" name="GRAS_SC_EXTENT_WINDOW_TL" type="adreno_reg_xy"/> + + <!-- UCHE registers --> + <reg32 offset="0x0e80" name="UCHE_CACHE_MODE_CONTROL"/> + <reg32 offset="0x0e83" name="UCHE_TRAP_BASE_LO"/> + <reg32 offset="0x0e84" name="UCHE_TRAP_BASE_HI"/> + <reg32 offset="0x0e88" name="UCHE_CACHE_STATUS"/> + <reg32 offset="0x0e8a" name="UCHE_INVALIDATE0"/> + <reg32 offset="0x0e8b" name="UCHE_INVALIDATE1"/> + <reg32 offset="0x0e8c" name="UCHE_CACHE_WAYS_VFD"/> + <reg32 offset="0x0e8e" name="UCHE_PERFCTR_UCHE_SEL_0" type="a4xx_uche_perfcounter_select"/> + <reg32 offset="0x0e8f" name="UCHE_PERFCTR_UCHE_SEL_1" type="a4xx_uche_perfcounter_select"/> + <reg32 offset="0x0e90" name="UCHE_PERFCTR_UCHE_SEL_2" type="a4xx_uche_perfcounter_select"/> + <reg32 offset="0x0e91" name="UCHE_PERFCTR_UCHE_SEL_3" type="a4xx_uche_perfcounter_select"/> + <reg32 offset="0x0e92" name="UCHE_PERFCTR_UCHE_SEL_4" type="a4xx_uche_perfcounter_select"/> + <reg32 offset="0x0e93" name="UCHE_PERFCTR_UCHE_SEL_5" type="a4xx_uche_perfcounter_select"/> + <reg32 offset="0x0e94" name="UCHE_PERFCTR_UCHE_SEL_6" type="a4xx_uche_perfcounter_select"/> + <reg32 offset="0x0e95" name="UCHE_PERFCTR_UCHE_SEL_7" type="a4xx_uche_perfcounter_select"/> + + <!-- HLSQ registers --> + <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD"/> + <reg32 offset="0x0e04" name="HLSQ_DEBUG_ECO_CONTROL"/> + <!-- always 00000000: --> + <reg32 offset="0x0e05" name="HLSQ_MODE_CONTROL"/> + <reg32 offset="0x0e0e" name="HLSQ_PERF_PIPE_MASK"/> + <reg32 offset="0x0e06" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a4xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e07" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a4xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e08" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a4xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e09" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a4xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e0a" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a4xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e0b" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a4xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e0c" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a4xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e0d" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a4xx_hlsq_perfcounter_select"/> + <reg32 offset="0x23c0" name="HLSQ_CONTROL_0_REG"> + <!-- I guess same as a3xx, but so far only seen 08000050 --> + <bitfield name="FSTHREADSIZE" pos="4" type="a3xx_threadsize"/> + <bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/> + <bitfield name="SPSHADERRESTART" pos="9" type="boolean"/> + <bitfield name="RESERVED2" pos="10" type="boolean"/> + <bitfield name="CHUNKDISABLE" pos="26" type="boolean"/> + <bitfield name="CONSTMODE" pos="27" type="uint"/> + <bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/> + <bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/> + <bitfield name="TPFULLUPDATE" pos="30" type="boolean"/> + <bitfield name="SINGLECONTEXT" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x23c1" name="HLSQ_CONTROL_1_REG"> + <bitfield name="VSTHREADSIZE" pos="6" type="a3xx_threadsize"/> + <bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/> + <bitfield name="RESERVED1" pos="9" type="boolean"/> + <bitfield name="COORDREGID" low="16" high="23" type="a3xx_regid"/> + <!-- set if gl_FragCoord.[zw] used in frag shader: --> + <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0x23c2" name="HLSQ_CONTROL_2_REG"> + <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/> + <bitfield name="FACEREGID" low="2" high="9" type="a3xx_regid"/> + <bitfield name="SAMPLEID_REGID" low="10" high="17" type="a3xx_regid"/> + <bitfield name="SAMPLEMASK_REGID" low="18" high="25" type="a3xx_regid"/> + </reg32> + <reg32 offset="0x23c3" name="HLSQ_CONTROL_3_REG"> + <!-- register loaded with position (bary.f, gl_FragCoord, etc) --> + <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> + </reg32> + <!-- 0x23c4 3 regids, lowest one goes to 0 when *not* per-sample shading --> + <reg32 offset="0x23c4" name="HLSQ_CONTROL_4_REG"/> + + <bitset name="a4xx_xs_control_reg" inline="yes"> + <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/> + <bitfield name="CONSTOBJECTOFFSET" low="8" high="14" type="uint"/> + <bitfield name="SSBO_ENABLE" pos="15"/> + <bitfield name="ENABLED" pos="16"/> + <bitfield name="SHADEROBJOFFSET" low="17" high="23" type="uint"/> + <bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/> + </bitset> + <reg32 offset="0x23c5" name="HLSQ_VS_CONTROL_REG" type="a4xx_xs_control_reg"/> + <reg32 offset="0x23c6" name="HLSQ_FS_CONTROL_REG" type="a4xx_xs_control_reg"/> + <reg32 offset="0x23c7" name="HLSQ_HS_CONTROL_REG" type="a4xx_xs_control_reg"/> + <reg32 offset="0x23c8" name="HLSQ_DS_CONTROL_REG" type="a4xx_xs_control_reg"/> + <reg32 offset="0x23c9" name="HLSQ_GS_CONTROL_REG" type="a4xx_xs_control_reg"/> + <reg32 offset="0x23ca" name="HLSQ_CS_CONTROL_REG" type="a4xx_xs_control_reg"/> + <reg32 offset="0x23cd" name="HLSQ_CL_NDRANGE_0"> + <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> + <!-- localsize is value minus one: --> + <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> + <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> + <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> + </reg32> + <reg32 offset="0x23ce" name="HLSQ_CL_NDRANGE_1"> + <bitfield name="SIZE_X" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0x23cf" name="HLSQ_CL_NDRANGE_2"/> + <reg32 offset="0x23d0" name="HLSQ_CL_NDRANGE_3"> + <bitfield name="SIZE_Y" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0x23d1" name="HLSQ_CL_NDRANGE_4"/> + <reg32 offset="0x23d2" name="HLSQ_CL_NDRANGE_5"> + <bitfield name="SIZE_Z" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0x23d3" name="HLSQ_CL_NDRANGE_6"/> + <reg32 offset="0x23d4" name="HLSQ_CL_CONTROL_0"> + <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0x23d5" name="HLSQ_CL_CONTROL_1"/> + <reg32 offset="0x23d6" name="HLSQ_CL_KERNEL_CONST"/> + <reg32 offset="0x23d7" name="HLSQ_CL_KERNEL_GROUP_X"/> + <reg32 offset="0x23d8" name="HLSQ_CL_KERNEL_GROUP_Y"/> + <reg32 offset="0x23d9" name="HLSQ_CL_KERNEL_GROUP_Z"/> + <reg32 offset="0x23da" name="HLSQ_CL_WG_OFFSET"/> + <reg32 offset="0x23db" name="HLSQ_UPDATE_CONTROL"/> + + <!-- PC registers --> + <reg32 offset="0x0d00" name="PC_BINNING_COMMAND"> + <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR"/> + <reg32 offset="0x0d0c" name="PC_DRAWCALL_SETUP_OVERRIDE"/> + <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a4xx_pc_perfcounter_select"/> + <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a4xx_pc_perfcounter_select"/> + <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a4xx_pc_perfcounter_select"/> + <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a4xx_pc_perfcounter_select"/> + <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a4xx_pc_perfcounter_select"/> + <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a4xx_pc_perfcounter_select"/> + <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a4xx_pc_perfcounter_select"/> + <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a4xx_pc_perfcounter_select"/> + <reg32 offset="0x21c0" name="PC_BIN_BASE"/> + <reg32 offset="0x21c2" name="PC_VSTREAM_CONTROL"> + <doc>SIZE is current pipe width * height (in tiles)</doc> + <bitfield name="SIZE" low="16" high="21" type="uint"/> + <doc> + N is some sort of slot # between 0..(SIZE-1). In case + multiple tiles use same pipe, each tile gets unique slot # + </doc> + <bitfield name="N" low="22" high="26" type="uint"/> + </reg32> + <reg32 offset="0x21c4" name="PC_PRIM_VTX_CNTL"> + <!-- bit0 set if there is >= 1 varying (actually used by FS) --> + <bitfield name="VAROUT" low="0" high="3" type="uint"> + <doc>in groups of 4x vec4, blob only uses values + 0, 1, 2, 4, 6, 8</doc> + </bitfield> + <bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/> + <bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/> + <!-- PSIZE bit set if gl_PointSize written: --> + <bitfield name="PSIZE" pos="26" type="boolean"/> + </reg32> + <reg32 offset="0x21c5" name="PC_PRIM_VTX_CNTL2"> + <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/> + <bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/> + <bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/> + </reg32> + <reg32 offset="0x21c6" name="PC_RESTART_INDEX"/> + <reg32 offset="0x21e5" name="PC_GS_PARAM"> + <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- +1, i.e. max is 1024 --> + <bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- +1, i.e. max is 32 --> + <bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/> + <bitfield name="LAYER" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x21e7" name="PC_HS_PARAM"> + <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/> + <bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/> + <bitfield name="CW" pos="23" type="boolean"/> + <bitfield name="CONNECTED" pos="24" type="boolean"/> + </reg32> + + <!-- VBIF registers --> + <reg32 offset="0x3000" name="VBIF_VERSION"/> + <reg32 offset="0x3001" name="VBIF_CLKON"> + <bitfield name="FORCE_ON_TESTBUS" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/> + <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/> + <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/> + <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/> + <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/> + <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/> + <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/> + <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/> + <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/> + <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/> + <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/> + <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/> + <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a4xx_vbif_perfcounter_select"/> + <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a4xx_vbif_perfcounter_select"/> + <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a4xx_vbif_perfcounter_select"/> + <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a4xx_vbif_perfcounter_select"/> + <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/> + <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/> + <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/> + <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/> + <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/> + <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/> + <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/> + <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/> + <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/> + <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/> + <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/> + + <!-- + Unknown registers: + (mostly related to DX11 features not used yet, I guess?) + --> + + <!-- always 00000006: --> + <reg32 offset="0x0cc5" name="UNKNOWN_0CC5"/> + + <!-- always 00000000: --> + <reg32 offset="0x0cc6" name="UNKNOWN_0CC6"/> + + <!-- always 00000001: --> + <reg32 offset="0x0d01" name="UNKNOWN_0D01"/> + + <!-- always 00000000: --> + <reg32 offset="0x0e42" name="UNKNOWN_0E42"/> + + <!-- always 00040000: --> + <reg32 offset="0x0ec2" name="UNKNOWN_0EC2"/> + + <!-- always 00000000: --> + <reg32 offset="0x2001" name="UNKNOWN_2001"/> + + <!-- always 00000000: --> + <reg32 offset="0x209b" name="UNKNOWN_209B"/> + + <!-- always 00000000: --> + <reg32 offset="0x20ef" name="UNKNOWN_20EF"/> + + <!-- always 00000000: --> + <reg32 offset="0x2152" name="UNKNOWN_2152"/> + + <!-- always 00000000: --> + <reg32 offset="0x2153" name="UNKNOWN_2153"/> + + <!-- always 00000000: --> + <reg32 offset="0x2154" name="UNKNOWN_2154"/> + + <!-- always 00000000: --> + <reg32 offset="0x2155" name="UNKNOWN_2155"/> + + <!-- always 00000000: --> + <reg32 offset="0x2156" name="UNKNOWN_2156"/> + + <!-- always 00000000: --> + <reg32 offset="0x2157" name="UNKNOWN_2157"/> + + <!-- always 0000000b: --> + <reg32 offset="0x21c3" name="UNKNOWN_21C3"/> + + <!-- always 00000001: --> + <reg32 offset="0x21e6" name="UNKNOWN_21E6"/> + + <!-- always 00000000: --> + <reg32 offset="0x2209" name="UNKNOWN_2209"/> + + <!-- always 00000000: --> + <reg32 offset="0x22d7" name="UNKNOWN_22D7"/> + + <!-- always 00fcfc00: --> + <reg32 offset="0x2352" name="UNKNOWN_2352"/> + +</domain> + + +<domain name="A4XX_TEX_SAMP" width="32"> + <doc>Texture sampler dwords</doc> + <enum name="a4xx_tex_filter"> + <value name="A4XX_TEX_NEAREST" value="0"/> + <value name="A4XX_TEX_LINEAR" value="1"/> + <value name="A4XX_TEX_ANISO" value="2"/> + </enum> + <enum name="a4xx_tex_clamp"> + <value name="A4XX_TEX_REPEAT" value="0"/> + <value name="A4XX_TEX_CLAMP_TO_EDGE" value="1"/> + <value name="A4XX_TEX_MIRROR_REPEAT" value="2"/> + <value name="A4XX_TEX_CLAMP_TO_BORDER" value="3"/> + <value name="A4XX_TEX_MIRROR_CLAMP" value="4"/> + </enum> + <enum name="a4xx_tex_aniso"> + <value name="A4XX_TEX_ANISO_1" value="0"/> + <value name="A4XX_TEX_ANISO_2" value="1"/> + <value name="A4XX_TEX_ANISO_4" value="2"/> + <value name="A4XX_TEX_ANISO_8" value="3"/> + <value name="A4XX_TEX_ANISO_16" value="4"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> + <bitfield name="XY_MAG" low="1" high="2" type="a4xx_tex_filter"/> + <bitfield name="XY_MIN" low="3" high="4" type="a4xx_tex_filter"/> + <bitfield name="WRAP_S" low="5" high="7" type="a4xx_tex_clamp"/> + <bitfield name="WRAP_T" low="8" high="10" type="a4xx_tex_clamp"/> + <bitfield name="WRAP_R" low="11" high="13" type="a4xx_tex_clamp"/> + <bitfield name="ANISO" low="14" high="16" type="a4xx_tex_aniso"/> + <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real --> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/> + <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/> + <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/> + <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/> + <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/> + <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/> + </reg32> +</domain> + +<domain name="A4XX_TEX_CONST" width="32"> + <doc>Texture constant dwords</doc> + <enum name="a4xx_tex_swiz"> + <!-- same as a2xx? --> + <value name="A4XX_TEX_X" value="0"/> + <value name="A4XX_TEX_Y" value="1"/> + <value name="A4XX_TEX_Z" value="2"/> + <value name="A4XX_TEX_W" value="3"/> + <value name="A4XX_TEX_ZERO" value="4"/> + <value name="A4XX_TEX_ONE" value="5"/> + </enum> + <enum name="a4xx_tex_type"> + <value name="A4XX_TEX_1D" value="0"/> + <value name="A4XX_TEX_2D" value="1"/> + <value name="A4XX_TEX_CUBE" value="2"/> + <value name="A4XX_TEX_3D" value="3"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="TILED" pos="0" type="boolean"/> + <bitfield name="SRGB" pos="2" type="boolean"/> + <bitfield name="SWIZ_X" low="4" high="6" type="a4xx_tex_swiz"/> + <bitfield name="SWIZ_Y" low="7" high="9" type="a4xx_tex_swiz"/> + <bitfield name="SWIZ_Z" low="10" high="12" type="a4xx_tex_swiz"/> + <bitfield name="SWIZ_W" low="13" high="15" type="a4xx_tex_swiz"/> + <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> + <bitfield name="FMT" low="22" high="28" type="a4xx_tex_fmt"/> + <bitfield name="TYPE" low="29" high="30" type="a4xx_tex_type"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="HEIGHT" low="0" high="14" type="uint"/> + <bitfield name="WIDTH" low="15" high="29" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="FETCHSIZE" low="0" high="3" type="a4xx_tex_fetchsize"/> + <doc>Pitch in bytes (so actually stride)</doc> + <bitfield name="PITCH" low="9" high="29" type="uint"/> + <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="LAYERSZ" low="0" high="13" shr="12" type="uint"/> + <bitfield name="DEPTH" low="18" high="30" type="uint"/> + </reg32> + <reg32 offset="4" name="4"> + <!-- + like a3xx we seem to have two LAYERSZ's.. although this one + seems too small to be useful, and when it overflows blob just + sets it to zero.. + --> + <bitfield name="LAYERSZ" low="0" high="3" shr="12" type="uint"/> + <bitfield name="BASE" low="5" high="31" shr="5"/> + </reg32> + <reg32 offset="5" name="5"/> + <reg32 offset="6" name="6"/> + <reg32 offset="7" name="7"/> +</domain> + +<domain name="A4XX_SSBO_0" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="BASE" low="5" high="31" shr="5"/> + </reg32> + <reg32 offset="1" name="1"> + <doc>Pitch in bytes (so actually stride)</doc> + <bitfield name="PITCH" low="0" high="21" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/> + </reg32> + <reg32 offset="3" name="3"> + <!-- bytes per pixel: --> + <bitfield name="CPP" low="0" high="5" type="uint"/> + </reg32> +</domain> + +<domain name="A4XX_SSBO_1" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="CPP" low="0" high="4" type="uint"/> + <bitfield name="FMT" low="8" high="15" type="a4xx_color_fmt"/> + <bitfield name="WIDTH" low="16" high="31" type="uint"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="HEIGHT" low="0" high="15" type="uint"/> + <bitfield name="DEPTH" low="16" high="31" type="uint"/> + </reg32> +</domain> + +</database> diff --git a/src/freedreno/registers/a4xx.xml.h b/src/freedreno/registers/a4xx.xml.h deleted file mode 100644 index 395ef9cc5b2..00000000000 --- a/src/freedreno/registers/a4xx.xml.h +++ /dev/null @@ -1,4257 +0,0 @@ -#ifndef A4XX_XML -#define A4XX_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2018 by the following authors: -- Rob Clark <[email protected]> (robclark) -- Ilia Mirkin <[email protected]> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum a4xx_color_fmt { - RB4_A8_UNORM = 1, - RB4_R8_UNORM = 2, - RB4_R8_SNORM = 3, - RB4_R8_UINT = 4, - RB4_R8_SINT = 5, - RB4_R4G4B4A4_UNORM = 8, - RB4_R5G5B5A1_UNORM = 10, - RB4_R5G6B5_UNORM = 14, - RB4_R8G8_UNORM = 15, - RB4_R8G8_SNORM = 16, - RB4_R8G8_UINT = 17, - RB4_R8G8_SINT = 18, - RB4_R16_UNORM = 19, - RB4_R16_SNORM = 20, - RB4_R16_FLOAT = 21, - RB4_R16_UINT = 22, - RB4_R16_SINT = 23, - RB4_R8G8B8_UNORM = 25, - RB4_R8G8B8A8_UNORM = 26, - RB4_R8G8B8A8_SNORM = 28, - RB4_R8G8B8A8_UINT = 29, - RB4_R8G8B8A8_SINT = 30, - RB4_R10G10B10A2_UNORM = 31, - RB4_R10G10B10A2_UINT = 34, - RB4_R11G11B10_FLOAT = 39, - RB4_R16G16_UNORM = 40, - RB4_R16G16_SNORM = 41, - RB4_R16G16_FLOAT = 42, - RB4_R16G16_UINT = 43, - RB4_R16G16_SINT = 44, - RB4_R32_FLOAT = 45, - RB4_R32_UINT = 46, - RB4_R32_SINT = 47, - RB4_R16G16B16A16_UNORM = 52, - RB4_R16G16B16A16_SNORM = 53, - RB4_R16G16B16A16_FLOAT = 54, - RB4_R16G16B16A16_UINT = 55, - RB4_R16G16B16A16_SINT = 56, - RB4_R32G32_FLOAT = 57, - RB4_R32G32_UINT = 58, - RB4_R32G32_SINT = 59, - RB4_R32G32B32A32_FLOAT = 60, - RB4_R32G32B32A32_UINT = 61, - RB4_R32G32B32A32_SINT = 62, -}; - -enum a4xx_tile_mode { - TILE4_LINEAR = 0, - TILE4_2 = 2, - TILE4_3 = 3, -}; - -enum a4xx_vtx_fmt { - VFMT4_32_FLOAT = 1, - VFMT4_32_32_FLOAT = 2, - VFMT4_32_32_32_FLOAT = 3, - VFMT4_32_32_32_32_FLOAT = 4, - VFMT4_16_FLOAT = 5, - VFMT4_16_16_FLOAT = 6, - VFMT4_16_16_16_FLOAT = 7, - VFMT4_16_16_16_16_FLOAT = 8, - VFMT4_32_FIXED = 9, - VFMT4_32_32_FIXED = 10, - VFMT4_32_32_32_FIXED = 11, - VFMT4_32_32_32_32_FIXED = 12, - VFMT4_11_11_10_FLOAT = 13, - VFMT4_16_SINT = 16, - VFMT4_16_16_SINT = 17, - VFMT4_16_16_16_SINT = 18, - VFMT4_16_16_16_16_SINT = 19, - VFMT4_16_UINT = 20, - VFMT4_16_16_UINT = 21, - VFMT4_16_16_16_UINT = 22, - VFMT4_16_16_16_16_UINT = 23, - VFMT4_16_SNORM = 24, - VFMT4_16_16_SNORM = 25, - VFMT4_16_16_16_SNORM = 26, - VFMT4_16_16_16_16_SNORM = 27, - VFMT4_16_UNORM = 28, - VFMT4_16_16_UNORM = 29, - VFMT4_16_16_16_UNORM = 30, - VFMT4_16_16_16_16_UNORM = 31, - VFMT4_32_UINT = 32, - VFMT4_32_32_UINT = 33, - VFMT4_32_32_32_UINT = 34, - VFMT4_32_32_32_32_UINT = 35, - VFMT4_32_SINT = 36, - VFMT4_32_32_SINT = 37, - VFMT4_32_32_32_SINT = 38, - VFMT4_32_32_32_32_SINT = 39, - VFMT4_8_UINT = 40, - VFMT4_8_8_UINT = 41, - VFMT4_8_8_8_UINT = 42, - VFMT4_8_8_8_8_UINT = 43, - VFMT4_8_UNORM = 44, - VFMT4_8_8_UNORM = 45, - VFMT4_8_8_8_UNORM = 46, - VFMT4_8_8_8_8_UNORM = 47, - VFMT4_8_SINT = 48, - VFMT4_8_8_SINT = 49, - VFMT4_8_8_8_SINT = 50, - VFMT4_8_8_8_8_SINT = 51, - VFMT4_8_SNORM = 52, - VFMT4_8_8_SNORM = 53, - VFMT4_8_8_8_SNORM = 54, - VFMT4_8_8_8_8_SNORM = 55, - VFMT4_10_10_10_2_UINT = 56, - VFMT4_10_10_10_2_UNORM = 57, - VFMT4_10_10_10_2_SINT = 58, - VFMT4_10_10_10_2_SNORM = 59, - VFMT4_2_10_10_10_UINT = 60, - VFMT4_2_10_10_10_UNORM = 61, - VFMT4_2_10_10_10_SINT = 62, - VFMT4_2_10_10_10_SNORM = 63, -}; - -enum a4xx_tex_fmt { - TFMT4_A8_UNORM = 3, - TFMT4_8_UNORM = 4, - TFMT4_8_SNORM = 5, - TFMT4_8_UINT = 6, - TFMT4_8_SINT = 7, - TFMT4_4_4_4_4_UNORM = 8, - TFMT4_5_5_5_1_UNORM = 9, - TFMT4_5_6_5_UNORM = 11, - TFMT4_L8_A8_UNORM = 13, - TFMT4_8_8_UNORM = 14, - TFMT4_8_8_SNORM = 15, - TFMT4_8_8_UINT = 16, - TFMT4_8_8_SINT = 17, - TFMT4_16_UNORM = 18, - TFMT4_16_SNORM = 19, - TFMT4_16_FLOAT = 20, - TFMT4_16_UINT = 21, - TFMT4_16_SINT = 22, - TFMT4_8_8_8_8_UNORM = 28, - TFMT4_8_8_8_8_SNORM = 29, - TFMT4_8_8_8_8_UINT = 30, - TFMT4_8_8_8_8_SINT = 31, - TFMT4_9_9_9_E5_FLOAT = 32, - TFMT4_10_10_10_2_UNORM = 33, - TFMT4_10_10_10_2_UINT = 34, - TFMT4_11_11_10_FLOAT = 37, - TFMT4_16_16_UNORM = 38, - TFMT4_16_16_SNORM = 39, - TFMT4_16_16_FLOAT = 40, - TFMT4_16_16_UINT = 41, - TFMT4_16_16_SINT = 42, - TFMT4_32_FLOAT = 43, - TFMT4_32_UINT = 44, - TFMT4_32_SINT = 45, - TFMT4_16_16_16_16_UNORM = 51, - TFMT4_16_16_16_16_SNORM = 52, - TFMT4_16_16_16_16_FLOAT = 53, - TFMT4_16_16_16_16_UINT = 54, - TFMT4_16_16_16_16_SINT = 55, - TFMT4_32_32_FLOAT = 56, - TFMT4_32_32_UINT = 57, - TFMT4_32_32_SINT = 58, - TFMT4_32_32_32_FLOAT = 59, - TFMT4_32_32_32_UINT = 60, - TFMT4_32_32_32_SINT = 61, - TFMT4_32_32_32_32_FLOAT = 63, - TFMT4_32_32_32_32_UINT = 64, - TFMT4_32_32_32_32_SINT = 65, - TFMT4_X8Z24_UNORM = 71, - TFMT4_DXT1 = 86, - TFMT4_DXT3 = 87, - TFMT4_DXT5 = 88, - TFMT4_RGTC1_UNORM = 90, - TFMT4_RGTC1_SNORM = 91, - TFMT4_RGTC2_UNORM = 94, - TFMT4_RGTC2_SNORM = 95, - TFMT4_BPTC_UFLOAT = 97, - TFMT4_BPTC_FLOAT = 98, - TFMT4_BPTC = 99, - TFMT4_ATC_RGB = 100, - TFMT4_ATC_RGBA_EXPLICIT = 101, - TFMT4_ATC_RGBA_INTERPOLATED = 102, - TFMT4_ETC2_RG11_UNORM = 103, - TFMT4_ETC2_RG11_SNORM = 104, - TFMT4_ETC2_R11_UNORM = 105, - TFMT4_ETC2_R11_SNORM = 106, - TFMT4_ETC1 = 107, - TFMT4_ETC2_RGB8 = 108, - TFMT4_ETC2_RGBA8 = 109, - TFMT4_ETC2_RGB8A1 = 110, - TFMT4_ASTC_4x4 = 111, - TFMT4_ASTC_5x4 = 112, - TFMT4_ASTC_5x5 = 113, - TFMT4_ASTC_6x5 = 114, - TFMT4_ASTC_6x6 = 115, - TFMT4_ASTC_8x5 = 116, - TFMT4_ASTC_8x6 = 117, - TFMT4_ASTC_8x8 = 118, - TFMT4_ASTC_10x5 = 119, - TFMT4_ASTC_10x6 = 120, - TFMT4_ASTC_10x8 = 121, - TFMT4_ASTC_10x10 = 122, - TFMT4_ASTC_12x10 = 123, - TFMT4_ASTC_12x12 = 124, -}; - -enum a4xx_tex_fetchsize { - TFETCH4_1_BYTE = 0, - TFETCH4_2_BYTE = 1, - TFETCH4_4_BYTE = 2, - TFETCH4_8_BYTE = 3, - TFETCH4_16_BYTE = 4, -}; - -enum a4xx_depth_format { - DEPTH4_NONE = 0, - DEPTH4_16 = 1, - DEPTH4_24_8 = 2, - DEPTH4_32 = 3, -}; - -enum a4xx_ccu_perfcounter_select { - CCU_BUSY_CYCLES = 0, - CCU_RB_DEPTH_RETURN_STALL = 2, - CCU_RB_COLOR_RETURN_STALL = 3, - CCU_DEPTH_BLOCKS = 6, - CCU_COLOR_BLOCKS = 7, - CCU_DEPTH_BLOCK_HIT = 8, - CCU_COLOR_BLOCK_HIT = 9, - CCU_DEPTH_FLAG1_COUNT = 10, - CCU_DEPTH_FLAG2_COUNT = 11, - CCU_DEPTH_FLAG3_COUNT = 12, - CCU_DEPTH_FLAG4_COUNT = 13, - CCU_COLOR_FLAG1_COUNT = 14, - CCU_COLOR_FLAG2_COUNT = 15, - CCU_COLOR_FLAG3_COUNT = 16, - CCU_COLOR_FLAG4_COUNT = 17, - CCU_PARTIAL_BLOCK_READ = 18, -}; - -enum a4xx_cp_perfcounter_select { - CP_ALWAYS_COUNT = 0, - CP_BUSY = 1, - CP_PFP_IDLE = 2, - CP_PFP_BUSY_WORKING = 3, - CP_PFP_STALL_CYCLES_ANY = 4, - CP_PFP_STARVE_CYCLES_ANY = 5, - CP_PFP_STARVED_PER_LOAD_ADDR = 6, - CP_PFP_STALLED_PER_STORE_ADDR = 7, - CP_PFP_PC_PROFILE = 8, - CP_PFP_MATCH_PM4_PKT_PROFILE = 9, - CP_PFP_COND_INDIRECT_DISCARDED = 10, - CP_LONG_RESUMPTIONS = 11, - CP_RESUME_CYCLES = 12, - CP_RESUME_TO_BOUNDARY_CYCLES = 13, - CP_LONG_PREEMPTIONS = 14, - CP_PREEMPT_CYCLES = 15, - CP_PREEMPT_TO_BOUNDARY_CYCLES = 16, - CP_ME_FIFO_EMPTY_PFP_IDLE = 17, - CP_ME_FIFO_EMPTY_PFP_BUSY = 18, - CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19, - CP_ME_FIFO_FULL_ME_BUSY = 20, - CP_ME_FIFO_FULL_ME_NON_WORKING = 21, - CP_ME_WAITING_FOR_PACKETS = 22, - CP_ME_BUSY_WORKING = 23, - CP_ME_STARVE_CYCLES_ANY = 24, - CP_ME_STARVE_CYCLES_PER_PROFILE = 25, - CP_ME_STALL_CYCLES_PER_PROFILE = 26, - CP_ME_PC_PROFILE = 27, - CP_RCIU_FIFO_EMPTY = 28, - CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29, - CP_RCIU_FIFO_FULL = 30, - CP_RCIU_FIFO_FULL_NO_CONTEXT = 31, - CP_RCIU_FIFO_FULL_AHB_MASTER = 32, - CP_RCIU_FIFO_FULL_OTHER = 33, - CP_AHB_IDLE = 34, - CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35, - CP_AHB_STALL_ON_GRANT_SPLIT = 36, - CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37, - CP_AHB_BUSY_WORKING = 38, - CP_AHB_BUSY_STALL_ON_HRDY = 39, - CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40, -}; - -enum a4xx_gras_ras_perfcounter_select { - RAS_SUPER_TILES = 0, - RAS_8X8_TILES = 1, - RAS_4X4_TILES = 2, - RAS_BUSY_CYCLES = 3, - RAS_STALL_CYCLES_BY_RB = 4, - RAS_STALL_CYCLES_BY_VSC = 5, - RAS_STARVE_CYCLES_BY_TSE = 6, - RAS_SUPERTILE_CYCLES = 7, - RAS_TILE_CYCLES = 8, - RAS_FULLY_COVERED_SUPER_TILES = 9, - RAS_FULLY_COVERED_8X8_TILES = 10, - RAS_4X4_PRIM = 11, - RAS_8X4_4X8_PRIM = 12, - RAS_8X8_PRIM = 13, -}; - -enum a4xx_gras_tse_perfcounter_select { - TSE_INPUT_PRIM = 0, - TSE_INPUT_NULL_PRIM = 1, - TSE_TRIVAL_REJ_PRIM = 2, - TSE_CLIPPED_PRIM = 3, - TSE_NEW_PRIM = 4, - TSE_ZERO_AREA_PRIM = 5, - TSE_FACENESS_CULLED_PRIM = 6, - TSE_ZERO_PIXEL_PRIM = 7, - TSE_OUTPUT_NULL_PRIM = 8, - TSE_OUTPUT_VISIBLE_PRIM = 9, - TSE_PRE_CLIP_PRIM = 10, - TSE_POST_CLIP_PRIM = 11, - TSE_BUSY_CYCLES = 12, - TSE_PC_STARVE = 13, - TSE_RAS_STALL = 14, - TSE_STALL_BARYPLANE_FIFO_FULL = 15, - TSE_STALL_ZPLANE_FIFO_FULL = 16, -}; - -enum a4xx_hlsq_perfcounter_select { - HLSQ_SP_VS_STAGE_CONSTANT = 0, - HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1, - HLSQ_SP_FS_STAGE_CONSTANT = 2, - HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3, - HLSQ_TP_STATE = 4, - HLSQ_QUADS = 5, - HLSQ_PIXELS = 6, - HLSQ_VERTICES = 7, - HLSQ_SP_VS_STAGE_DATA_BYTES = 13, - HLSQ_SP_FS_STAGE_DATA_BYTES = 14, - HLSQ_BUSY_CYCLES = 15, - HLSQ_STALL_CYCLES_SP_STATE = 16, - HLSQ_STALL_CYCLES_SP_VS_STAGE = 17, - HLSQ_STALL_CYCLES_SP_FS_STAGE = 18, - HLSQ_STALL_CYCLES_UCHE = 19, - HLSQ_RBBM_LOAD_CYCLES = 20, - HLSQ_DI_TO_VS_START_SP = 21, - HLSQ_DI_TO_FS_START_SP = 22, - HLSQ_VS_STAGE_START_TO_DONE_SP = 23, - HLSQ_FS_STAGE_START_TO_DONE_SP = 24, - HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25, - HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26, - HLSQ_UCHE_LATENCY_CYCLES = 27, - HLSQ_UCHE_LATENCY_COUNT = 28, - HLSQ_STARVE_CYCLES_VFD = 29, -}; - -enum a4xx_pc_perfcounter_select { - PC_VIS_STREAMS_LOADED = 0, - PC_VPC_PRIMITIVES = 2, - PC_DEAD_PRIM = 3, - PC_LIVE_PRIM = 4, - PC_DEAD_DRAWCALLS = 5, - PC_LIVE_DRAWCALLS = 6, - PC_VERTEX_MISSES = 7, - PC_STALL_CYCLES_VFD = 9, - PC_STALL_CYCLES_TSE = 10, - PC_STALL_CYCLES_UCHE = 11, - PC_WORKING_CYCLES = 12, - PC_IA_VERTICES = 13, - PC_GS_PRIMITIVES = 14, - PC_HS_INVOCATIONS = 15, - PC_DS_INVOCATIONS = 16, - PC_DS_PRIMITIVES = 17, - PC_STARVE_CYCLES_FOR_INDEX = 20, - PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21, - PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22, - PC_STALL_CYCLES_TESS = 23, - PC_STARVE_CYCLES_FOR_POSITION = 24, - PC_MODE0_DRAWCALL = 25, - PC_MODE1_DRAWCALL = 26, - PC_MODE2_DRAWCALL = 27, - PC_MODE3_DRAWCALL = 28, - PC_MODE4_DRAWCALL = 29, - PC_PREDICATED_DEAD_DRAWCALL = 30, - PC_STALL_CYCLES_BY_TSE_ONLY = 31, - PC_STALL_CYCLES_BY_VPC_ONLY = 32, - PC_VPC_POS_DATA_TRANSACTION = 33, - PC_BUSY_CYCLES = 34, - PC_STARVE_CYCLES_DI = 35, - PC_STALL_CYCLES_VPC = 36, - TESS_WORKING_CYCLES = 37, - TESS_NUM_CYCLES_SETUP_WORKING = 38, - TESS_NUM_CYCLES_PTGEN_WORKING = 39, - TESS_NUM_CYCLES_CONNGEN_WORKING = 40, - TESS_BUSY_CYCLES = 41, - TESS_STARVE_CYCLES_PC = 42, - TESS_STALL_CYCLES_PC = 43, -}; - -enum a4xx_pwr_perfcounter_select { - PWR_CORE_CLOCK_CYCLES = 0, - PWR_BUSY_CLOCK_CYCLES = 1, -}; - -enum a4xx_rb_perfcounter_select { - RB_BUSY_CYCLES = 0, - RB_BUSY_CYCLES_BINNING = 1, - RB_BUSY_CYCLES_RENDERING = 2, - RB_BUSY_CYCLES_RESOLVE = 3, - RB_STARVE_CYCLES_BY_SP = 4, - RB_STARVE_CYCLES_BY_RAS = 5, - RB_STARVE_CYCLES_BY_MARB = 6, - RB_STALL_CYCLES_BY_MARB = 7, - RB_STALL_CYCLES_BY_HLSQ = 8, - RB_RB_RB_MARB_DATA = 9, - RB_SP_RB_QUAD = 10, - RB_RAS_RB_Z_QUADS = 11, - RB_GMEM_CH0_READ = 12, - RB_GMEM_CH1_READ = 13, - RB_GMEM_CH0_WRITE = 14, - RB_GMEM_CH1_WRITE = 15, - RB_CP_CONTEXT_DONE = 16, - RB_CP_CACHE_FLUSH = 17, - RB_CP_ZPASS_DONE = 18, - RB_STALL_FIFO0_FULL = 19, - RB_STALL_FIFO1_FULL = 20, - RB_STALL_FIFO2_FULL = 21, - RB_STALL_FIFO3_FULL = 22, - RB_RB_HLSQ_TRANSACTIONS = 23, - RB_Z_READ = 24, - RB_Z_WRITE = 25, - RB_C_READ = 26, - RB_C_WRITE = 27, - RB_C_READ_LATENCY = 28, - RB_Z_READ_LATENCY = 29, - RB_STALL_BY_UCHE = 30, - RB_MARB_UCHE_TRANSACTIONS = 31, - RB_CACHE_STALL_MISS = 32, - RB_CACHE_STALL_FIFO_FULL = 33, - RB_8BIT_BLENDER_UNITS_ACTIVE = 34, - RB_16BIT_BLENDER_UNITS_ACTIVE = 35, - RB_SAMPLER_UNITS_ACTIVE = 36, - RB_TOTAL_PASS = 38, - RB_Z_PASS = 39, - RB_Z_FAIL = 40, - RB_S_FAIL = 41, - RB_POWER0 = 42, - RB_POWER1 = 43, - RB_POWER2 = 44, - RB_POWER3 = 45, - RB_POWER4 = 46, - RB_POWER5 = 47, - RB_POWER6 = 48, - RB_POWER7 = 49, -}; - -enum a4xx_rbbm_perfcounter_select { - RBBM_ALWAYS_ON = 0, - RBBM_VBIF_BUSY = 1, - RBBM_TSE_BUSY = 2, - RBBM_RAS_BUSY = 3, - RBBM_PC_DCALL_BUSY = 4, - RBBM_PC_VSD_BUSY = 5, - RBBM_VFD_BUSY = 6, - RBBM_VPC_BUSY = 7, - RBBM_UCHE_BUSY = 8, - RBBM_VSC_BUSY = 9, - RBBM_HLSQ_BUSY = 10, - RBBM_ANY_RB_BUSY = 11, - RBBM_ANY_TPL1_BUSY = 12, - RBBM_ANY_SP_BUSY = 13, - RBBM_ANY_MARB_BUSY = 14, - RBBM_ANY_ARB_BUSY = 15, - RBBM_AHB_STATUS_BUSY = 16, - RBBM_AHB_STATUS_STALLED = 17, - RBBM_AHB_STATUS_TXFR = 18, - RBBM_AHB_STATUS_TXFR_SPLIT = 19, - RBBM_AHB_STATUS_TXFR_ERROR = 20, - RBBM_AHB_STATUS_LONG_STALL = 21, - RBBM_STATUS_MASKED = 22, - RBBM_CP_BUSY_GFX_CORE_IDLE = 23, - RBBM_TESS_BUSY = 24, - RBBM_COM_BUSY = 25, - RBBM_DCOM_BUSY = 32, - RBBM_ANY_CCU_BUSY = 33, - RBBM_DPM_BUSY = 34, -}; - -enum a4xx_sp_perfcounter_select { - SP_LM_LOAD_INSTRUCTIONS = 0, - SP_LM_STORE_INSTRUCTIONS = 1, - SP_LM_ATOMICS = 2, - SP_GM_LOAD_INSTRUCTIONS = 3, - SP_GM_STORE_INSTRUCTIONS = 4, - SP_GM_ATOMICS = 5, - SP_VS_STAGE_TEX_INSTRUCTIONS = 6, - SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7, - SP_VS_STAGE_EFU_INSTRUCTIONS = 8, - SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9, - SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10, - SP_FS_STAGE_TEX_INSTRUCTIONS = 11, - SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12, - SP_FS_STAGE_EFU_INSTRUCTIONS = 13, - SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14, - SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15, - SP_VS_INSTRUCTIONS = 17, - SP_FS_INSTRUCTIONS = 18, - SP_ADDR_LOCK_COUNT = 19, - SP_UCHE_READ_TRANS = 20, - SP_UCHE_WRITE_TRANS = 21, - SP_EXPORT_VPC_TRANS = 22, - SP_EXPORT_RB_TRANS = 23, - SP_PIXELS_KILLED = 24, - SP_ICL1_REQUESTS = 25, - SP_ICL1_MISSES = 26, - SP_ICL0_REQUESTS = 27, - SP_ICL0_MISSES = 28, - SP_ALU_WORKING_CYCLES = 29, - SP_EFU_WORKING_CYCLES = 30, - SP_STALL_CYCLES_BY_VPC = 31, - SP_STALL_CYCLES_BY_TP = 32, - SP_STALL_CYCLES_BY_UCHE = 33, - SP_STALL_CYCLES_BY_RB = 34, - SP_BUSY_CYCLES = 35, - SP_HS_INSTRUCTIONS = 36, - SP_DS_INSTRUCTIONS = 37, - SP_GS_INSTRUCTIONS = 38, - SP_CS_INSTRUCTIONS = 39, - SP_SCHEDULER_NON_WORKING = 40, - SP_WAVE_CONTEXTS = 41, - SP_WAVE_CONTEXT_CYCLES = 42, - SP_POWER0 = 43, - SP_POWER1 = 44, - SP_POWER2 = 45, - SP_POWER3 = 46, - SP_POWER4 = 47, - SP_POWER5 = 48, - SP_POWER6 = 49, - SP_POWER7 = 50, - SP_POWER8 = 51, - SP_POWER9 = 52, - SP_POWER10 = 53, - SP_POWER11 = 54, - SP_POWER12 = 55, - SP_POWER13 = 56, - SP_POWER14 = 57, - SP_POWER15 = 58, -}; - -enum a4xx_tp_perfcounter_select { - TP_L1_REQUESTS = 0, - TP_L1_MISSES = 1, - TP_QUADS_OFFSET = 8, - TP_QUAD_SHADOW = 9, - TP_QUADS_ARRAY = 10, - TP_QUADS_GRADIENT = 11, - TP_QUADS_1D2D = 12, - TP_QUADS_3DCUBE = 13, - TP_BUSY_CYCLES = 16, - TP_STALL_CYCLES_BY_ARB = 17, - TP_STATE_CACHE_REQUESTS = 20, - TP_STATE_CACHE_MISSES = 21, - TP_POWER0 = 22, - TP_POWER1 = 23, - TP_POWER2 = 24, - TP_POWER3 = 25, - TP_POWER4 = 26, - TP_POWER5 = 27, - TP_POWER6 = 28, - TP_POWER7 = 29, -}; - -enum a4xx_uche_perfcounter_select { - UCHE_VBIF_READ_BEATS_TP = 0, - UCHE_VBIF_READ_BEATS_VFD = 1, - UCHE_VBIF_READ_BEATS_HLSQ = 2, - UCHE_VBIF_READ_BEATS_MARB = 3, - UCHE_VBIF_READ_BEATS_SP = 4, - UCHE_READ_REQUESTS_TP = 5, - UCHE_READ_REQUESTS_VFD = 6, - UCHE_READ_REQUESTS_HLSQ = 7, - UCHE_READ_REQUESTS_MARB = 8, - UCHE_READ_REQUESTS_SP = 9, - UCHE_WRITE_REQUESTS_MARB = 10, - UCHE_WRITE_REQUESTS_SP = 11, - UCHE_TAG_CHECK_FAILS = 12, - UCHE_EVICTS = 13, - UCHE_FLUSHES = 14, - UCHE_VBIF_LATENCY_CYCLES = 15, - UCHE_VBIF_LATENCY_SAMPLES = 16, - UCHE_BUSY_CYCLES = 17, - UCHE_VBIF_READ_BEATS_PC = 18, - UCHE_READ_REQUESTS_PC = 19, - UCHE_WRITE_REQUESTS_VPC = 20, - UCHE_STALL_BY_VBIF = 21, - UCHE_WRITE_REQUESTS_VSC = 22, - UCHE_POWER0 = 23, - UCHE_POWER1 = 24, - UCHE_POWER2 = 25, - UCHE_POWER3 = 26, - UCHE_POWER4 = 27, - UCHE_POWER5 = 28, - UCHE_POWER6 = 29, - UCHE_POWER7 = 30, -}; - -enum a4xx_vbif_perfcounter_select { - AXI_READ_REQUESTS_ID_0 = 0, - AXI_READ_REQUESTS_ID_1 = 1, - AXI_READ_REQUESTS_ID_2 = 2, - AXI_READ_REQUESTS_ID_3 = 3, - AXI_READ_REQUESTS_ID_4 = 4, - AXI_READ_REQUESTS_ID_5 = 5, - AXI_READ_REQUESTS_ID_6 = 6, - AXI_READ_REQUESTS_ID_7 = 7, - AXI_READ_REQUESTS_ID_8 = 8, - AXI_READ_REQUESTS_ID_9 = 9, - AXI_READ_REQUESTS_ID_10 = 10, - AXI_READ_REQUESTS_ID_11 = 11, - AXI_READ_REQUESTS_ID_12 = 12, - AXI_READ_REQUESTS_ID_13 = 13, - AXI_READ_REQUESTS_ID_14 = 14, - AXI_READ_REQUESTS_ID_15 = 15, - AXI0_READ_REQUESTS_TOTAL = 16, - AXI1_READ_REQUESTS_TOTAL = 17, - AXI2_READ_REQUESTS_TOTAL = 18, - AXI3_READ_REQUESTS_TOTAL = 19, - AXI_READ_REQUESTS_TOTAL = 20, - AXI_WRITE_REQUESTS_ID_0 = 21, - AXI_WRITE_REQUESTS_ID_1 = 22, - AXI_WRITE_REQUESTS_ID_2 = 23, - AXI_WRITE_REQUESTS_ID_3 = 24, - AXI_WRITE_REQUESTS_ID_4 = 25, - AXI_WRITE_REQUESTS_ID_5 = 26, - AXI_WRITE_REQUESTS_ID_6 = 27, - AXI_WRITE_REQUESTS_ID_7 = 28, - AXI_WRITE_REQUESTS_ID_8 = 29, - AXI_WRITE_REQUESTS_ID_9 = 30, - AXI_WRITE_REQUESTS_ID_10 = 31, - AXI_WRITE_REQUESTS_ID_11 = 32, - AXI_WRITE_REQUESTS_ID_12 = 33, - AXI_WRITE_REQUESTS_ID_13 = 34, - AXI_WRITE_REQUESTS_ID_14 = 35, - AXI_WRITE_REQUESTS_ID_15 = 36, - AXI0_WRITE_REQUESTS_TOTAL = 37, - AXI1_WRITE_REQUESTS_TOTAL = 38, - AXI2_WRITE_REQUESTS_TOTAL = 39, - AXI3_WRITE_REQUESTS_TOTAL = 40, - AXI_WRITE_REQUESTS_TOTAL = 41, - AXI_TOTAL_REQUESTS = 42, - AXI_READ_DATA_BEATS_ID_0 = 43, - AXI_READ_DATA_BEATS_ID_1 = 44, - AXI_READ_DATA_BEATS_ID_2 = 45, - AXI_READ_DATA_BEATS_ID_3 = 46, - AXI_READ_DATA_BEATS_ID_4 = 47, - AXI_READ_DATA_BEATS_ID_5 = 48, - AXI_READ_DATA_BEATS_ID_6 = 49, - AXI_READ_DATA_BEATS_ID_7 = 50, - AXI_READ_DATA_BEATS_ID_8 = 51, - AXI_READ_DATA_BEATS_ID_9 = 52, - AXI_READ_DATA_BEATS_ID_10 = 53, - AXI_READ_DATA_BEATS_ID_11 = 54, - AXI_READ_DATA_BEATS_ID_12 = 55, - AXI_READ_DATA_BEATS_ID_13 = 56, - AXI_READ_DATA_BEATS_ID_14 = 57, - AXI_READ_DATA_BEATS_ID_15 = 58, - AXI0_READ_DATA_BEATS_TOTAL = 59, - AXI1_READ_DATA_BEATS_TOTAL = 60, - AXI2_READ_DATA_BEATS_TOTAL = 61, - AXI3_READ_DATA_BEATS_TOTAL = 62, - AXI_READ_DATA_BEATS_TOTAL = 63, - AXI_WRITE_DATA_BEATS_ID_0 = 64, - AXI_WRITE_DATA_BEATS_ID_1 = 65, - AXI_WRITE_DATA_BEATS_ID_2 = 66, - AXI_WRITE_DATA_BEATS_ID_3 = 67, - AXI_WRITE_DATA_BEATS_ID_4 = 68, - AXI_WRITE_DATA_BEATS_ID_5 = 69, - AXI_WRITE_DATA_BEATS_ID_6 = 70, - AXI_WRITE_DATA_BEATS_ID_7 = 71, - AXI_WRITE_DATA_BEATS_ID_8 = 72, - AXI_WRITE_DATA_BEATS_ID_9 = 73, - AXI_WRITE_DATA_BEATS_ID_10 = 74, - AXI_WRITE_DATA_BEATS_ID_11 = 75, - AXI_WRITE_DATA_BEATS_ID_12 = 76, - AXI_WRITE_DATA_BEATS_ID_13 = 77, - AXI_WRITE_DATA_BEATS_ID_14 = 78, - AXI_WRITE_DATA_BEATS_ID_15 = 79, - AXI0_WRITE_DATA_BEATS_TOTAL = 80, - AXI1_WRITE_DATA_BEATS_TOTAL = 81, - AXI2_WRITE_DATA_BEATS_TOTAL = 82, - AXI3_WRITE_DATA_BEATS_TOTAL = 83, - AXI_WRITE_DATA_BEATS_TOTAL = 84, - AXI_DATA_BEATS_TOTAL = 85, - CYCLES_HELD_OFF_ID_0 = 86, - CYCLES_HELD_OFF_ID_1 = 87, - CYCLES_HELD_OFF_ID_2 = 88, - CYCLES_HELD_OFF_ID_3 = 89, - CYCLES_HELD_OFF_ID_4 = 90, - CYCLES_HELD_OFF_ID_5 = 91, - CYCLES_HELD_OFF_ID_6 = 92, - CYCLES_HELD_OFF_ID_7 = 93, - CYCLES_HELD_OFF_ID_8 = 94, - CYCLES_HELD_OFF_ID_9 = 95, - CYCLES_HELD_OFF_ID_10 = 96, - CYCLES_HELD_OFF_ID_11 = 97, - CYCLES_HELD_OFF_ID_12 = 98, - CYCLES_HELD_OFF_ID_13 = 99, - CYCLES_HELD_OFF_ID_14 = 100, - CYCLES_HELD_OFF_ID_15 = 101, - AXI_READ_REQUEST_HELD_OFF = 102, - AXI_WRITE_REQUEST_HELD_OFF = 103, - AXI_REQUEST_HELD_OFF = 104, - AXI_WRITE_DATA_HELD_OFF = 105, - OCMEM_AXI_READ_REQUEST_HELD_OFF = 106, - OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107, - OCMEM_AXI_REQUEST_HELD_OFF = 108, - OCMEM_AXI_WRITE_DATA_HELD_OFF = 109, - ELAPSED_CYCLES_DDR = 110, - ELAPSED_CYCLES_OCMEM = 111, -}; - -enum a4xx_vfd_perfcounter_select { - VFD_UCHE_BYTE_FETCHED = 0, - VFD_UCHE_TRANS = 1, - VFD_FETCH_INSTRUCTIONS = 3, - VFD_BUSY_CYCLES = 5, - VFD_STALL_CYCLES_UCHE = 6, - VFD_STALL_CYCLES_HLSQ = 7, - VFD_STALL_CYCLES_VPC_BYPASS = 8, - VFD_STALL_CYCLES_VPC_ALLOC = 9, - VFD_MODE_0_FIBERS = 13, - VFD_MODE_1_FIBERS = 14, - VFD_MODE_2_FIBERS = 15, - VFD_MODE_3_FIBERS = 16, - VFD_MODE_4_FIBERS = 17, - VFD_BFIFO_STALL = 18, - VFD_NUM_VERTICES_TOTAL = 19, - VFD_PACKER_FULL = 20, - VFD_UCHE_REQUEST_FIFO_FULL = 21, - VFD_STARVE_CYCLES_PC = 22, - VFD_STARVE_CYCLES_UCHE = 23, -}; - -enum a4xx_vpc_perfcounter_select { - VPC_SP_LM_COMPONENTS = 2, - VPC_SP0_LM_BYTES = 3, - VPC_SP1_LM_BYTES = 4, - VPC_SP2_LM_BYTES = 5, - VPC_SP3_LM_BYTES = 6, - VPC_WORKING_CYCLES = 7, - VPC_STALL_CYCLES_LM = 8, - VPC_STARVE_CYCLES_RAS = 9, - VPC_STREAMOUT_CYCLES = 10, - VPC_UCHE_TRANSACTIONS = 12, - VPC_STALL_CYCLES_UCHE = 13, - VPC_BUSY_CYCLES = 14, - VPC_STARVE_CYCLES_SP = 15, -}; - -enum a4xx_vsc_perfcounter_select { - VSC_BUSY_CYCLES = 0, - VSC_WORKING_CYCLES = 1, - VSC_STALL_CYCLES_UCHE = 2, - VSC_STARVE_CYCLES_RAS = 3, - VSC_EOT_NUM = 4, -}; - -enum a4xx_tex_filter { - A4XX_TEX_NEAREST = 0, - A4XX_TEX_LINEAR = 1, - A4XX_TEX_ANISO = 2, -}; - -enum a4xx_tex_clamp { - A4XX_TEX_REPEAT = 0, - A4XX_TEX_CLAMP_TO_EDGE = 1, - A4XX_TEX_MIRROR_REPEAT = 2, - A4XX_TEX_CLAMP_TO_BORDER = 3, - A4XX_TEX_MIRROR_CLAMP = 4, -}; - -enum a4xx_tex_aniso { - A4XX_TEX_ANISO_1 = 0, - A4XX_TEX_ANISO_2 = 1, - A4XX_TEX_ANISO_4 = 2, - A4XX_TEX_ANISO_8 = 3, - A4XX_TEX_ANISO_16 = 4, -}; - -enum a4xx_tex_swiz { - A4XX_TEX_X = 0, - A4XX_TEX_Y = 1, - A4XX_TEX_Z = 2, - A4XX_TEX_W = 3, - A4XX_TEX_ZERO = 4, - A4XX_TEX_ONE = 5, -}; - -enum a4xx_tex_type { - A4XX_TEX_1D = 0, - A4XX_TEX_2D = 1, - A4XX_TEX_CUBE = 2, - A4XX_TEX_3D = 3, -}; - -#define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 -#define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 -static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) -{ - return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; -} -#define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 -#define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 -#define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 -#define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 -#define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 -#define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 -#define A4XX_INT0_VFD_ERROR 0x00000040 -#define A4XX_INT0_CP_SW_INT 0x00000080 -#define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 -#define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 -#define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 -#define A4XX_INT0_CP_HW_FAULT 0x00000800 -#define A4XX_INT0_CP_DMA 0x00001000 -#define A4XX_INT0_CP_IB2_INT 0x00002000 -#define A4XX_INT0_CP_IB1_INT 0x00004000 -#define A4XX_INT0_CP_RB_INT 0x00008000 -#define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 -#define A4XX_INT0_CP_RB_DONE_TS 0x00020000 -#define A4XX_INT0_CP_VS_DONE_TS 0x00040000 -#define A4XX_INT0_CP_PS_DONE_TS 0x00080000 -#define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 -#define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 -#define A4XX_INT0_MISC_HANG_DETECT 0x01000000 -#define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 -#define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 - -#define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 - -#define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 - -#define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 - -#define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca - -#define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb - -#define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc - -#define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd - -#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce - -#define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf - -#define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0 - -#define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1 - -#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 - -#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 -#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff -#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 -static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) -{ - return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; -} -#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 -#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 -static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) -{ - return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; -} - -#define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc - -#define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd - -#define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce - -#define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf - -#define REG_A4XX_RB_MODE_CONTROL 0x000020a0 -#define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f -#define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 -static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; -} -#define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 -#define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 -static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; -} -#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000 - -#define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 -#define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 -#define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 - -#define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 -#define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 -#define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 -#define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 -static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) -{ - return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; -} - -#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 -#define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001 -#define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 -#define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 -#define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 -#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 -#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 -#define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 -#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 -#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 -static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) -{ - return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; -} -#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 -#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 - -static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } - -static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } -#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 -#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 -#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 -#define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040 -#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 -#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 -static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) -{ - return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK; -} -#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 -#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 -static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) -{ - return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; -} - -static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } -#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f -#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) -{ - return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; -} -#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 -#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 -static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) -{ - return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; -} -#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 -#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 -static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) -{ - return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; -} -#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 -#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 -static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; -} -#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 -#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000 -#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 -static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) -{ - assert(!(val & 0xf)); - return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; -} - -static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } - -static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } -#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8 -#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 -static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) -{ - return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; -} - -static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } -#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f -#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; -} -#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 -#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; -} -#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 -#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; -} -#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 -#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; -} -#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 -#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; -} -#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 -#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; -} - -#define REG_A4XX_RB_BLEND_RED 0x000020f0 -#define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff -#define A4XX_RB_BLEND_RED_UINT__SHIFT 0 -static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) -{ - return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; -} -#define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 -#define A4XX_RB_BLEND_RED_SINT__SHIFT 8 -static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) -{ - return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK; -} -#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 -#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 -static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; -} - -#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1 -#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff -#define A4XX_RB_BLEND_RED_F32__SHIFT 0 -static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) -{ - return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK; -} - -#define REG_A4XX_RB_BLEND_GREEN 0x000020f2 -#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff -#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 -static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) -{ - return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; -} -#define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 -#define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8 -static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) -{ - return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK; -} -#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 -#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 -static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; -} - -#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3 -#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff -#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0 -static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) -{ - return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK; -} - -#define REG_A4XX_RB_BLEND_BLUE 0x000020f4 -#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff -#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 -static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) -{ - return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; -} -#define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 -#define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8 -static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) -{ - return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK; -} -#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 -#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 -static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; -} - -#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5 -#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff -#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0 -static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) -{ - return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK; -} - -#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 -#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff -#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 -static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) -{ - return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; -} -#define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 -#define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8 -static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) -{ - return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK; -} -#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 -#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 -static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; -} - -#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7 -#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff -#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0 -static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) -{ - return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK; -} - -#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 -#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff -#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 -static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) -{ - return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; -} -#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 -#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 -#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 -static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) -{ - return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; -} - -#define REG_A4XX_RB_FS_OUTPUT 0x000020f9 -#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff -#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 -static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) -{ - return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; -} -#define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100 -#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 -#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 -static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) -{ - return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; -} - -#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa -#define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 -#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc -#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 -static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; -} - -#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb -#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f -#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 -static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) -{ - return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; -} -#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 -#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 -static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) -{ - return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; -} -#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 -#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 -static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) -{ - return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; -} -#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 -#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 -static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) -{ - return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; -} -#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 -#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 -static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) -{ - return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; -} -#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 -#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 -static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) -{ - return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; -} -#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 -#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 -static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) -{ - return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; -} -#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 -#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 -static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) -{ - return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; -} - -#define REG_A4XX_RB_COPY_CONTROL 0x000020fc -#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 -#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 -static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) -{ - return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; -} -#define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 -#define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 -static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) -{ - return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; -} -#define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 -#define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 -static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) -{ - return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; -} -#define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 -#define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 -static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) -{ - assert(!(val & 0x3fff)); - return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; -} - -#define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd -#define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 -#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 -static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; -} - -#define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe -#define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff -#define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 -static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; -} - -#define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff -#define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc -#define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 -static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) -{ - return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; -} -#define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 -#define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 -static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; -} -#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 -#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 -static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) -{ - return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; -} -#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 -#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 -static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) -{ - return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; -} -#define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 -#define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 -static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) -{ - return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; -} -#define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 -#define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 -static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) -{ - return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; -} - -#define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 -#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f -#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 -static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) -{ - return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; -} -#define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 - -#define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 -#define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 -#define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 -#define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 -#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 -#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 -static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) -{ - return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; -} -#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 -#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 -#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000 -#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 - -#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 - -#define REG_A4XX_RB_DEPTH_INFO 0x00002103 -#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 -#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 -static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) -{ - return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; -} -#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 -#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 -static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; -} - -#define REG_A4XX_RB_DEPTH_PITCH 0x00002104 -#define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff -#define A4XX_RB_DEPTH_PITCH__SHIFT 0 -static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; -} - -#define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 -#define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff -#define A4XX_RB_DEPTH_PITCH2__SHIFT 0 -static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; -} - -#define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 -#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 -#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 -#define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 -#define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 -#define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 -static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) -{ - return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; -} -#define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 -#define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 -static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) -{ - return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; -} -#define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 -#define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 -static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) -{ - return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; -} -#define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 -#define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 -static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) -{ - return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; -} -#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 -#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 -static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) -{ - return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; -} -#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 -#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 -static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; -} -#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 -#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 -static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) -{ - return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; -} -#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 -#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 -static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; -} - -#define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 -#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 - -#define REG_A4XX_RB_STENCIL_INFO 0x00002108 -#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 -#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 -#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 -static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; -} - -#define REG_A4XX_RB_STENCIL_PITCH 0x00002109 -#define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff -#define A4XX_RB_STENCIL_PITCH__SHIFT 0 -static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; -} - -#define REG_A4XX_RB_STENCILREFMASK 0x0000210b -#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff -#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 -static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) -{ - return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; -} -#define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 -#define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 -static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) -{ - return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; -} -#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 -#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 -static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) -{ - return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; -} - -#define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c -#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff -#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 -static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) -{ - return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; -} -#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 -#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 -static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) -{ - return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; -} -#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 -#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 -static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) -{ - return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; -} - -#define REG_A4XX_RB_BIN_OFFSET 0x0000210d -#define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 -#define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff -#define A4XX_RB_BIN_OFFSET_X__SHIFT 0 -static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) -{ - return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; -} -#define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 -#define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 -static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) -{ - return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; -} - -static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } - -static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } - -static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } - -#define REG_A4XX_RBBM_HW_VERSION 0x00000000 - -#define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } - -#define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 - -#define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 - -#define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 - -#define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 - -#define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 - -#define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 - -#define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a - -#define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b - -#define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c - -#define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d - -#define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e - -#define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f - -#define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 - -#define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 - -#define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 - -#define REG_A4XX_RBBM_AHB_CTL0 0x00000023 - -#define REG_A4XX_RBBM_AHB_CTL1 0x00000024 - -#define REG_A4XX_RBBM_AHB_CMD 0x00000025 - -#define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 - -#define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 - -#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b - -#define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f - -#define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 - -#define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 - -#define REG_A4XX_RBBM_INT_0_MASK 0x00000037 - -#define REG_A4XX_RBBM_RBBM_CTL 0x0000003e - -#define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f - -#define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 - -#define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 - -#define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 - -#define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 - -#define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 - -#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a - -#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b - -#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c - -#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d - -#define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098 -#define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001 -#define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000 - -#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c - -#define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d - -#define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e - -#define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f - -#define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0 - -#define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1 - -#define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2 - -#define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3 - -#define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4 - -#define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5 - -#define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6 - -#define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7 - -#define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8 - -#define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9 - -#define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa - -#define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab - -#define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac - -#define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad - -#define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae - -#define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af - -#define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0 - -#define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1 - -#define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2 - -#define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3 - -#define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4 - -#define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5 - -#define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6 - -#define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7 - -#define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8 - -#define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9 - -#define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba - -#define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb - -#define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc - -#define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd - -#define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be - -#define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf - -#define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0 - -#define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1 - -#define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2 - -#define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3 - -#define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4 - -#define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5 - -#define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6 - -#define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7 - -#define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8 - -#define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9 - -#define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca - -#define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb - -#define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc - -#define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd - -#define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce - -#define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf - -#define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0 - -#define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1 - -#define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2 - -#define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2 - -#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3 - -#define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4 - -#define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5 - -#define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6 - -#define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7 - -#define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8 - -#define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9 - -#define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea - -#define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb - -#define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec - -#define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed - -#define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee - -#define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef - -#define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0 - -#define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1 - -#define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2 - -#define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3 - -#define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4 - -#define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5 - -#define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6 - -#define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7 - -#define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8 - -#define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9 - -#define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa - -#define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb - -#define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc - -#define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd - -#define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe - -#define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff - -#define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100 - -#define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101 - -#define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102 - -#define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a - -#define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b - -#define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c - -#define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d - -#define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e - -#define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f - -#define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112 - -#define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113 - -#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 - -#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 - -#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 - -#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 - -#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116 - -#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117 - -#define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118 - -#define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119 - -#define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a - -#define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b - -#define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c - -#define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d - -#define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e - -#define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f - -#define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120 - -#define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121 - -#define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122 - -#define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123 - -#define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124 - -#define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125 - -#define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126 - -#define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127 - -#define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128 - -#define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129 - -#define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a - -#define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b - -#define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c - -#define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d - -#define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e - -#define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f - -#define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130 - -#define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131 - -#define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132 - -#define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133 - -#define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134 - -#define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135 - -#define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136 - -#define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137 - -#define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138 - -#define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139 - -#define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a - -#define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b - -#define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c - -#define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d - -#define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e - -#define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f - -#define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140 - -#define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141 - -#define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142 - -#define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143 - -#define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144 - -#define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145 - -#define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146 - -#define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147 - -#define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148 - -#define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149 - -#define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a - -#define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b - -#define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c - -#define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d - -#define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e - -#define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f - -#define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166 - -#define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167 - -#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 - -#define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169 - -#define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e - -#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } - -#define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 - -#define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 - -#define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a - -#define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b - -#define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c - -#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d - -static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } - -static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } - -#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099 - -#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a - -#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 - -#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 - -#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 - -#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 - -#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 - -#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 - -#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 - -#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176 - -#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177 - -#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178 - -#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179 - -#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a - -#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d - -#define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 - -#define REG_A4XX_RBBM_AHB_STATUS 0x00000189 - -#define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c - -#define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d - -#define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f - -#define REG_A4XX_RBBM_STATUS 0x00000191 -#define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 -#define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 -#define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 -#define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 -#define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 -#define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 -#define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 -#define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 -#define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 -#define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 -#define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 -#define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 -#define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 -#define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 -#define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 -#define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 -#define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 -#define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 -#define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 -#define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 -#define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 - -#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f - -#define REG_A4XX_RBBM_POWER_STATUS 0x000001b0 -#define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000 - -#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8 - -#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 - -#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 - -#define REG_A4XX_CP_RB_BASE 0x00000200 - -#define REG_A4XX_CP_RB_CNTL 0x00000201 - -#define REG_A4XX_CP_RB_WPTR 0x00000205 - -#define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 - -#define REG_A4XX_CP_RB_RPTR 0x00000204 - -#define REG_A4XX_CP_IB1_BASE 0x00000206 - -#define REG_A4XX_CP_IB1_BUFSZ 0x00000207 - -#define REG_A4XX_CP_IB2_BASE 0x00000208 - -#define REG_A4XX_CP_IB2_BUFSZ 0x00000209 - -#define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c - -#define REG_A4XX_CP_ME_NRT_DATA 0x0000020d - -#define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 - -#define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 - -#define REG_A4XX_CP_MERCIU_SIZE 0x0000021b - -#define REG_A4XX_CP_ROQ_ADDR 0x0000021c - -#define REG_A4XX_CP_ROQ_DATA 0x0000021d - -#define REG_A4XX_CP_MEQ_ADDR 0x0000021e - -#define REG_A4XX_CP_MEQ_DATA 0x0000021f - -#define REG_A4XX_CP_MERCIU_ADDR 0x00000220 - -#define REG_A4XX_CP_MERCIU_DATA 0x00000221 - -#define REG_A4XX_CP_MERCIU_DATA2 0x00000222 - -#define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 - -#define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 - -#define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 - -#define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 - -#define REG_A4XX_CP_ME_RAM_DATA 0x00000227 - -#define REG_A4XX_CP_PREEMPT 0x0000022a - -#define REG_A4XX_CP_CNTL 0x0000022c - -#define REG_A4XX_CP_ME_CNTL 0x0000022d - -#define REG_A4XX_CP_DEBUG 0x0000022e - -#define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 - -#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 - -static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } - -static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } -#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff -#define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 -static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) -{ - return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK; -} -#define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 -#define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 -static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) -{ - return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; -} -#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 -#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000 - -#define REG_A4XX_CP_PROTECT_CTRL 0x00000250 - -#define REG_A4XX_CP_ST_BASE 0x000004c0 - -#define REG_A4XX_CP_STQ_AVAIL 0x000004ce - -#define REG_A4XX_CP_MERCIU_STAT 0x000004d0 - -#define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 - -#define REG_A4XX_CP_HW_FAULT 0x000004d8 - -#define REG_A4XX_CP_PROTECT_STATUS 0x000004da - -#define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd - -#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 - -#define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501 - -#define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502 - -#define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503 - -#define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504 - -#define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505 - -#define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506 - -#define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507 - -#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b - -static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } - -static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } - -#define REG_A4XX_SP_VS_STATUS 0x00000ec0 - -#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 - -#define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4 - -#define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5 - -#define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6 - -#define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7 - -#define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8 - -#define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9 - -#define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca - -#define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb - -#define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc - -#define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd - -#define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece - -#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf - -#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 -#define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 - -#define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 -#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 -#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 -#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 - -#define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 -#define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; -} -#define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 -#define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 -#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 -#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 -static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) -{ - return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; -} -#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; -} -#define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 -#define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 - -#define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 -#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff -#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 -static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) -{ - return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; -} -#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 -#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 -static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) -{ - return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; -} - -#define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 -#define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff -#define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 -static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) -{ - return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; -} -#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 -#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 -static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) -{ - return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; -} -#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 -#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 -static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) -{ - return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; -} - -static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } - -static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } -#define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff -#define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 -static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) -{ - return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; -} -#define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 -#define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 -static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) -{ - return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; -} -#define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 -#define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 -static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) -{ - return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; -} -#define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 -#define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 -static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) -{ - return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; -} - -static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } - -static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } -#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff -#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) -{ - return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 -#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) -{ - return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 -#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) -{ - return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 -#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) -{ - return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 -#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 -#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 -static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 -#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 -static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; -} - -#define REG_A4XX_SP_VS_OBJ_START 0x000022e1 - -#define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 - -#define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 - -#define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 - -#define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 -#define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; -} -#define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 -#define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 -#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 -#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 -static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) -{ - return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; -} -#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; -} -#define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 -#define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 - -#define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 -#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff -#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 -static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) -{ - return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; -} -#define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 -#define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 -#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 - -#define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea -#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 -#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 -static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 -#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 -static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; -} - -#define REG_A4XX_SP_FS_OBJ_START 0x000022eb - -#define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec - -#define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed - -#define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef - -#define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 -#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f -#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 -static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) -{ - return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; -} -#define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 -#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 -#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 -static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) -{ - return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; -} -#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 -#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 -static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) -{ - return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; -} - -static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } - -static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } -#define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff -#define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 -static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) -{ - return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; -} -#define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 -#define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 -#define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 -static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) -{ - return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; -} -#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000 - -#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 - -#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 - -#define REG_A4XX_SP_CS_OBJ_START 0x00002302 - -#define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 - -#define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 - -#define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 - -#define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 - -#define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d -#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 -#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 -static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 -#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 -static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; -} - -#define REG_A4XX_SP_HS_OBJ_START 0x0000230e - -#define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f - -#define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 - -#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 - -#define REG_A4XX_SP_DS_PARAM_REG 0x0000231a -#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff -#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0 -static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) -{ - return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; -} -#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 -#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 -static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) -{ - return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; -} - -static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } - -static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } -#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff -#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 -static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) -{ - return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; -} -#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00 -#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9 -static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) -{ - return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; -} -#define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000 -#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 -static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) -{ - return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; -} -#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000 -#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25 -static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) -{ - return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; -} - -static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } - -static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } -#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff -#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) -{ - return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 -#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) -{ - return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 -#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) -{ - return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 -#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) -{ - return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 -#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 -#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 -static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 -#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 -static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; -} - -#define REG_A4XX_SP_DS_OBJ_START 0x00002335 - -#define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 - -#define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 - -#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 - -#define REG_A4XX_SP_GS_PARAM_REG 0x00002341 -#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff -#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0 -static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) -{ - return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; -} -#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00 -#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8 -static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) -{ - return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; -} -#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 -#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 -static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) -{ - return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; -} - -static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } - -static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } -#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff -#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 -static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) -{ - return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; -} -#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00 -#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9 -static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) -{ - return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; -} -#define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000 -#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 -static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) -{ - return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; -} -#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000 -#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25 -static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) -{ - return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; -} - -static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } - -static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } -#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff -#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) -{ - return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 -#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) -{ - return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 -#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) -{ - return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 -#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) -{ - return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b -#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 -#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 -static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 -#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 -static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; -} - -#define REG_A4XX_SP_GS_OBJ_START 0x0000235c - -#define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d - -#define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e - -#define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 - -#define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 - -#define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 - -#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 - -#define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65 - -#define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66 - -#define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67 - -#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 - -#define REG_A4XX_VPC_ATTR 0x00002140 -#define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff -#define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 -static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) -{ - return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; -} -#define A4XX_VPC_ATTR_PSIZE 0x00000200 -#define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 -#define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 -static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) -{ - return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; -} -#define A4XX_VPC_ATTR_ENABLE 0x02000000 - -#define REG_A4XX_VPC_PACK 0x00002141 -#define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff -#define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 -static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) -{ - return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; -} -#define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 -#define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 -static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) -{ - return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; -} -#define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 -#define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 -static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) -{ - return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; -} - -static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } - -static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } - -static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } - -static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } - -#define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e - -#define REG_A4XX_VSC_BIN_SIZE 0x00000c00 -#define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f -#define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 -static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; -} -#define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 -#define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 -static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; -} - -#define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 - -#define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 - -#define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 - -static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } - -static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } -#define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff -#define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 -static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) -{ - return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; -} -#define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 -#define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 -static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) -{ - return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; -} -#define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 -#define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 -static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) -{ - return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; -} -#define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 -#define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 -static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) -{ - return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; -} - -static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } - -static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } - -static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } - -static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } - -#define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 - -#define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 - -#define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 - -#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 - -#define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43 - -#define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44 - -#define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45 - -#define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46 - -#define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47 - -#define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48 - -#define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49 - -#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a - -#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 - -#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 - -#define REG_A4XX_VFD_CONTROL_0 0x00002200 -#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff -#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 -static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; -} -#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 -#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 -static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; -} -#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 -#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 -static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; -} -#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 -#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 -static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; -} - -#define REG_A4XX_VFD_CONTROL_1 0x00002201 -#define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff -#define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 -static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; -} -#define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 -#define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 -static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; -} -#define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 -#define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 -static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; -} - -#define REG_A4XX_VFD_CONTROL_2 0x00002202 - -#define REG_A4XX_VFD_CONTROL_3 0x00002203 -#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 -#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 -static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; -} -#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 -#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 -static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; -} -#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 -#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 -static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) -{ - return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; -} - -#define REG_A4XX_VFD_CONTROL_4 0x00002204 - -#define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 - -static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } - -static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } -#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f -#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 -static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) -{ - return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; -} -#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 -#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 -static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) -{ - return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; -} -#define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 -#define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 - -static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } - -static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } -#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff -#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0 -static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) -{ - return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; -} - -static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } -#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff -#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 -static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) -{ - return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; -} - -static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } - -static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } -#define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f -#define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 -static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) -{ - return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; -} -#define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 -#define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 -#define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 -static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) -{ - return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; -} -#define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 -#define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 -static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) -{ - return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; -} -#define A4XX_VFD_DECODE_INSTR_INT 0x00100000 -#define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 -#define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 -static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; -} -#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 -#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 -static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) -{ - return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; -} -#define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 -#define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 - -#define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 - -#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 - -#define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04 - -#define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05 - -#define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06 - -#define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07 - -#define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08 - -#define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09 - -#define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a - -#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b - -#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 - -#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 -#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff -#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 -static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) -{ - return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; -} -#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 -#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 -static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) -{ - return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; -} -#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 -#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 -static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) -{ - return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; -} -#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 -#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 -static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) -{ - return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; -} - -#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 - -#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 - -#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a - -#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d - -#define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 - -#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 - -#define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 - -#define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 - -#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 - -#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 - -#define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 - -#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 - -#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89 - -#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a - -#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b - -#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c - -#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d - -#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e - -#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f - -#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 -#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000 -#define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000 -#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 -#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 - -#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 -#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 - -#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 -#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff -#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 -static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) -{ - return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; -} -#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 -#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 -static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) -{ - return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; -} - -#define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 -#define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff -#define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 -static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) -{ - return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; -} - -#define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 -#define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff -#define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 -static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) -{ - return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; -} - -#define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a -#define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff -#define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 -static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) -{ - return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; -} - -#define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b -#define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff -#define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 -static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) -{ - return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; -} - -#define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c -#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff -#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 -static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) -{ - return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; -} - -#define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d -#define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff -#define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 -static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) -{ - return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; -} - -#define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 -#define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff -#define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 -static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) -{ - return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; -} -#define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 -#define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 -static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) -{ - return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; -} - -#define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 -#define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff -#define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 -static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) -{ - return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; -} - -#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 -#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 -#define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008 - -#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 -#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff -#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 -static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) -{ - return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; -} - -#define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 -#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff -#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 -static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) -{ - return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; -} - -#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 -#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff -#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 -static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) -{ - return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; -} - -#define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 -#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 -#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 -static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) -{ - return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; -} - -#define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 -#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 -#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 -#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 -#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 -#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 -static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) -{ - return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; -} -#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 -#define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000 -#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 - -#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b -#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c -#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 -static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) -{ - return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; -} -#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 -#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 -static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; -} -#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 -#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 -#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 -static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; -} - -#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c -#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff -#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 -static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; -} -#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 -#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 -static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; -} - -#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d -#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff -#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 -static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; -} -#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 -#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 -static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; -} - -#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c -#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff -#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 -static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; -} -#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 -#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 -static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; -} - -#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d -#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff -#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 -static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; -} -#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 -#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 -static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; -} - -#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e -#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff -#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 -static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; -} -#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 -#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 -static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; -} - -#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f -#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff -#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 -static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; -} -#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 -#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 -static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) -{ - return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; -} - -#define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 - -#define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 - -#define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 - -#define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 - -#define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a - -#define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b - -#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c - -#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e - -#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f - -#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90 - -#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91 - -#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92 - -#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93 - -#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94 - -#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 - -#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 - -#define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 - -#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 - -#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e - -#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06 - -#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07 - -#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08 - -#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09 - -#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a - -#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b - -#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c - -#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d - -#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 -#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 -#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 -static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; -} -#define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 -#define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 -#define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 -#define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 -#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 -#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 -static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; -} -#define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 -#define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 -#define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 -#define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 - -#define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 -#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 -#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 -static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; -} -#define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 -#define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 -#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 -#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 -static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; -} -#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 -#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 -static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; -} - -#define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 -#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 -#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 -static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; -} -#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc -#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 -static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; -} -#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 -#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 -static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; -} -#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 -#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 -static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; -} - -#define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 -#define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff -#define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 -static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; -} - -#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 - -#define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 -#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff -#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 -static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; -} -#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 -#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 -static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000 -#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 -#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 -#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 -static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; -} -#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 -#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 -static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; -} - -#define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 -#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff -#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 -static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; -} -#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 -#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 -static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000 -#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 -#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 -#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 -static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; -} -#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 -#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 -static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; -} - -#define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 -#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff -#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 -static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; -} -#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 -#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 -static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000 -#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 -#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 -#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 -static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; -} -#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 -#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 -static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; -} - -#define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 -#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff -#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 -static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; -} -#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 -#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 -static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000 -#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 -#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 -#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 -static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; -} -#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 -#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 -static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; -} - -#define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 -#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff -#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 -static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; -} -#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 -#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 -static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000 -#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 -#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 -#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 -static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; -} -#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 -#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 -static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; -} - -#define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca -#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff -#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0 -static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK; -} -#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 -#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 -static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; -} -#define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000 -#define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000 -#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 -#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 -static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK; -} -#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 -#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24 -static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK; -} - -#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd -#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003 -#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0 -static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK; -} -#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc -#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2 -static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK; -} -#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 -#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12 -static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK; -} -#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 -#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22 -static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK; -} - -#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce -#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff -#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0 -static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK; -} - -#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf - -#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 -#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff -#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0 -static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK; -} - -#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 - -#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 -#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff -#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0 -static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK; -} - -#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 - -#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 -#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff -#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0 -static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK; -} -#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000 -#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24 -static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val) -{ - return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK; -} - -#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 - -#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 - -#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 - -#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 - -#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 - -#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da - -#define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db - -#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 -#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 - -#define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08 - -#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c - -#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 - -#define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11 - -#define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12 - -#define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13 - -#define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14 - -#define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15 - -#define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16 - -#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 - -#define REG_A4XX_PC_BIN_BASE 0x000021c0 - -#define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2 -#define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 -#define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 -static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) -{ - return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK; -} -#define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 -#define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22 -static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) -{ - return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK; -} - -#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 -#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f -#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 -static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) -{ - return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; -} -#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 -#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 -#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 - -#define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5 -#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007 -#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0 -static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK; -} -#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038 -#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3 -static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK; -} -#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040 - -#define REG_A4XX_PC_RESTART_INDEX 0x000021c6 - -#define REG_A4XX_PC_GS_PARAM 0x000021e5 -#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff -#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 -static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) -{ - return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; -} -#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 -#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 -static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) -{ - return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; -} -#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 -#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 -static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; -} -#define A4XX_PC_GS_PARAM_LAYER 0x80000000 - -#define REG_A4XX_PC_HS_PARAM 0x000021e7 -#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f -#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 -static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) -{ - return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; -} -#define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 -#define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 -static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) -{ - return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; -} -#define A4XX_PC_HS_PARAM_CW 0x00800000 -#define A4XX_PC_HS_PARAM_CONNECTED 0x01000000 - -#define REG_A4XX_VBIF_VERSION 0x00003000 - -#define REG_A4XX_VBIF_CLKON 0x00003001 -#define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 - -#define REG_A4XX_VBIF_ABIT_SORT 0x0000301c - -#define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d - -#define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a - -#define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c - -#define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d - -#define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 - -#define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 - -#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 - -#define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0 - -#define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1 - -#define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2 - -#define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3 - -#define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0 - -#define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1 - -#define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2 - -#define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3 - -#define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8 - -#define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9 - -#define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da - -#define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db - -#define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0 - -#define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1 - -#define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2 - -#define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3 - -#define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 - -#define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 - -#define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 - -#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 - -#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 - -#define REG_A4XX_UNKNOWN_0D01 0x00000d01 - -#define REG_A4XX_UNKNOWN_0E42 0x00000e42 - -#define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 - -#define REG_A4XX_UNKNOWN_2001 0x00002001 - -#define REG_A4XX_UNKNOWN_209B 0x0000209b - -#define REG_A4XX_UNKNOWN_20EF 0x000020ef - -#define REG_A4XX_UNKNOWN_2152 0x00002152 - -#define REG_A4XX_UNKNOWN_2153 0x00002153 - -#define REG_A4XX_UNKNOWN_2154 0x00002154 - -#define REG_A4XX_UNKNOWN_2155 0x00002155 - -#define REG_A4XX_UNKNOWN_2156 0x00002156 - -#define REG_A4XX_UNKNOWN_2157 0x00002157 - -#define REG_A4XX_UNKNOWN_21C3 0x000021c3 - -#define REG_A4XX_UNKNOWN_21E6 0x000021e6 - -#define REG_A4XX_UNKNOWN_2209 0x00002209 - -#define REG_A4XX_UNKNOWN_22D7 0x000022d7 - -#define REG_A4XX_UNKNOWN_2352 0x00002352 - -#define REG_A4XX_TEX_SAMP_0 0x00000000 -#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 -#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 -#define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 -static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) -{ - return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; -} -#define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 -#define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 -static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) -{ - return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; -} -#define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 -#define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 -static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) -{ - return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; -} -#define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 -#define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 -static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) -{ - return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; -} -#define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 -#define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 -static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) -{ - return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; -} -#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 -#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 -static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) -{ - return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; -} -#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 -#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 -static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) -{ - return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK; -} - -#define REG_A4XX_TEX_SAMP_1 0x00000001 -#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e -#define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 -static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) -{ - return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; -} -#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 -#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 -#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 -#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 -#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 -static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) -{ - return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; -} -#define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 -#define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 -static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) -{ - return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; -} - -#define REG_A4XX_TEX_CONST_0 0x00000000 -#define A4XX_TEX_CONST_0_TILED 0x00000001 -#define A4XX_TEX_CONST_0_SRGB 0x00000004 -#define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 -#define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 -static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) -{ - return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; -} -#define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 -#define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 -static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) -{ - return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; -} -#define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 -#define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 -static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) -{ - return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; -} -#define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 -#define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 -static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) -{ - return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; -} -#define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 -#define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 -static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) -{ - return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; -} -#define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 -#define A4XX_TEX_CONST_0_FMT__SHIFT 22 -static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) -{ - return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; -} -#define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 -#define A4XX_TEX_CONST_0_TYPE__SHIFT 29 -static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) -{ - return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; -} - -#define REG_A4XX_TEX_CONST_1 0x00000001 -#define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff -#define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 -static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) -{ - return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; -} -#define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000 -#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 -static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) -{ - return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; -} - -#define REG_A4XX_TEX_CONST_2 0x00000002 -#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f -#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 -static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) -{ - return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; -} -#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 -#define A4XX_TEX_CONST_2_PITCH__SHIFT 9 -static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) -{ - return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; -} -#define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 -#define A4XX_TEX_CONST_2_SWAP__SHIFT 30 -static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; -} - -#define REG_A4XX_TEX_CONST_3 0x00000003 -#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff -#define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 -static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; -} -#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 -#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 -static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) -{ - return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; -} - -#define REG_A4XX_TEX_CONST_4 0x00000004 -#define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f -#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 -static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; -} -#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 -#define A4XX_TEX_CONST_4_BASE__SHIFT 5 -static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; -} - -#define REG_A4XX_TEX_CONST_5 0x00000005 - -#define REG_A4XX_TEX_CONST_6 0x00000006 - -#define REG_A4XX_TEX_CONST_7 0x00000007 - -#define REG_A4XX_SSBO_0_0 0x00000000 -#define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0 -#define A4XX_SSBO_0_0_BASE__SHIFT 5 -static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK; -} - -#define REG_A4XX_SSBO_0_1 0x00000001 -#define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff -#define A4XX_SSBO_0_1_PITCH__SHIFT 0 -static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val) -{ - return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK; -} - -#define REG_A4XX_SSBO_0_2 0x00000002 -#define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000 -#define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12 -static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK; -} - -#define REG_A4XX_SSBO_0_3 0x00000003 -#define A4XX_SSBO_0_3_CPP__MASK 0x0000003f -#define A4XX_SSBO_0_3_CPP__SHIFT 0 -static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val) -{ - return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK; -} - -#define REG_A4XX_SSBO_1_0 0x00000000 -#define A4XX_SSBO_1_0_CPP__MASK 0x0000001f -#define A4XX_SSBO_1_0_CPP__SHIFT 0 -static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val) -{ - return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK; -} -#define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00 -#define A4XX_SSBO_1_0_FMT__SHIFT 8 -static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val) -{ - return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK; -} -#define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000 -#define A4XX_SSBO_1_0_WIDTH__SHIFT 16 -static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val) -{ - return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK; -} - -#define REG_A4XX_SSBO_1_1 0x00000001 -#define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff -#define A4XX_SSBO_1_1_HEIGHT__SHIFT 0 -static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val) -{ - return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK; -} -#define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000 -#define A4XX_SSBO_1_1_DEPTH__SHIFT 16 -static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val) -{ - return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK; -} - - -#endif /* A4XX_XML */ diff --git a/src/freedreno/registers/a5xx.xml b/src/freedreno/registers/a5xx.xml new file mode 100644 index 00000000000..16b8d2c7bac --- /dev/null +++ b/src/freedreno/registers/a5xx.xml @@ -0,0 +1,2987 @@ +<?xml version="1.0" encoding="UTF-8"?> +<database xmlns="http://nouveau.freedesktop.org/" +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" +xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> +<import file="freedreno_copyright.xml"/> +<import file="adreno/adreno_common.xml"/> +<import file="adreno/adreno_pm4.xml"/> + +<enum name="a5xx_color_fmt"> + <value value="0x02" name="RB5_A8_UNORM"/> + <value value="0x03" name="RB5_R8_UNORM"/> + <value value="0x04" name="RB5_R8_SNORM"/> + <value value="0x05" name="RB5_R8_UINT"/> + <value value="0x06" name="RB5_R8_SINT"/> + <value value="0x08" name="RB5_R4G4B4A4_UNORM"/> + <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/> + <value value="0x0e" name="RB5_R5G6B5_UNORM"/> + <value value="0x0f" name="RB5_R8G8_UNORM"/> + <value value="0x10" name="RB5_R8G8_SNORM"/> + <value value="0x11" name="RB5_R8G8_UINT"/> + <value value="0x12" name="RB5_R8G8_SINT"/> + <value value="0x15" name="RB5_R16_UNORM"/> + <value value="0x16" name="RB5_R16_SNORM"/> + <value value="0x17" name="RB5_R16_FLOAT"/> + <value value="0x18" name="RB5_R16_UINT"/> + <value value="0x19" name="RB5_R16_SINT"/> + <value value="0x30" name="RB5_R8G8B8A8_UNORM"/> + <value value="0x31" name="RB5_R8G8B8_UNORM"/> + <value value="0x32" name="RB5_R8G8B8A8_SNORM"/> + <value value="0x33" name="RB5_R8G8B8A8_UINT"/> + <value value="0x34" name="RB5_R8G8B8A8_SINT"/> + <value value="0x37" name="RB5_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 --> + <value value="0x3a" name="RB5_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI --> + <value value="0x42" name="RB5_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F --> + <value value="0x43" name="RB5_R16G16_UNORM"/> + <value value="0x44" name="RB5_R16G16_SNORM"/> + <value value="0x45" name="RB5_R16G16_FLOAT"/> + <value value="0x46" name="RB5_R16G16_UINT"/> + <value value="0x47" name="RB5_R16G16_SINT"/> + <value value="0x4a" name="RB5_R32_FLOAT"/> + <value value="0x4b" name="RB5_R32_UINT"/> + <value value="0x4c" name="RB5_R32_SINT"/> + <value value="0x60" name="RB5_R16G16B16A16_UNORM"/> + <value value="0x61" name="RB5_R16G16B16A16_SNORM"/> + <value value="0x62" name="RB5_R16G16B16A16_FLOAT"/> + <value value="0x63" name="RB5_R16G16B16A16_UINT"/> + <value value="0x64" name="RB5_R16G16B16A16_SINT"/> + <value value="0x67" name="RB5_R32G32_FLOAT"/> + <value value="0x68" name="RB5_R32G32_UINT"/> + <value value="0x69" name="RB5_R32G32_SINT"/> + <value value="0x82" name="RB5_R32G32B32A32_FLOAT"/> + <value value="0x83" name="RB5_R32G32B32A32_UINT"/> + <value value="0x84" name="RB5_R32G32B32A32_SINT"/> +</enum> + +<enum name="a5xx_tile_mode"> + <value name="TILE5_LINEAR" value="0"/> + <value name="TILE5_2" value="2"/> + <value name="TILE5_3" value="3"/> +</enum> + +<enum name="a5xx_vtx_fmt" prefix="chipset"> + <value value="0x03" name="VFMT5_8_UNORM"/> + <value value="0x04" name="VFMT5_8_SNORM"/> + <value value="0x05" name="VFMT5_8_UINT"/> + <value value="0x06" name="VFMT5_8_SINT"/> + + <value value="0x0f" name="VFMT5_8_8_UNORM"/> + <value value="0x10" name="VFMT5_8_8_SNORM"/> + <value value="0x11" name="VFMT5_8_8_UINT"/> + <value value="0x12" name="VFMT5_8_8_SINT"/> + + <value value="0x15" name="VFMT5_16_UNORM"/> + <value value="0x16" name="VFMT5_16_SNORM"/> + <value value="0x17" name="VFMT5_16_FLOAT"/> + <value value="0x18" name="VFMT5_16_UINT"/> + <value value="0x19" name="VFMT5_16_SINT"/> + + <value value="0x21" name="VFMT5_8_8_8_UNORM"/> + <value value="0x22" name="VFMT5_8_8_8_SNORM"/> + <value value="0x23" name="VFMT5_8_8_8_UINT"/> + <value value="0x24" name="VFMT5_8_8_8_SINT"/> + + <value value="0x30" name="VFMT5_8_8_8_8_UNORM"/> + <value value="0x32" name="VFMT5_8_8_8_8_SNORM"/> + <value value="0x33" name="VFMT5_8_8_8_8_UINT"/> + <value value="0x34" name="VFMT5_8_8_8_8_SINT"/> + + <value value="0x36" name="VFMT5_10_10_10_2_UNORM"/> + <value value="0x39" name="VFMT5_10_10_10_2_SNORM"/> + <value value="0x3a" name="VFMT5_10_10_10_2_UINT"/> + <value value="0x3b" name="VFMT5_10_10_10_2_SINT"/> + + <value value="0x42" name="VFMT5_11_11_10_FLOAT"/> + + <value value="0x43" name="VFMT5_16_16_UNORM"/> + <value value="0x44" name="VFMT5_16_16_SNORM"/> + <value value="0x45" name="VFMT5_16_16_FLOAT"/> + <value value="0x46" name="VFMT5_16_16_UINT"/> + <value value="0x47" name="VFMT5_16_16_SINT"/> + + <value value="0x48" name="VFMT5_32_UNORM"/> + <value value="0x49" name="VFMT5_32_SNORM"/> + <value value="0x4a" name="VFMT5_32_FLOAT"/> + <value value="0x4b" name="VFMT5_32_UINT"/> + <value value="0x4c" name="VFMT5_32_SINT"/> + <value value="0x4d" name="VFMT5_32_FIXED"/> + + <value value="0x58" name="VFMT5_16_16_16_UNORM"/> + <value value="0x59" name="VFMT5_16_16_16_SNORM"/> + <value value="0x5a" name="VFMT5_16_16_16_FLOAT"/> + <value value="0x5b" name="VFMT5_16_16_16_UINT"/> + <value value="0x5c" name="VFMT5_16_16_16_SINT"/> + + <value value="0x60" name="VFMT5_16_16_16_16_UNORM"/> + <value value="0x61" name="VFMT5_16_16_16_16_SNORM"/> + <value value="0x62" name="VFMT5_16_16_16_16_FLOAT"/> + <value value="0x63" name="VFMT5_16_16_16_16_UINT"/> + <value value="0x64" name="VFMT5_16_16_16_16_SINT"/> + + <value value="0x65" name="VFMT5_32_32_UNORM"/> + <value value="0x66" name="VFMT5_32_32_SNORM"/> + <value value="0x67" name="VFMT5_32_32_FLOAT"/> + <value value="0x68" name="VFMT5_32_32_UINT"/> + <value value="0x69" name="VFMT5_32_32_SINT"/> + <value value="0x6a" name="VFMT5_32_32_FIXED"/> + + <value value="0x70" name="VFMT5_32_32_32_UNORM"/> + <value value="0x71" name="VFMT5_32_32_32_SNORM"/> + <value value="0x72" name="VFMT5_32_32_32_UINT"/> + <value value="0x73" name="VFMT5_32_32_32_SINT"/> + <value value="0x74" name="VFMT5_32_32_32_FLOAT"/> + <value value="0x75" name="VFMT5_32_32_32_FIXED"/> + + <value value="0x80" name="VFMT5_32_32_32_32_UNORM"/> + <value value="0x81" name="VFMT5_32_32_32_32_SNORM"/> + <value value="0x82" name="VFMT5_32_32_32_32_FLOAT"/> + <value value="0x83" name="VFMT5_32_32_32_32_UINT"/> + <value value="0x84" name="VFMT5_32_32_32_32_SINT"/> + <value value="0x85" name="VFMT5_32_32_32_32_FIXED"/> +</enum> + +<enum name="a5xx_tex_fmt"> + <value value="0x02" name="TFMT5_A8_UNORM"/> + <value value="0x03" name="TFMT5_8_UNORM"/> + <value value="0x04" name="TFMT5_8_SNORM"/> + <value value="0x05" name="TFMT5_8_UINT"/> + <value value="0x06" name="TFMT5_8_SINT"/> + <value value="0x08" name="TFMT5_4_4_4_4_UNORM"/> + <value value="0x0a" name="TFMT5_5_5_5_1_UNORM"/> + <value value="0x0e" name="TFMT5_5_6_5_UNORM"/> + <value value="0x0f" name="TFMT5_8_8_UNORM"/> + <value value="0x10" name="TFMT5_8_8_SNORM"/> + <value value="0x11" name="TFMT5_8_8_UINT"/> + <value value="0x12" name="TFMT5_8_8_SINT"/> + <value value="0x13" name="TFMT5_L8_A8_UNORM"/> + <value value="0x15" name="TFMT5_16_UNORM"/> + <value value="0x16" name="TFMT5_16_SNORM"/> + <value value="0x17" name="TFMT5_16_FLOAT"/> + <value value="0x18" name="TFMT5_16_UINT"/> + <value value="0x19" name="TFMT5_16_SINT"/> + <value value="0x30" name="TFMT5_8_8_8_8_UNORM"/> + <value value="0x31" name="TFMT5_8_8_8_UNORM"/> + <value value="0x32" name="TFMT5_8_8_8_8_SNORM"/> + <value value="0x33" name="TFMT5_8_8_8_8_UINT"/> + <value value="0x34" name="TFMT5_8_8_8_8_SINT"/> + <value value="0x35" name="TFMT5_9_9_9_E5_FLOAT"/> + <value value="0x36" name="TFMT5_10_10_10_2_UNORM"/> + <value value="0x3a" name="TFMT5_10_10_10_2_UINT"/> + <value value="0x42" name="TFMT5_11_11_10_FLOAT"/> + <value value="0x43" name="TFMT5_16_16_UNORM"/> + <value value="0x44" name="TFMT5_16_16_SNORM"/> + <value value="0x45" name="TFMT5_16_16_FLOAT"/> + <value value="0x46" name="TFMT5_16_16_UINT"/> + <value value="0x47" name="TFMT5_16_16_SINT"/> + <value value="0x4a" name="TFMT5_32_FLOAT"/> + <value value="0x4b" name="TFMT5_32_UINT"/> + <value value="0x4c" name="TFMT5_32_SINT"/> + <value value="0x60" name="TFMT5_16_16_16_16_UNORM"/> + <value value="0x61" name="TFMT5_16_16_16_16_SNORM"/> + <value value="0x62" name="TFMT5_16_16_16_16_FLOAT"/> + <value value="0x63" name="TFMT5_16_16_16_16_UINT"/> + <value value="0x64" name="TFMT5_16_16_16_16_SINT"/> + <value value="0x67" name="TFMT5_32_32_FLOAT"/> + <value value="0x68" name="TFMT5_32_32_UINT"/> + <value value="0x69" name="TFMT5_32_32_SINT"/> + <value value="0x72" name="TFMT5_32_32_32_UINT"/> + <value value="0x73" name="TFMT5_32_32_32_SINT"/> + <value value="0x74" name="TFMT5_32_32_32_FLOAT"/> + <value value="0x82" name="TFMT5_32_32_32_32_FLOAT"/> + <value value="0x83" name="TFMT5_32_32_32_32_UINT"/> + <value value="0x84" name="TFMT5_32_32_32_32_SINT"/> + <value value="0xa0" name="TFMT5_X8Z24_UNORM"/> + + <value value="0xab" name="TFMT5_ETC2_RG11_UNORM"/> + <value value="0xac" name="TFMT5_ETC2_RG11_SNORM"/> + <value value="0xad" name="TFMT5_ETC2_R11_UNORM"/> + <value value="0xae" name="TFMT5_ETC2_R11_SNORM"/> + <value value="0xaf" name="TFMT5_ETC1"/> + <value value="0xb0" name="TFMT5_ETC2_RGB8"/> + <value value="0xb1" name="TFMT5_ETC2_RGBA8"/> + <value value="0xb2" name="TFMT5_ETC2_RGB8A1"/> + <value value="0xb3" name="TFMT5_DXT1"/> + <value value="0xb4" name="TFMT5_DXT3"/> + <value value="0xb5" name="TFMT5_DXT5"/> + <value value="0xb7" name="TFMT5_RGTC1_UNORM"/> + <value value="0xb8" name="TFMT5_RGTC1_SNORM"/> + <value value="0xbb" name="TFMT5_RGTC2_UNORM"/> + <value value="0xbc" name="TFMT5_RGTC2_SNORM"/> + <value value="0xbe" name="TFMT5_BPTC_UFLOAT"/> + <value value="0xbf" name="TFMT5_BPTC_FLOAT"/> + <value value="0xc0" name="TFMT5_BPTC"/> + <value value="0xc1" name="TFMT5_ASTC_4x4"/> + <value value="0xc2" name="TFMT5_ASTC_5x4"/> + <value value="0xc3" name="TFMT5_ASTC_5x5"/> + <value value="0xc4" name="TFMT5_ASTC_6x5"/> + <value value="0xc5" name="TFMT5_ASTC_6x6"/> + <value value="0xc6" name="TFMT5_ASTC_8x5"/> + <value value="0xc7" name="TFMT5_ASTC_8x6"/> + <value value="0xc8" name="TFMT5_ASTC_8x8"/> + <value value="0xc9" name="TFMT5_ASTC_10x5"/> + <value value="0xca" name="TFMT5_ASTC_10x6"/> + <value value="0xcb" name="TFMT5_ASTC_10x8"/> + <value value="0xcc" name="TFMT5_ASTC_10x10"/> + <value value="0xcd" name="TFMT5_ASTC_12x10"/> + <value value="0xce" name="TFMT5_ASTC_12x12"/> +</enum> + +<enum name="a5xx_tex_fetchsize"> + <doc> + Size pixel to fetch, in bytes. Doesn't seem to be required, setting + it to 0x0 seems to work ok, but may be less optimal. + </doc> + <value name="TFETCH5_1_BYTE" value="0"/> + <value name="TFETCH5_2_BYTE" value="1"/> + <value name="TFETCH5_4_BYTE" value="2"/> + <value name="TFETCH5_8_BYTE" value="3"/> + <value name="TFETCH5_16_BYTE" value="4"/> +</enum> + +<enum name="a5xx_depth_format"> + <value name="DEPTH5_NONE" value="0"/> + <value name="DEPTH5_16" value="1"/> + <value name="DEPTH5_24_8" value="2"/> + <value name="DEPTH5_32" value="4"/> +</enum> + +<enum name="a5xx_blit_buf"> + <value value="0" name="BLIT_MRT0"/> + <value value="1" name="BLIT_MRT1"/> + <value value="2" name="BLIT_MRT2"/> + <value value="3" name="BLIT_MRT3"/> + <value value="4" name="BLIT_MRT4"/> + <value value="5" name="BLIT_MRT5"/> + <value value="6" name="BLIT_MRT6"/> + <value value="7" name="BLIT_MRT7"/> + <value value="8" name="BLIT_ZS"/> <!-- depth or combined depth+stencil --> + <value value="9" name="BLIT_S"/> <!-- separate stencil --> +</enum> + +<!-- see comment in a4xx.xml about script to extract countables from test-perf output --> +<enum name="a5xx_cp_perfcounter_select"> + <value value="0" name="PERF_CP_ALWAYS_COUNT"/> + <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> + <value value="2" name="PERF_CP_BUSY_CYCLES"/> + <value value="3" name="PERF_CP_PFP_IDLE"/> + <value value="4" name="PERF_CP_PFP_BUSY_WORKING"/> + <value value="5" name="PERF_CP_PFP_STALL_CYCLES_ANY"/> + <value value="6" name="PERF_CP_PFP_STARVE_CYCLES_ANY"/> + <value value="7" name="PERF_CP_PFP_ICACHE_MISS"/> + <value value="8" name="PERF_CP_PFP_ICACHE_HIT"/> + <value value="9" name="PERF_CP_PFP_MATCH_PM4_PKT_PROFILE"/> + <value value="10" name="PERF_CP_ME_BUSY_WORKING"/> + <value value="11" name="PERF_CP_ME_IDLE"/> + <value value="12" name="PERF_CP_ME_STARVE_CYCLES_ANY"/> + <value value="13" name="PERF_CP_ME_FIFO_EMPTY_PFP_IDLE"/> + <value value="14" name="PERF_CP_ME_FIFO_EMPTY_PFP_BUSY"/> + <value value="15" name="PERF_CP_ME_FIFO_FULL_ME_BUSY"/> + <value value="16" name="PERF_CP_ME_FIFO_FULL_ME_NON_WORKING"/> + <value value="17" name="PERF_CP_ME_STALL_CYCLES_ANY"/> + <value value="18" name="PERF_CP_ME_ICACHE_MISS"/> + <value value="19" name="PERF_CP_ME_ICACHE_HIT"/> + <value value="20" name="PERF_CP_NUM_PREEMPTIONS"/> + <value value="21" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> + <value value="22" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> + <value value="23" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> + <value value="24" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> + <value value="25" name="PERF_CP_PREDICATED_DRAWS_KILLED"/> + <value value="26" name="PERF_CP_MODE_SWITCH"/> + <value value="27" name="PERF_CP_ZPASS_DONE"/> + <value value="28" name="PERF_CP_CONTEXT_DONE"/> + <value value="29" name="PERF_CP_CACHE_FLUSH"/> + <value value="30" name="PERF_CP_LONG_PREEMPTIONS"/> +</enum> + +<enum name="a5xx_rbbm_perfcounter_select"> + <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/> + <value value="1" name="PERF_RBBM_ALWAYS_ON"/> + <value value="2" name="PERF_RBBM_TSE_BUSY"/> + <value value="3" name="PERF_RBBM_RAS_BUSY"/> + <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/> + <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/> + <value value="6" name="PERF_RBBM_STATUS_MASKED"/> + <value value="7" name="PERF_RBBM_COM_BUSY"/> + <value value="8" name="PERF_RBBM_DCOM_BUSY"/> + <value value="9" name="PERF_RBBM_VBIF_BUSY"/> + <value value="10" name="PERF_RBBM_VSC_BUSY"/> + <value value="11" name="PERF_RBBM_TESS_BUSY"/> + <value value="12" name="PERF_RBBM_UCHE_BUSY"/> + <value value="13" name="PERF_RBBM_HLSQ_BUSY"/> +</enum> + +<enum name="a5xx_pc_perfcounter_select"> + <value value="0" name="PERF_PC_BUSY_CYCLES"/> + <value value="1" name="PERF_PC_WORKING_CYCLES"/> + <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/> + <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/> + <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/> + <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/> + <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/> + <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/> + <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/> + <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/> + <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/> + <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> + <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> + <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/> + <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/> + <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/> + <value value="16" name="PERF_PC_INSTANCES"/> + <value value="17" name="PERF_PC_VPC_PRIMITIVES"/> + <value value="18" name="PERF_PC_DEAD_PRIM"/> + <value value="19" name="PERF_PC_LIVE_PRIM"/> + <value value="20" name="PERF_PC_VERTEX_HITS"/> + <value value="21" name="PERF_PC_IA_VERTICES"/> + <value value="22" name="PERF_PC_IA_PRIMITIVES"/> + <value value="23" name="PERF_PC_GS_PRIMITIVES"/> + <value value="24" name="PERF_PC_HS_INVOCATIONS"/> + <value value="25" name="PERF_PC_DS_INVOCATIONS"/> + <value value="26" name="PERF_PC_VS_INVOCATIONS"/> + <value value="27" name="PERF_PC_GS_INVOCATIONS"/> + <value value="28" name="PERF_PC_DS_PRIMITIVES"/> + <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/> + <value value="30" name="PERF_PC_3D_DRAWCALLS"/> + <value value="31" name="PERF_PC_2D_DRAWCALLS"/> + <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> + <value value="33" name="PERF_TESS_BUSY_CYCLES"/> + <value value="34" name="PERF_TESS_WORKING_CYCLES"/> + <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/> + <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/> +</enum> + +<enum name="a5xx_vfd_perfcounter_select"> + <value value="0" name="PERF_VFD_BUSY_CYCLES"/> + <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/> + <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> + <value value="3" name="PERF_VFD_STALL_CYCLES_MISS_VB"/> + <value value="4" name="PERF_VFD_STALL_CYCLES_MISS_Q"/> + <value value="5" name="PERF_VFD_STALL_CYCLES_SP_INFO"/> + <value value="6" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/> + <value value="7" name="PERF_VFD_STALL_CYCLES_VFDP_VB"/> + <value value="8" name="PERF_VFD_STALL_CYCLES_VFDP_Q"/> + <value value="9" name="PERF_VFD_DECODER_PACKER_STALL"/> + <value value="10" name="PERF_VFD_STARVE_CYCLES_UCHE"/> + <value value="11" name="PERF_VFD_RBUFFER_FULL"/> + <value value="12" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/> + <value value="13" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> + <value value="14" name="PERF_VFD_NUM_ATTRIBUTES"/> + <value value="15" name="PERF_VFD_INSTRUCTIONS"/> + <value value="16" name="PERF_VFD_UPPER_SHADER_FIBERS"/> + <value value="17" name="PERF_VFD_LOWER_SHADER_FIBERS"/> + <value value="18" name="PERF_VFD_MODE_0_FIBERS"/> + <value value="19" name="PERF_VFD_MODE_1_FIBERS"/> + <value value="20" name="PERF_VFD_MODE_2_FIBERS"/> + <value value="21" name="PERF_VFD_MODE_3_FIBERS"/> + <value value="22" name="PERF_VFD_MODE_4_FIBERS"/> + <value value="23" name="PERF_VFD_TOTAL_VERTICES"/> + <value value="24" name="PERF_VFD_NUM_ATTR_MISS"/> + <value value="25" name="PERF_VFD_1_BURST_REQ"/> + <value value="26" name="PERF_VFDP_STALL_CYCLES_VFD"/> + <value value="27" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> + <value value="28" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/> + <value value="29" name="PERF_VFDP_STARVE_CYCLES_PC"/> + <value value="30" name="PERF_VFDP_VS_STAGE_32_WAVES"/> +</enum> + +<enum name="a5xx_hlsq_perfcounter_select"> + <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/> + <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/> + <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/> + <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> + <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/> + <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/> + <value value="6" name="PERF_HLSQ_FS_STAGE_32_WAVES"/> + <value value="7" name="PERF_HLSQ_FS_STAGE_64_WAVES"/> + <value value="8" name="PERF_HLSQ_QUADS"/> + <value value="9" name="PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE"/> + <value value="10" name="PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE"/> + <value value="11" name="PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE"/> + <value value="12" name="PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE"/> + <value value="13" name="PERF_HLSQ_CS_INVOCATIONS"/> + <value value="14" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/> +</enum> + +<enum name="a5xx_vpc_perfcounter_select"> + <value value="0" name="PERF_VPC_BUSY_CYCLES"/> + <value value="1" name="PERF_VPC_WORKING_CYCLES"/> + <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/> + <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/> + <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> + <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/> + <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/> + <value value="7" name="PERF_VPC_POS_EXPORT_STALL_CYCLES"/> + <value value="8" name="PERF_VPC_STARVE_CYCLES_SP"/> + <value value="9" name="PERF_VPC_STARVE_CYCLES_LRZ"/> + <value value="10" name="PERF_VPC_PC_PRIMITIVES"/> + <value value="11" name="PERF_VPC_SP_COMPONENTS"/> + <value value="12" name="PERF_VPC_SP_LM_PRIMITIVES"/> + <value value="13" name="PERF_VPC_SP_LM_COMPONENTS"/> + <value value="14" name="PERF_VPC_SP_LM_DWORDS"/> + <value value="15" name="PERF_VPC_STREAMOUT_COMPONENTS"/> + <value value="16" name="PERF_VPC_GRANT_PHASES"/> +</enum> + +<enum name="a5xx_tse_perfcounter_select"> + <value value="0" name="PERF_TSE_BUSY_CYCLES"/> + <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/> + <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/> + <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> + <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> + <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/> + <value value="6" name="PERF_TSE_INPUT_PRIM"/> + <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/> + <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/> + <value value="9" name="PERF_TSE_CLIPPED_PRIM"/> + <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/> + <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/> + <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/> + <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/> + <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/> + <value value="15" name="PERF_TSE_CINVOCATION"/> + <value value="16" name="PERF_TSE_CPRIMITIVES"/> + <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/> + <value value="18" name="PERF_TSE_2D_ALIVE_CLCLES"/> +</enum> + +<enum name="a5xx_ras_perfcounter_select"> + <value value="0" name="PERF_RAS_BUSY_CYCLES"/> + <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> + <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/> + <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/> + <value value="4" name="PERF_RAS_SUPER_TILES"/> + <value value="5" name="PERF_RAS_8X4_TILES"/> + <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/> + <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/> + <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/> + <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/> +</enum> + +<enum name="a5xx_lrz_perfcounter_select"> + <value value="0" name="PERF_LRZ_BUSY_CYCLES"/> + <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/> + <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/> + <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/> + <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/> + <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> + <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/> + <value value="7" name="PERF_LRZ_LRZ_READ"/> + <value value="8" name="PERF_LRZ_LRZ_WRITE"/> + <value value="9" name="PERF_LRZ_READ_LATENCY"/> + <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/> + <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> + <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/> + <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> + <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/> + <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/> + <value value="16" name="PERF_LRZ_TILE_KILLED"/> + <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/> + <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> +</enum> + +<enum name="a5xx_uche_perfcounter_select"> + <value value="0" name="PERF_UCHE_BUSY_CYCLES"/> + <value value="1" name="PERF_UCHE_STALL_CYCLES_VBIF"/> + <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/> + <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/> + <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/> + <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/> + <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> + <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/> + <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/> + <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/> + <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/> + <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/> + <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/> + <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/> + <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/> + <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/> + <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/> + <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/> + <value value="18" name="PERF_UCHE_EVICTS"/> + <value value="19" name="PERF_UCHE_BANK_REQ0"/> + <value value="20" name="PERF_UCHE_BANK_REQ1"/> + <value value="21" name="PERF_UCHE_BANK_REQ2"/> + <value value="22" name="PERF_UCHE_BANK_REQ3"/> + <value value="23" name="PERF_UCHE_BANK_REQ4"/> + <value value="24" name="PERF_UCHE_BANK_REQ5"/> + <value value="25" name="PERF_UCHE_BANK_REQ6"/> + <value value="26" name="PERF_UCHE_BANK_REQ7"/> + <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/> + <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/> + <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/> + <value value="30" name="PERF_UCHE_FLAG_COUNT"/> +</enum> + +<enum name="a5xx_tp_perfcounter_select"> + <value value="0" name="PERF_TP_BUSY_CYCLES"/> + <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/> + <value value="2" name="PERF_TP_LATENCY_CYCLES"/> + <value value="3" name="PERF_TP_LATENCY_TRANS"/> + <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/> + <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/> + <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/> + <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/> + <value value="8" name="PERF_TP_SP_TP_TRANS"/> + <value value="9" name="PERF_TP_TP_SP_TRANS"/> + <value value="10" name="PERF_TP_OUTPUT_PIXELS"/> + <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/> + <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/> + <value value="13" name="PERF_TP_QUADS_RECEIVED"/> + <value value="14" name="PERF_TP_QUADS_OFFSET"/> + <value value="15" name="PERF_TP_QUADS_SHADOW"/> + <value value="16" name="PERF_TP_QUADS_ARRAY"/> + <value value="17" name="PERF_TP_QUADS_GRADIENT"/> + <value value="18" name="PERF_TP_QUADS_1D"/> + <value value="19" name="PERF_TP_QUADS_2D"/> + <value value="20" name="PERF_TP_QUADS_BUFFER"/> + <value value="21" name="PERF_TP_QUADS_3D"/> + <value value="22" name="PERF_TP_QUADS_CUBE"/> + <value value="23" name="PERF_TP_STATE_CACHE_REQUESTS"/> + <value value="24" name="PERF_TP_STATE_CACHE_MISSES"/> + <value value="25" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/> + <value value="26" name="PERF_TP_BINDLESS_STATE_CACHE_REQUESTS"/> + <value value="27" name="PERF_TP_BINDLESS_STATE_CACHE_MISSES"/> + <value value="28" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/> + <value value="29" name="PERF_TP_OUTPUT_PIXELS_POINT"/> + <value value="30" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/> + <value value="31" name="PERF_TP_OUTPUT_PIXELS_MIP"/> + <value value="32" name="PERF_TP_OUTPUT_PIXELS_ANISO"/> + <value value="33" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> + <value value="34" name="PERF_TP_FLAG_CACHE_REQUESTS"/> + <value value="35" name="PERF_TP_FLAG_CACHE_MISSES"/> + <value value="36" name="PERF_TP_L1_5_L2_REQUESTS"/> + <value value="37" name="PERF_TP_2D_OUTPUT_PIXELS"/> + <value value="38" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/> + <value value="39" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> + <value value="40" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> + <value value="41" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> +</enum> + +<enum name="a5xx_sp_perfcounter_select"> + <value value="0" name="PERF_SP_BUSY_CYCLES"/> + <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/> + <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/> + <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/> + <value value="4" name="PERF_SP_STALL_CYCLES_TP"/> + <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/> + <value value="6" name="PERF_SP_STALL_CYCLES_RB"/> + <value value="7" name="PERF_SP_SCHEDULER_NON_WORKING"/> + <value value="8" name="PERF_SP_WAVE_CONTEXTS"/> + <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/> + <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/> + <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/> + <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/> + <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/> + <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/> + <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/> + <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/> + <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/> + <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/> + <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/> + <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/> + <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/> + <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/> + <value value="23" name="PERF_SP_WAVE_END_CYCLES"/> + <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/> + <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> + <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/> + <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/> + <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/> + <value value="29" name="PERF_SP_LM_ATOMICS"/> + <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/> + <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/> + <value value="32" name="PERF_SP_GM_ATOMICS"/> + <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> + <value value="34" name="PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS"/> + <value value="35" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> + <value value="36" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> + <value value="37" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> + <value value="38" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> + <value value="39" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> + <value value="40" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> + <value value="41" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> + <value value="42" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> + <value value="43" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> + <value value="44" name="PERF_SP_VS_INSTRUCTIONS"/> + <value value="45" name="PERF_SP_FS_INSTRUCTIONS"/> + <value value="46" name="PERF_SP_ADDR_LOCK_COUNT"/> + <value value="47" name="PERF_SP_UCHE_READ_TRANS"/> + <value value="48" name="PERF_SP_UCHE_WRITE_TRANS"/> + <value value="49" name="PERF_SP_EXPORT_VPC_TRANS"/> + <value value="50" name="PERF_SP_EXPORT_RB_TRANS"/> + <value value="51" name="PERF_SP_PIXELS_KILLED"/> + <value value="52" name="PERF_SP_ICL1_REQUESTS"/> + <value value="53" name="PERF_SP_ICL1_MISSES"/> + <value value="54" name="PERF_SP_ICL0_REQUESTS"/> + <value value="55" name="PERF_SP_ICL0_MISSES"/> + <value value="56" name="PERF_SP_HS_INSTRUCTIONS"/> + <value value="57" name="PERF_SP_DS_INSTRUCTIONS"/> + <value value="58" name="PERF_SP_GS_INSTRUCTIONS"/> + <value value="59" name="PERF_SP_CS_INSTRUCTIONS"/> + <value value="60" name="PERF_SP_GPR_READ"/> + <value value="61" name="PERF_SP_GPR_WRITE"/> + <value value="62" name="PERF_SP_LM_CH0_REQUESTS"/> + <value value="63" name="PERF_SP_LM_CH1_REQUESTS"/> + <value value="64" name="PERF_SP_LM_BANK_CONFLICTS"/> +</enum> + +<enum name="a5xx_rb_perfcounter_select"> + <value value="0" name="PERF_RB_BUSY_CYCLES"/> + <value value="1" name="PERF_RB_STALL_CYCLES_CCU"/> + <value value="2" name="PERF_RB_STALL_CYCLES_HLSQ"/> + <value value="3" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/> + <value value="4" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/> + <value value="5" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/> + <value value="6" name="PERF_RB_STARVE_CYCLES_SP"/> + <value value="7" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/> + <value value="8" name="PERF_RB_STARVE_CYCLES_CCU"/> + <value value="9" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/> + <value value="10" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/> + <value value="11" name="PERF_RB_Z_WORKLOAD"/> + <value value="12" name="PERF_RB_HLSQ_ACTIVE"/> + <value value="13" name="PERF_RB_Z_READ"/> + <value value="14" name="PERF_RB_Z_WRITE"/> + <value value="15" name="PERF_RB_C_READ"/> + <value value="16" name="PERF_RB_C_WRITE"/> + <value value="17" name="PERF_RB_TOTAL_PASS"/> + <value value="18" name="PERF_RB_Z_PASS"/> + <value value="19" name="PERF_RB_Z_FAIL"/> + <value value="20" name="PERF_RB_S_FAIL"/> + <value value="21" name="PERF_RB_BLENDED_FXP_COMPONENTS"/> + <value value="22" name="PERF_RB_BLENDED_FP16_COMPONENTS"/> + <value value="23" name="RB_RESERVED"/> + <value value="24" name="PERF_RB_2D_ALIVE_CYCLES"/> + <value value="25" name="PERF_RB_2D_STALL_CYCLES_A2D"/> + <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SRC"/> + <value value="27" name="PERF_RB_2D_STARVE_CYCLES_SP"/> + <value value="28" name="PERF_RB_2D_STARVE_CYCLES_DST"/> + <value value="29" name="PERF_RB_2D_VALID_PIXELS"/> +</enum> + +<enum name="a5xx_rb_samples_perfcounter_select"> + <value value="0" name="TOTAL_SAMPLES"/> + <value value="1" name="ZPASS_SAMPLES"/> + <value value="2" name="ZFAIL_SAMPLES"/> + <value value="3" name="SFAIL_SAMPLES"/> +</enum> + +<enum name="a5xx_vsc_perfcounter_select"> + <value value="0" name="PERF_VSC_BUSY_CYCLES"/> + <value value="1" name="PERF_VSC_WORKING_CYCLES"/> + <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/> + <value value="3" name="PERF_VSC_EOT_NUM"/> +</enum> + +<enum name="a5xx_ccu_perfcounter_select"> + <value value="0" name="PERF_CCU_BUSY_CYCLES"/> + <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> + <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> + <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/> + <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/> + <value value="5" name="PERF_CCU_COLOR_BLOCKS"/> + <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/> + <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/> + <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/> + <value value="9" name="PERF_CCU_GMEM_READ"/> + <value value="10" name="PERF_CCU_GMEM_WRITE"/> + <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/> + <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/> + <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/> + <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/> + <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/> + <value value="16" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/> + <value value="17" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/> + <value value="18" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/> + <value value="19" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/> + <value value="20" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/> + <value value="21" name="PERF_CCU_2D_BUSY_CYCLES"/> + <value value="22" name="PERF_CCU_2D_RD_REQ"/> + <value value="23" name="PERF_CCU_2D_WR_REQ"/> + <value value="24" name="PERF_CCU_2D_REORDER_STARVE_CYCLES"/> + <value value="25" name="PERF_CCU_2D_PIXELS"/> +</enum> + +<enum name="a5xx_cmp_perfcounter_select"> + <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_VBIF"/> + <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> + <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> + <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> + <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> + <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/> + <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> + <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/> + <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/> + <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/> + <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/> + <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> + <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> + <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> + <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> + <value value="15" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> + <value value="16" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> + <value value="17" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> + <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> + <value value="19" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/> + <value value="20" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/> + <value value="21" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/> + <value value="22" name="PERF_CMPDECMP_2D_RD_DATA"/> + <value value="23" name="PERF_CMPDECMP_2D_WR_DATA"/> +</enum> + +<enum name="a5xx_vbif_perfcounter_select"> + <value value="0" name="AXI_READ_REQUESTS_ID_0"/> + <value value="1" name="AXI_READ_REQUESTS_ID_1"/> + <value value="2" name="AXI_READ_REQUESTS_ID_2"/> + <value value="3" name="AXI_READ_REQUESTS_ID_3"/> + <value value="4" name="AXI_READ_REQUESTS_ID_4"/> + <value value="5" name="AXI_READ_REQUESTS_ID_5"/> + <value value="6" name="AXI_READ_REQUESTS_ID_6"/> + <value value="7" name="AXI_READ_REQUESTS_ID_7"/> + <value value="8" name="AXI_READ_REQUESTS_ID_8"/> + <value value="9" name="AXI_READ_REQUESTS_ID_9"/> + <value value="10" name="AXI_READ_REQUESTS_ID_10"/> + <value value="11" name="AXI_READ_REQUESTS_ID_11"/> + <value value="12" name="AXI_READ_REQUESTS_ID_12"/> + <value value="13" name="AXI_READ_REQUESTS_ID_13"/> + <value value="14" name="AXI_READ_REQUESTS_ID_14"/> + <value value="15" name="AXI_READ_REQUESTS_ID_15"/> + <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/> + <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/> + <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/> + <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/> + <value value="20" name="AXI_READ_REQUESTS_TOTAL"/> + <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/> + <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/> + <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/> + <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/> + <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/> + <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/> + <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/> + <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/> + <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/> + <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/> + <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/> + <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/> + <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/> + <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/> + <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/> + <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/> + <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/> + <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/> + <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/> + <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/> + <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/> + <value value="42" name="AXI_TOTAL_REQUESTS"/> + <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/> + <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/> + <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/> + <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/> + <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/> + <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/> + <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/> + <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/> + <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/> + <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/> + <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/> + <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/> + <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/> + <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/> + <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/> + <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/> + <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/> + <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/> + <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/> + <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/> + <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/> + <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/> + <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/> + <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/> + <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/> + <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/> + <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/> + <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/> + <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/> + <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/> + <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/> + <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/> + <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/> + <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/> + <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/> + <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/> + <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/> + <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/> + <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/> + <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/> + <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/> + <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/> + <value value="85" name="AXI_DATA_BEATS_TOTAL"/> +</enum> + +<domain name="A5XX" width="32"> + <bitset name="A5XX_INT0"> + <bitfield name="RBBM_GPU_IDLE" pos="0"/> + <bitfield name="RBBM_AHB_ERROR" pos="1"/> + <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2"/> + <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/> + <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/> + <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5"/> + <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6"/> + <bitfield name="RBBM_GPC_ERROR" pos="7"/> + <bitfield name="CP_SW" pos="8"/> + <bitfield name="CP_HW_ERROR" pos="9"/> + <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/> + <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/> + <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/> + <bitfield name="CP_IB2" pos="13"/> + <bitfield name="CP_IB1" pos="14"/> + <bitfield name="CP_RB" pos="15"/> + <bitfield name="CP_UNUSED_1" pos="16"/> + <bitfield name="CP_RB_DONE_TS" pos="17"/> + <bitfield name="CP_WT_DONE_TS" pos="18"/> + <bitfield name="UNKNOWN_1" pos="19"/> + <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/> + <bitfield name="UNUSED_2" pos="21"/> + <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/> + <bitfield name="MISC_HANG_DETECT" pos="23"/> + <bitfield name="UCHE_OOB_ACCESS" pos="24"/> + <bitfield name="UCHE_TRAP_INTR" pos="25"/> + <bitfield name="DEBBUS_INTR_0" pos="26"/> + <bitfield name="DEBBUS_INTR_1" pos="27"/> + <bitfield name="GPMU_VOLTAGE_DROOP" pos="28"/> + <bitfield name="GPMU_FIRMWARE" pos="29"/> + <bitfield name="ISDB_CPU_IRQ" pos="30"/> + <bitfield name="ISDB_UNDER_DEBUG" pos="31"/> + </bitset> + + <!-- CP Interrupt bits --> + <bitset name="A5XX_CP_INT"> + <bitfield name="CP_OPCODE_ERROR" pos="0"/> + <bitfield name="CP_RESERVED_BIT_ERROR" pos="1"/> + <bitfield name="CP_HW_FAULT_ERROR" pos="2"/> + <bitfield name="CP_DMA_ERROR" pos="3"/> + <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/> + <bitfield name="CP_AHB_ERROR" pos="5"/> + </bitset> + + <!-- CP registers --> + <reg32 offset="0x0800" name="CP_RB_BASE"/> + <reg32 offset="0x0801" name="CP_RB_BASE_HI"/> + <reg32 offset="0x0802" name="CP_RB_CNTL"/> + <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/> + <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/> + <reg32 offset="0x0806" name="CP_RB_RPTR"/> + <reg32 offset="0x0807" name="CP_RB_WPTR"/> + <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/> + <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/> + <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/> + <reg32 offset="0x080c" name="CP_DRAW_STATE_DATA"/> + <reg32 offset="0x080d" name="CP_ME_NRT_ADDR_LO"/> + <reg32 offset="0x080e" name="CP_ME_NRT_ADDR_HI"/> + <reg32 offset="0x0810" name="CP_ME_NRT_DATA"/> + <reg32 offset="0x0817" name="CP_CRASH_SCRIPT_BASE_LO"/> + <reg32 offset="0x0818" name="CP_CRASH_SCRIPT_BASE_HI"/> + <reg32 offset="0x0819" name="CP_CRASH_DUMP_CNTL"/> + <reg32 offset="0x081a" name="CP_ME_STAT_ADDR"/> + <reg32 offset="0x081f" name="CP_ROQ_THRESHOLDS_1"/> + <reg32 offset="0x0820" name="CP_ROQ_THRESHOLDS_2"/> + <reg32 offset="0x0821" name="CP_ROQ_DBG_ADDR"/> + <reg32 offset="0x0822" name="CP_ROQ_DBG_DATA"/> + <reg32 offset="0x0823" name="CP_MEQ_DBG_ADDR"/> + <reg32 offset="0x0824" name="CP_MEQ_DBG_DATA"/> + <reg32 offset="0x0825" name="CP_MEQ_THRESHOLDS"/> + <reg32 offset="0x0826" name="CP_MERCIU_SIZE"/> + <reg32 offset="0x0827" name="CP_MERCIU_DBG_ADDR"/> + <reg32 offset="0x0828" name="CP_MERCIU_DBG_DATA_1"/> + <reg32 offset="0x0829" name="CP_MERCIU_DBG_DATA_2"/> + <reg32 offset="0x082a" name="CP_PFP_UCODE_DBG_ADDR"/> + <reg32 offset="0x082b" name="CP_PFP_UCODE_DBG_DATA"/> + <reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/> + <reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/> + <reg32 offset="0x0831" name="CP_CNTL"/> + <reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/> + <reg32 offset="0x0833" name="CP_CHICKEN_DBG"/> + <reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/> + <reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/> + <reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/> + <reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/> + <reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/> + <reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/> + <reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/> + <reg32 offset="0x083e" name="CP_CONTEXT_SWITCH_SAVE_ADDR_LO"/> + <reg32 offset="0x083f" name="CP_CONTEXT_SWITCH_SAVE_ADDR_HI"/> + <reg32 offset="0x0840" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/> + <reg32 offset="0x0841" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/> + <reg32 offset="0x0860" name="CP_ADDR_MODE_CNTL"/> + <reg32 offset="0x0b14" name="CP_ME_STAT_DATA"/> + <reg32 offset="0x0b15" name="CP_WFI_PEND_CTR"/> + <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"/> + <reg32 offset="0x0b1a" name="CP_HW_FAULT"/> + <reg32 offset="0x0b1c" name="CP_PROTECT_STATUS"/> + <reg32 offset="0x0b1f" name="CP_IB1_BASE"/> + <reg32 offset="0x0b20" name="CP_IB1_BASE_HI"/> + <reg32 offset="0x0b21" name="CP_IB1_BUFSZ"/> + <reg32 offset="0x0b22" name="CP_IB2_BASE"/> + <reg32 offset="0x0b23" name="CP_IB2_BASE_HI"/> + <reg32 offset="0x0b24" name="CP_IB2_BUFSZ"/> + <array offset="0x0b78" name="CP_SCRATCH" stride="1" length="8"> + <reg32 offset="0x0" name="REG" type="uint"/> + </array> + <array offset="0x0880" name="CP_PROTECT" stride="1" length="32"> + <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/> + </array> + <reg32 offset="0x08a0" name="CP_PROTECT_CNTL"/> + <reg32 offset="0x0b1b" name="CP_AHB_FAULT"/> + <reg32 offset="0x0bb0" name="CP_PERFCTR_CP_SEL_0" type="a5xx_cp_perfcounter_select"/> + <reg32 offset="0x0bb1" name="CP_PERFCTR_CP_SEL_1" type="a5xx_cp_perfcounter_select"/> + <reg32 offset="0x0bb2" name="CP_PERFCTR_CP_SEL_2" type="a5xx_cp_perfcounter_select"/> + <reg32 offset="0x0bb3" name="CP_PERFCTR_CP_SEL_3" type="a5xx_cp_perfcounter_select"/> + <reg32 offset="0x0bb4" name="CP_PERFCTR_CP_SEL_4" type="a5xx_cp_perfcounter_select"/> + <reg32 offset="0x0bb5" name="CP_PERFCTR_CP_SEL_5" type="a5xx_cp_perfcounter_select"/> + <reg32 offset="0x0bb6" name="CP_PERFCTR_CP_SEL_6" type="a5xx_cp_perfcounter_select"/> + <reg32 offset="0x0bb7" name="CP_PERFCTR_CP_SEL_7" type="a5xx_cp_perfcounter_select"/> + <reg32 offset="0x0bc1" name="VSC_ADDR_MODE_CNTL"/> + <reg32 offset="0x0bba" name="CP_POWERCTR_CP_SEL_0"/> + <reg32 offset="0x0bbb" name="CP_POWERCTR_CP_SEL_1"/> + <reg32 offset="0x0bbc" name="CP_POWERCTR_CP_SEL_2"/> + <reg32 offset="0x0bbd" name="CP_POWERCTR_CP_SEL_3"/> + + <!-- RBBM registers --> + <reg32 offset="0x0004" name="RBBM_CFG_DBGBUS_SEL_A"/> + <reg32 offset="0x0005" name="RBBM_CFG_DBGBUS_SEL_B"/> + <reg32 offset="0x0006" name="RBBM_CFG_DBGBUS_SEL_C"/> + <reg32 offset="0x0007" name="RBBM_CFG_DBGBUS_SEL_D"/> +<!-- +#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_INDEX_SHIFT 0x0 +#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT 0x8 +#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_INDEX_SHIFT 0x10 +#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_BLK_SEL_SHIFT 0x18 + --> + <reg32 offset="0x0008" name="RBBM_CFG_DBGBUS_CNTLT"/> + <reg32 offset="0x0009" name="RBBM_CFG_DBGBUS_CNTLM"/> + <reg32 offset="0x0018" name="RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT"/> + <reg32 offset="0x000a" name="RBBM_CFG_DBGBUS_OPL"/> + <reg32 offset="0x000b" name="RBBM_CFG_DBGBUS_OPE"/> + <reg32 offset="0x000c" name="RBBM_CFG_DBGBUS_IVTL_0"/> + <reg32 offset="0x000d" name="RBBM_CFG_DBGBUS_IVTL_1"/> + <reg32 offset="0x000e" name="RBBM_CFG_DBGBUS_IVTL_2"/> + <reg32 offset="0x000f" name="RBBM_CFG_DBGBUS_IVTL_3"/> + <reg32 offset="0x0010" name="RBBM_CFG_DBGBUS_MASKL_0"/> + <reg32 offset="0x0011" name="RBBM_CFG_DBGBUS_MASKL_1"/> + <reg32 offset="0x0012" name="RBBM_CFG_DBGBUS_MASKL_2"/> + <reg32 offset="0x0013" name="RBBM_CFG_DBGBUS_MASKL_3"/> + <reg32 offset="0x0014" name="RBBM_CFG_DBGBUS_BYTEL_0"/> + <reg32 offset="0x0015" name="RBBM_CFG_DBGBUS_BYTEL_1"/> + <reg32 offset="0x0016" name="RBBM_CFG_DBGBUS_IVTE_0"/> + <reg32 offset="0x0017" name="RBBM_CFG_DBGBUS_IVTE_1"/> + <reg32 offset="0x0018" name="RBBM_CFG_DBGBUS_IVTE_2"/> + <reg32 offset="0x0019" name="RBBM_CFG_DBGBUS_IVTE_3"/> + <reg32 offset="0x001a" name="RBBM_CFG_DBGBUS_MASKE_0"/> + <reg32 offset="0x001b" name="RBBM_CFG_DBGBUS_MASKE_1"/> + <reg32 offset="0x001c" name="RBBM_CFG_DBGBUS_MASKE_2"/> + <reg32 offset="0x001d" name="RBBM_CFG_DBGBUS_MASKE_3"/> + <reg32 offset="0x001e" name="RBBM_CFG_DBGBUS_NIBBLEE"/> + <reg32 offset="0x001f" name="RBBM_CFG_DBGBUS_PTRC0"/> + <reg32 offset="0x0020" name="RBBM_CFG_DBGBUS_PTRC1"/> + <reg32 offset="0x0021" name="RBBM_CFG_DBGBUS_LOADREG"/> + <reg32 offset="0x0022" name="RBBM_CFG_DBGBUS_IDX"/> + <reg32 offset="0x0023" name="RBBM_CFG_DBGBUS_CLRC"/> + <reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/> + <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> + <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/> + <reg32 offset="0x0038" name="RBBM_INT_0_MASK"> + <bitfield name="RBBM_GPU_IDLE" pos="0"/> + <bitfield name="RBBM_AHB_ERROR" pos="1"/> + <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2"/> + <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/> + <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/> + <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5"/> + <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6"/> + <bitfield name="RBBM_GPC_ERROR" pos="7"/> + <bitfield name="CP_SW" pos="8"/> + <bitfield name="CP_HW_ERROR" pos="9"/> + <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/> + <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/> + <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/> + <bitfield name="CP_IB2" pos="13"/> + <bitfield name="CP_IB1" pos="14"/> + <bitfield name="CP_RB" pos="15"/> + <bitfield name="CP_RB_DONE_TS" pos="17"/> + <bitfield name="CP_WT_DONE_TS" pos="18"/> + <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/> + <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/> + <bitfield name="MISC_HANG_DETECT" pos="23"/> + <bitfield name="UCHE_OOB_ACCESS" pos="24"/> + <bitfield name="UCHE_TRAP_INTR" pos="25"/> + <bitfield name="DEBBUS_INTR_0" pos="26"/> + <bitfield name="DEBBUS_INTR_1" pos="27"/> + <bitfield name="GPMU_VOLTAGE_DROOP" pos="28"/> + <bitfield name="GPMU_FIRMWARE" pos="29"/> + <bitfield name="ISDB_CPU_IRQ" pos="30"/> + <bitfield name="ISDB_UNDER_DEBUG" pos="31"/> + </reg32> + <reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/> + <reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/> + <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/> + <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/> + <reg32 offset="0x0046" name="RBBM_BLOCK_SW_RESET_CMD2"/> + <reg32 offset="0x0048" name="RBBM_DBG_LO_HI_GPIO"/> + <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CNTL"/> + <reg32 offset="0x004a" name="RBBM_CLOCK_CNTL_TP0"/> + <reg32 offset="0x004b" name="RBBM_CLOCK_CNTL_TP1"/> + <reg32 offset="0x004c" name="RBBM_CLOCK_CNTL_TP2"/> + <reg32 offset="0x004d" name="RBBM_CLOCK_CNTL_TP3"/> + <reg32 offset="0x004e" name="RBBM_CLOCK_CNTL2_TP0"/> + <reg32 offset="0x004f" name="RBBM_CLOCK_CNTL2_TP1"/> + <reg32 offset="0x0050" name="RBBM_CLOCK_CNTL2_TP2"/> + <reg32 offset="0x0051" name="RBBM_CLOCK_CNTL2_TP3"/> + <reg32 offset="0x0052" name="RBBM_CLOCK_CNTL3_TP0"/> + <reg32 offset="0x0053" name="RBBM_CLOCK_CNTL3_TP1"/> + <reg32 offset="0x0054" name="RBBM_CLOCK_CNTL3_TP2"/> + <reg32 offset="0x0055" name="RBBM_CLOCK_CNTL3_TP3"/> + <reg32 offset="0x0059" name="RBBM_READ_AHB_THROUGH_DBG"/> + <reg32 offset="0x005a" name="RBBM_CLOCK_CNTL_UCHE"/> + <reg32 offset="0x005b" name="RBBM_CLOCK_CNTL2_UCHE"/> + <reg32 offset="0x005c" name="RBBM_CLOCK_CNTL3_UCHE"/> + <reg32 offset="0x005d" name="RBBM_CLOCK_CNTL4_UCHE"/> + <reg32 offset="0x005e" name="RBBM_CLOCK_HYST_UCHE"/> + <reg32 offset="0x005f" name="RBBM_CLOCK_DELAY_UCHE"/> + <reg32 offset="0x0060" name="RBBM_CLOCK_MODE_GPC"/> + <reg32 offset="0x0061" name="RBBM_CLOCK_DELAY_GPC"/> + <reg32 offset="0x0062" name="RBBM_CLOCK_HYST_GPC"/> + <reg32 offset="0x0063" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/> + <reg32 offset="0x0064" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/> + <reg32 offset="0x0065" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/> + <reg32 offset="0x0066" name="RBBM_CLOCK_DELAY_HLSQ"/> + <reg32 offset="0x0067" name="RBBM_CLOCK_CNTL"/> + <reg32 offset="0x0068" name="RBBM_CLOCK_CNTL_SP0"/> + <reg32 offset="0x0069" name="RBBM_CLOCK_CNTL_SP1"/> + <reg32 offset="0x006a" name="RBBM_CLOCK_CNTL_SP2"/> + <reg32 offset="0x006b" name="RBBM_CLOCK_CNTL_SP3"/> + <reg32 offset="0x006c" name="RBBM_CLOCK_CNTL2_SP0"/> + <reg32 offset="0x006d" name="RBBM_CLOCK_CNTL2_SP1"/> + <reg32 offset="0x006e" name="RBBM_CLOCK_CNTL2_SP2"/> + <reg32 offset="0x006f" name="RBBM_CLOCK_CNTL2_SP3"/> + <reg32 offset="0x0070" name="RBBM_CLOCK_HYST_SP0"/> + <reg32 offset="0x0071" name="RBBM_CLOCK_HYST_SP1"/> + <reg32 offset="0x0072" name="RBBM_CLOCK_HYST_SP2"/> + <reg32 offset="0x0073" name="RBBM_CLOCK_HYST_SP3"/> + <reg32 offset="0x0074" name="RBBM_CLOCK_DELAY_SP0"/> + <reg32 offset="0x0075" name="RBBM_CLOCK_DELAY_SP1"/> + <reg32 offset="0x0076" name="RBBM_CLOCK_DELAY_SP2"/> + <reg32 offset="0x0077" name="RBBM_CLOCK_DELAY_SP3"/> + <reg32 offset="0x0078" name="RBBM_CLOCK_CNTL_RB0"/> + <reg32 offset="0x0079" name="RBBM_CLOCK_CNTL_RB1"/> + <reg32 offset="0x007a" name="RBBM_CLOCK_CNTL_RB2"/> + <reg32 offset="0x007b" name="RBBM_CLOCK_CNTL_RB3"/> + <reg32 offset="0x007c" name="RBBM_CLOCK_CNTL2_RB0"/> + <reg32 offset="0x007d" name="RBBM_CLOCK_CNTL2_RB1"/> + <reg32 offset="0x007e" name="RBBM_CLOCK_CNTL2_RB2"/> + <reg32 offset="0x007f" name="RBBM_CLOCK_CNTL2_RB3"/> + <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_RAC"/> + <reg32 offset="0x0081" name="RBBM_CLOCK_DELAY_RAC"/> + <reg32 offset="0x0082" name="RBBM_CLOCK_CNTL_CCU0"/> + <reg32 offset="0x0083" name="RBBM_CLOCK_CNTL_CCU1"/> + <reg32 offset="0x0084" name="RBBM_CLOCK_CNTL_CCU2"/> + <reg32 offset="0x0085" name="RBBM_CLOCK_CNTL_CCU3"/> + <reg32 offset="0x0086" name="RBBM_CLOCK_HYST_RB_CCU0"/> + <reg32 offset="0x0087" name="RBBM_CLOCK_HYST_RB_CCU1"/> + <reg32 offset="0x0088" name="RBBM_CLOCK_HYST_RB_CCU2"/> + <reg32 offset="0x0089" name="RBBM_CLOCK_HYST_RB_CCU3"/> + <reg32 offset="0x008a" name="RBBM_CLOCK_CNTL_RAC"/> + <reg32 offset="0x008b" name="RBBM_CLOCK_CNTL2_RAC"/> + <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_RB_CCU_L1_0"/> + <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_RB_CCU_L1_1"/> + <reg32 offset="0x008e" name="RBBM_CLOCK_DELAY_RB_CCU_L1_2"/> + <reg32 offset="0x008f" name="RBBM_CLOCK_DELAY_RB_CCU_L1_3"/> + <reg32 offset="0x0090" name="RBBM_CLOCK_HYST_VFD"/> + <reg32 offset="0x0091" name="RBBM_CLOCK_MODE_VFD"/> + <reg32 offset="0x0092" name="RBBM_CLOCK_DELAY_VFD"/> + <reg32 offset="0x0093" name="RBBM_AHB_CNTL0"/> + <reg32 offset="0x0094" name="RBBM_AHB_CNTL1"/> + <reg32 offset="0x0095" name="RBBM_AHB_CNTL2"/> + <reg32 offset="0x0096" name="RBBM_AHB_CMD"/> + <reg32 offset="0x009c" name="RBBM_INTERFACE_HANG_MASK_CNTL11"/> + <reg32 offset="0x009d" name="RBBM_INTERFACE_HANG_MASK_CNTL12"/> + <reg32 offset="0x009e" name="RBBM_INTERFACE_HANG_MASK_CNTL13"/> + <reg32 offset="0x009f" name="RBBM_INTERFACE_HANG_MASK_CNTL14"/> + <reg32 offset="0x00a0" name="RBBM_INTERFACE_HANG_MASK_CNTL15"/> + <reg32 offset="0x00a1" name="RBBM_INTERFACE_HANG_MASK_CNTL16"/> + <reg32 offset="0x00a2" name="RBBM_INTERFACE_HANG_MASK_CNTL17"/> + <reg32 offset="0x00a3" name="RBBM_INTERFACE_HANG_MASK_CNTL18"/> + <reg32 offset="0x00a4" name="RBBM_CLOCK_DELAY_TP0"/> + <reg32 offset="0x00a5" name="RBBM_CLOCK_DELAY_TP1"/> + <reg32 offset="0x00a6" name="RBBM_CLOCK_DELAY_TP2"/> + <reg32 offset="0x00a7" name="RBBM_CLOCK_DELAY_TP3"/> + <reg32 offset="0x00a8" name="RBBM_CLOCK_DELAY2_TP0"/> + <reg32 offset="0x00a9" name="RBBM_CLOCK_DELAY2_TP1"/> + <reg32 offset="0x00aa" name="RBBM_CLOCK_DELAY2_TP2"/> + <reg32 offset="0x00ab" name="RBBM_CLOCK_DELAY2_TP3"/> + <reg32 offset="0x00ac" name="RBBM_CLOCK_DELAY3_TP0"/> + <reg32 offset="0x00ad" name="RBBM_CLOCK_DELAY3_TP1"/> + <reg32 offset="0x00ae" name="RBBM_CLOCK_DELAY3_TP2"/> + <reg32 offset="0x00af" name="RBBM_CLOCK_DELAY3_TP3"/> + <reg32 offset="0x00b0" name="RBBM_CLOCK_HYST_TP0"/> + <reg32 offset="0x00b1" name="RBBM_CLOCK_HYST_TP1"/> + <reg32 offset="0x00b2" name="RBBM_CLOCK_HYST_TP2"/> + <reg32 offset="0x00b3" name="RBBM_CLOCK_HYST_TP3"/> + <reg32 offset="0x00b4" name="RBBM_CLOCK_HYST2_TP0"/> + <reg32 offset="0x00b5" name="RBBM_CLOCK_HYST2_TP1"/> + <reg32 offset="0x00b6" name="RBBM_CLOCK_HYST2_TP2"/> + <reg32 offset="0x00b7" name="RBBM_CLOCK_HYST2_TP3"/> + <reg32 offset="0x00b8" name="RBBM_CLOCK_HYST3_TP0"/> + <reg32 offset="0x00b9" name="RBBM_CLOCK_HYST3_TP1"/> + <reg32 offset="0x00ba" name="RBBM_CLOCK_HYST3_TP2"/> + <reg32 offset="0x00bb" name="RBBM_CLOCK_HYST3_TP3"/> + <reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL_GPMU"/> + <reg32 offset="0x00c9" name="RBBM_CLOCK_DELAY_GPMU"/> + <reg32 offset="0x00ca" name="RBBM_CLOCK_HYST_GPMU"/> + <reg32 offset="0x03a0" name="RBBM_PERFCTR_CP_0_LO"/> + <reg32 offset="0x03a1" name="RBBM_PERFCTR_CP_0_HI"/> + <reg32 offset="0x03a2" name="RBBM_PERFCTR_CP_1_LO"/> + <reg32 offset="0x03a3" name="RBBM_PERFCTR_CP_1_HI"/> + <reg32 offset="0x03a4" name="RBBM_PERFCTR_CP_2_LO"/> + <reg32 offset="0x03a5" name="RBBM_PERFCTR_CP_2_HI"/> + <reg32 offset="0x03a6" name="RBBM_PERFCTR_CP_3_LO"/> + <reg32 offset="0x03a7" name="RBBM_PERFCTR_CP_3_HI"/> + <reg32 offset="0x03a8" name="RBBM_PERFCTR_CP_4_LO"/> + <reg32 offset="0x03a9" name="RBBM_PERFCTR_CP_4_HI"/> + <reg32 offset="0x03aa" name="RBBM_PERFCTR_CP_5_LO"/> + <reg32 offset="0x03ab" name="RBBM_PERFCTR_CP_5_HI"/> + <reg32 offset="0x03ac" name="RBBM_PERFCTR_CP_6_LO"/> + <reg32 offset="0x03ad" name="RBBM_PERFCTR_CP_6_HI"/> + <reg32 offset="0x03ae" name="RBBM_PERFCTR_CP_7_LO"/> + <reg32 offset="0x03af" name="RBBM_PERFCTR_CP_7_HI"/> + <reg32 offset="0x03b0" name="RBBM_PERFCTR_RBBM_0_LO"/> + <reg32 offset="0x03b1" name="RBBM_PERFCTR_RBBM_0_HI"/> + <reg32 offset="0x03b2" name="RBBM_PERFCTR_RBBM_1_LO"/> + <reg32 offset="0x03b3" name="RBBM_PERFCTR_RBBM_1_HI"/> + <reg32 offset="0x03b4" name="RBBM_PERFCTR_RBBM_2_LO"/> + <reg32 offset="0x03b5" name="RBBM_PERFCTR_RBBM_2_HI"/> + <reg32 offset="0x03b6" name="RBBM_PERFCTR_RBBM_3_LO"/> + <reg32 offset="0x03b7" name="RBBM_PERFCTR_RBBM_3_HI"/> + <reg32 offset="0x03b8" name="RBBM_PERFCTR_PC_0_LO"/> + <reg32 offset="0x03b9" name="RBBM_PERFCTR_PC_0_HI"/> + <reg32 offset="0x03ba" name="RBBM_PERFCTR_PC_1_LO"/> + <reg32 offset="0x03bb" name="RBBM_PERFCTR_PC_1_HI"/> + <reg32 offset="0x03bc" name="RBBM_PERFCTR_PC_2_LO"/> + <reg32 offset="0x03bd" name="RBBM_PERFCTR_PC_2_HI"/> + <reg32 offset="0x03be" name="RBBM_PERFCTR_PC_3_LO"/> + <reg32 offset="0x03bf" name="RBBM_PERFCTR_PC_3_HI"/> + <reg32 offset="0x03c0" name="RBBM_PERFCTR_PC_4_LO"/> + <reg32 offset="0x03c1" name="RBBM_PERFCTR_PC_4_HI"/> + <reg32 offset="0x03c2" name="RBBM_PERFCTR_PC_5_LO"/> + <reg32 offset="0x03c3" name="RBBM_PERFCTR_PC_5_HI"/> + <reg32 offset="0x03c4" name="RBBM_PERFCTR_PC_6_LO"/> + <reg32 offset="0x03c5" name="RBBM_PERFCTR_PC_6_HI"/> + <reg32 offset="0x03c6" name="RBBM_PERFCTR_PC_7_LO"/> + <reg32 offset="0x03c7" name="RBBM_PERFCTR_PC_7_HI"/> + <reg32 offset="0x03c8" name="RBBM_PERFCTR_VFD_0_LO"/> + <reg32 offset="0x03c9" name="RBBM_PERFCTR_VFD_0_HI"/> + <reg32 offset="0x03ca" name="RBBM_PERFCTR_VFD_1_LO"/> + <reg32 offset="0x03cb" name="RBBM_PERFCTR_VFD_1_HI"/> + <reg32 offset="0x03cc" name="RBBM_PERFCTR_VFD_2_LO"/> + <reg32 offset="0x03cd" name="RBBM_PERFCTR_VFD_2_HI"/> + <reg32 offset="0x03ce" name="RBBM_PERFCTR_VFD_3_LO"/> + <reg32 offset="0x03cf" name="RBBM_PERFCTR_VFD_3_HI"/> + <reg32 offset="0x03d0" name="RBBM_PERFCTR_VFD_4_LO"/> + <reg32 offset="0x03d1" name="RBBM_PERFCTR_VFD_4_HI"/> + <reg32 offset="0x03d2" name="RBBM_PERFCTR_VFD_5_LO"/> + <reg32 offset="0x03d3" name="RBBM_PERFCTR_VFD_5_HI"/> + <reg32 offset="0x03d4" name="RBBM_PERFCTR_VFD_6_LO"/> + <reg32 offset="0x03d5" name="RBBM_PERFCTR_VFD_6_HI"/> + <reg32 offset="0x03d6" name="RBBM_PERFCTR_VFD_7_LO"/> + <reg32 offset="0x03d7" name="RBBM_PERFCTR_VFD_7_HI"/> + <reg32 offset="0x03d8" name="RBBM_PERFCTR_HLSQ_0_LO"/> + <reg32 offset="0x03d9" name="RBBM_PERFCTR_HLSQ_0_HI"/> + <reg32 offset="0x03da" name="RBBM_PERFCTR_HLSQ_1_LO"/> + <reg32 offset="0x03db" name="RBBM_PERFCTR_HLSQ_1_HI"/> + <reg32 offset="0x03dc" name="RBBM_PERFCTR_HLSQ_2_LO"/> + <reg32 offset="0x03dd" name="RBBM_PERFCTR_HLSQ_2_HI"/> + <reg32 offset="0x03de" name="RBBM_PERFCTR_HLSQ_3_LO"/> + <reg32 offset="0x03df" name="RBBM_PERFCTR_HLSQ_3_HI"/> + <reg32 offset="0x03e0" name="RBBM_PERFCTR_HLSQ_4_LO"/> + <reg32 offset="0x03e1" name="RBBM_PERFCTR_HLSQ_4_HI"/> + <reg32 offset="0x03e2" name="RBBM_PERFCTR_HLSQ_5_LO"/> + <reg32 offset="0x03e3" name="RBBM_PERFCTR_HLSQ_5_HI"/> + <reg32 offset="0x03e4" name="RBBM_PERFCTR_HLSQ_6_LO"/> + <reg32 offset="0x03e5" name="RBBM_PERFCTR_HLSQ_6_HI"/> + <reg32 offset="0x03e6" name="RBBM_PERFCTR_HLSQ_7_LO"/> + <reg32 offset="0x03e7" name="RBBM_PERFCTR_HLSQ_7_HI"/> + <reg32 offset="0x03e8" name="RBBM_PERFCTR_VPC_0_LO"/> + <reg32 offset="0x03e9" name="RBBM_PERFCTR_VPC_0_HI"/> + <reg32 offset="0x03ea" name="RBBM_PERFCTR_VPC_1_LO"/> + <reg32 offset="0x03eb" name="RBBM_PERFCTR_VPC_1_HI"/> + <reg32 offset="0x03ec" name="RBBM_PERFCTR_VPC_2_LO"/> + <reg32 offset="0x03ed" name="RBBM_PERFCTR_VPC_2_HI"/> + <reg32 offset="0x03ee" name="RBBM_PERFCTR_VPC_3_LO"/> + <reg32 offset="0x03ef" name="RBBM_PERFCTR_VPC_3_HI"/> + <reg32 offset="0x03f0" name="RBBM_PERFCTR_CCU_0_LO"/> + <reg32 offset="0x03f1" name="RBBM_PERFCTR_CCU_0_HI"/> + <reg32 offset="0x03f2" name="RBBM_PERFCTR_CCU_1_LO"/> + <reg32 offset="0x03f3" name="RBBM_PERFCTR_CCU_1_HI"/> + <reg32 offset="0x03f4" name="RBBM_PERFCTR_CCU_2_LO"/> + <reg32 offset="0x03f5" name="RBBM_PERFCTR_CCU_2_HI"/> + <reg32 offset="0x03f6" name="RBBM_PERFCTR_CCU_3_LO"/> + <reg32 offset="0x03f7" name="RBBM_PERFCTR_CCU_3_HI"/> + <reg32 offset="0x03f8" name="RBBM_PERFCTR_TSE_0_LO"/> + <reg32 offset="0x03f9" name="RBBM_PERFCTR_TSE_0_HI"/> + <reg32 offset="0x03fa" name="RBBM_PERFCTR_TSE_1_LO"/> + <reg32 offset="0x03fb" name="RBBM_PERFCTR_TSE_1_HI"/> + <reg32 offset="0x03fc" name="RBBM_PERFCTR_TSE_2_LO"/> + <reg32 offset="0x03fd" name="RBBM_PERFCTR_TSE_2_HI"/> + <reg32 offset="0x03fe" name="RBBM_PERFCTR_TSE_3_LO"/> + <reg32 offset="0x03ff" name="RBBM_PERFCTR_TSE_3_HI"/> + <reg32 offset="0x0400" name="RBBM_PERFCTR_RAS_0_LO"/> + <reg32 offset="0x0401" name="RBBM_PERFCTR_RAS_0_HI"/> + <reg32 offset="0x0402" name="RBBM_PERFCTR_RAS_1_LO"/> + <reg32 offset="0x0403" name="RBBM_PERFCTR_RAS_1_HI"/> + <reg32 offset="0x0404" name="RBBM_PERFCTR_RAS_2_LO"/> + <reg32 offset="0x0405" name="RBBM_PERFCTR_RAS_2_HI"/> + <reg32 offset="0x0406" name="RBBM_PERFCTR_RAS_3_LO"/> + <reg32 offset="0x0407" name="RBBM_PERFCTR_RAS_3_HI"/> + <reg32 offset="0x0408" name="RBBM_PERFCTR_UCHE_0_LO"/> + <reg32 offset="0x0409" name="RBBM_PERFCTR_UCHE_0_HI"/> + <reg32 offset="0x040a" name="RBBM_PERFCTR_UCHE_1_LO"/> + <reg32 offset="0x040b" name="RBBM_PERFCTR_UCHE_1_HI"/> + <reg32 offset="0x040c" name="RBBM_PERFCTR_UCHE_2_LO"/> + <reg32 offset="0x040d" name="RBBM_PERFCTR_UCHE_2_HI"/> + <reg32 offset="0x040e" name="RBBM_PERFCTR_UCHE_3_LO"/> + <reg32 offset="0x040f" name="RBBM_PERFCTR_UCHE_3_HI"/> + <reg32 offset="0x0410" name="RBBM_PERFCTR_UCHE_4_LO"/> + <reg32 offset="0x0411" name="RBBM_PERFCTR_UCHE_4_HI"/> + <reg32 offset="0x0412" name="RBBM_PERFCTR_UCHE_5_LO"/> + <reg32 offset="0x0413" name="RBBM_PERFCTR_UCHE_5_HI"/> + <reg32 offset="0x0414" name="RBBM_PERFCTR_UCHE_6_LO"/> + <reg32 offset="0x0415" name="RBBM_PERFCTR_UCHE_6_HI"/> + <reg32 offset="0x0416" name="RBBM_PERFCTR_UCHE_7_LO"/> + <reg32 offset="0x0417" name="RBBM_PERFCTR_UCHE_7_HI"/> + <reg32 offset="0x0418" name="RBBM_PERFCTR_TP_0_LO"/> + <reg32 offset="0x0419" name="RBBM_PERFCTR_TP_0_HI"/> + <reg32 offset="0x041a" name="RBBM_PERFCTR_TP_1_LO"/> + <reg32 offset="0x041b" name="RBBM_PERFCTR_TP_1_HI"/> + <reg32 offset="0x041c" name="RBBM_PERFCTR_TP_2_LO"/> + <reg32 offset="0x041d" name="RBBM_PERFCTR_TP_2_HI"/> + <reg32 offset="0x041e" name="RBBM_PERFCTR_TP_3_LO"/> + <reg32 offset="0x041f" name="RBBM_PERFCTR_TP_3_HI"/> + <reg32 offset="0x0420" name="RBBM_PERFCTR_TP_4_LO"/> + <reg32 offset="0x0421" name="RBBM_PERFCTR_TP_4_HI"/> + <reg32 offset="0x0422" name="RBBM_PERFCTR_TP_5_LO"/> + <reg32 offset="0x0423" name="RBBM_PERFCTR_TP_5_HI"/> + <reg32 offset="0x0424" name="RBBM_PERFCTR_TP_6_LO"/> + <reg32 offset="0x0425" name="RBBM_PERFCTR_TP_6_HI"/> + <reg32 offset="0x0426" name="RBBM_PERFCTR_TP_7_LO"/> + <reg32 offset="0x0427" name="RBBM_PERFCTR_TP_7_HI"/> + <reg32 offset="0x0428" name="RBBM_PERFCTR_SP_0_LO"/> + <reg32 offset="0x0429" name="RBBM_PERFCTR_SP_0_HI"/> + <reg32 offset="0x042a" name="RBBM_PERFCTR_SP_1_LO"/> + <reg32 offset="0x042b" name="RBBM_PERFCTR_SP_1_HI"/> + <reg32 offset="0x042c" name="RBBM_PERFCTR_SP_2_LO"/> + <reg32 offset="0x042d" name="RBBM_PERFCTR_SP_2_HI"/> + <reg32 offset="0x042e" name="RBBM_PERFCTR_SP_3_LO"/> + <reg32 offset="0x042f" name="RBBM_PERFCTR_SP_3_HI"/> + <reg32 offset="0x0430" name="RBBM_PERFCTR_SP_4_LO"/> + <reg32 offset="0x0431" name="RBBM_PERFCTR_SP_4_HI"/> + <reg32 offset="0x0432" name="RBBM_PERFCTR_SP_5_LO"/> + <reg32 offset="0x0433" name="RBBM_PERFCTR_SP_5_HI"/> + <reg32 offset="0x0434" name="RBBM_PERFCTR_SP_6_LO"/> + <reg32 offset="0x0435" name="RBBM_PERFCTR_SP_6_HI"/> + <reg32 offset="0x0436" name="RBBM_PERFCTR_SP_7_LO"/> + <reg32 offset="0x0437" name="RBBM_PERFCTR_SP_7_HI"/> + <reg32 offset="0x0438" name="RBBM_PERFCTR_SP_8_LO"/> + <reg32 offset="0x0439" name="RBBM_PERFCTR_SP_8_HI"/> + <reg32 offset="0x043a" name="RBBM_PERFCTR_SP_9_LO"/> + <reg32 offset="0x043b" name="RBBM_PERFCTR_SP_9_HI"/> + <reg32 offset="0x043c" name="RBBM_PERFCTR_SP_10_LO"/> + <reg32 offset="0x043d" name="RBBM_PERFCTR_SP_10_HI"/> + <reg32 offset="0x043e" name="RBBM_PERFCTR_SP_11_LO"/> + <reg32 offset="0x043f" name="RBBM_PERFCTR_SP_11_HI"/> + <reg32 offset="0x0440" name="RBBM_PERFCTR_RB_0_LO"/> + <reg32 offset="0x0441" name="RBBM_PERFCTR_RB_0_HI"/> + <reg32 offset="0x0442" name="RBBM_PERFCTR_RB_1_LO"/> + <reg32 offset="0x0443" name="RBBM_PERFCTR_RB_1_HI"/> + <reg32 offset="0x0444" name="RBBM_PERFCTR_RB_2_LO"/> + <reg32 offset="0x0445" name="RBBM_PERFCTR_RB_2_HI"/> + <reg32 offset="0x0446" name="RBBM_PERFCTR_RB_3_LO"/> + <reg32 offset="0x0447" name="RBBM_PERFCTR_RB_3_HI"/> + <reg32 offset="0x0448" name="RBBM_PERFCTR_RB_4_LO"/> + <reg32 offset="0x0449" name="RBBM_PERFCTR_RB_4_HI"/> + <reg32 offset="0x044a" name="RBBM_PERFCTR_RB_5_LO"/> + <reg32 offset="0x044b" name="RBBM_PERFCTR_RB_5_HI"/> + <reg32 offset="0x044c" name="RBBM_PERFCTR_RB_6_LO"/> + <reg32 offset="0x044d" name="RBBM_PERFCTR_RB_6_HI"/> + <reg32 offset="0x044e" name="RBBM_PERFCTR_RB_7_LO"/> + <reg32 offset="0x044f" name="RBBM_PERFCTR_RB_7_HI"/> + <reg32 offset="0x0450" name="RBBM_PERFCTR_VSC_0_LO"/> + <reg32 offset="0x0451" name="RBBM_PERFCTR_VSC_0_HI"/> + <reg32 offset="0x0452" name="RBBM_PERFCTR_VSC_1_LO"/> + <reg32 offset="0x0453" name="RBBM_PERFCTR_VSC_1_HI"/> + <reg32 offset="0x0454" name="RBBM_PERFCTR_LRZ_0_LO"/> + <reg32 offset="0x0455" name="RBBM_PERFCTR_LRZ_0_HI"/> + <reg32 offset="0x0456" name="RBBM_PERFCTR_LRZ_1_LO"/> + <reg32 offset="0x0457" name="RBBM_PERFCTR_LRZ_1_HI"/> + <reg32 offset="0x0458" name="RBBM_PERFCTR_LRZ_2_LO"/> + <reg32 offset="0x0459" name="RBBM_PERFCTR_LRZ_2_HI"/> + <reg32 offset="0x045a" name="RBBM_PERFCTR_LRZ_3_LO"/> + <reg32 offset="0x045b" name="RBBM_PERFCTR_LRZ_3_HI"/> + <reg32 offset="0x045c" name="RBBM_PERFCTR_CMP_0_LO"/> + <reg32 offset="0x045d" name="RBBM_PERFCTR_CMP_0_HI"/> + <reg32 offset="0x045e" name="RBBM_PERFCTR_CMP_1_LO"/> + <reg32 offset="0x045f" name="RBBM_PERFCTR_CMP_1_HI"/> + <reg32 offset="0x0460" name="RBBM_PERFCTR_CMP_2_LO"/> + <reg32 offset="0x0461" name="RBBM_PERFCTR_CMP_2_HI"/> + <reg32 offset="0x0462" name="RBBM_PERFCTR_CMP_3_LO"/> + <reg32 offset="0x0463" name="RBBM_PERFCTR_CMP_3_HI"/> + <reg32 offset="0x046b" name="RBBM_PERFCTR_RBBM_SEL_0" type="a5xx_rbbm_perfcounter_select"/> + <reg32 offset="0x046c" name="RBBM_PERFCTR_RBBM_SEL_1" type="a5xx_rbbm_perfcounter_select"/> + <reg32 offset="0x046d" name="RBBM_PERFCTR_RBBM_SEL_2" type="a5xx_rbbm_perfcounter_select"/> + <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3" type="a5xx_rbbm_perfcounter_select"/> + <reg32 offset="0x04d2" name="RBBM_ALWAYSON_COUNTER_LO"/> + <reg32 offset="0x04d3" name="RBBM_ALWAYSON_COUNTER_HI"/> + <reg32 offset="0x04f5" name="RBBM_STATUS"> + <bitfield high="31" low="31" name="GPU_BUSY_IGN_AHB" /> + <bitfield high="30" low="30" name="GPU_BUSY_IGN_AHB_CP" /> + <bitfield high="29" low="29" name="HLSQ_BUSY" /> + <bitfield high="28" low="28" name="VSC_BUSY" /> + <bitfield high="27" low="27" name="TPL1_BUSY" /> + <bitfield high="26" low="26" name="SP_BUSY" /> + <bitfield high="25" low="25" name="UCHE_BUSY" /> + <bitfield high="24" low="24" name="VPC_BUSY" /> + <bitfield high="23" low="23" name="VFDP_BUSY" /> + <bitfield high="22" low="22" name="VFD_BUSY" /> + <bitfield high="21" low="21" name="TESS_BUSY" /> + <bitfield high="20" low="20" name="PC_VSD_BUSY" /> + <bitfield high="19" low="19" name="PC_DCALL_BUSY" /> + <bitfield high="18" low="18" name="GPMU_SLAVE_BUSY" /> + <bitfield high="17" low="17" name="DCOM_BUSY" /> + <bitfield high="16" low="16" name="COM_BUSY" /> + <bitfield high="15" low="15" name="LRZ_BUZY" /> + <bitfield high="14" low="14" name="A2D_DSP_BUSY" /> + <bitfield high="13" low="13" name="CCUFCHE_BUSY" /> + <bitfield high="12" low="12" name="RB_BUSY" /> + <bitfield high="11" low="11" name="RAS_BUSY" /> + <bitfield high="10" low="10" name="TSE_BUSY" /> + <bitfield high="9" low="9" name="VBIF_BUSY" /> + <bitfield high="8" low="8" name="GPU_BUSY_IGN_AHB_HYST" /> + <bitfield high="7" low="7" name="CP_BUSY_IGN_HYST" /> + <bitfield high="6" low="6" name="CP_BUSY" /> + <bitfield high="5" low="5" name="GPMU_MASTER_BUSY" /> + <bitfield high="4" low="4" name="CP_CRASH_BUSY" /> + <bitfield high="3" low="3" name="CP_ETS_BUSY" /> + <bitfield high="2" low="2" name="CP_PFP_BUSY" /> + <bitfield high="1" low="1" name="CP_ME_BUSY" /> + <bitfield high="0" low="0" name="HI_BUSY" /> + </reg32> + <reg32 offset="0x0530" name="RBBM_STATUS3"/> + <reg32 offset="0x04e1" name="RBBM_INT_0_STATUS"/> + <reg32 offset="0x04f0" name="RBBM_AHB_ME_SPLIT_STATUS"/> + <reg32 offset="0x04f1" name="RBBM_AHB_PFP_SPLIT_STATUS"/> + <reg32 offset="0x04f3" name="RBBM_AHB_ETS_SPLIT_STATUS"/> + <reg32 offset="0x04f4" name="RBBM_AHB_ERROR_STATUS"/> + <reg32 offset="0x0464" name="RBBM_PERFCTR_CNTL"/> + <reg32 offset="0x0465" name="RBBM_PERFCTR_LOAD_CMD0"/> + <reg32 offset="0x0466" name="RBBM_PERFCTR_LOAD_CMD1"/> + <reg32 offset="0x0467" name="RBBM_PERFCTR_LOAD_CMD2"/> + <reg32 offset="0x0468" name="RBBM_PERFCTR_LOAD_CMD3"/> + <reg32 offset="0x0469" name="RBBM_PERFCTR_LOAD_VALUE_LO"/> + <reg32 offset="0x046a" name="RBBM_PERFCTR_LOAD_VALUE_HI"/> + <reg32 offset="0x046b" name="RBBM_PERFCTR_RBBM_SEL_0"/> + <reg32 offset="0x046c" name="RBBM_PERFCTR_RBBM_SEL_1"/> + <reg32 offset="0x046d" name="RBBM_PERFCTR_RBBM_SEL_2"/> + <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3"/> + <reg32 offset="0x046f" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/> + <reg32 offset="0x04ed" name="RBBM_AHB_ERROR"/> + <reg32 offset="0x0504" name="RBBM_CFG_DBGBUS_EVENT_LOGIC"/> + <reg32 offset="0x0505" name="RBBM_CFG_DBGBUS_OVER"/> + <reg32 offset="0x0506" name="RBBM_CFG_DBGBUS_COUNT0"/> + <reg32 offset="0x0507" name="RBBM_CFG_DBGBUS_COUNT1"/> + <reg32 offset="0x0508" name="RBBM_CFG_DBGBUS_COUNT2"/> + <reg32 offset="0x0509" name="RBBM_CFG_DBGBUS_COUNT3"/> + <reg32 offset="0x050a" name="RBBM_CFG_DBGBUS_COUNT4"/> + <reg32 offset="0x050b" name="RBBM_CFG_DBGBUS_COUNT5"/> + <reg32 offset="0x050c" name="RBBM_CFG_DBGBUS_TRACE_ADDR"/> + <reg32 offset="0x050d" name="RBBM_CFG_DBGBUS_TRACE_BUF0"/> + <reg32 offset="0x050e" name="RBBM_CFG_DBGBUS_TRACE_BUF1"/> + <reg32 offset="0x050f" name="RBBM_CFG_DBGBUS_TRACE_BUF2"/> + <reg32 offset="0x0510" name="RBBM_CFG_DBGBUS_TRACE_BUF3"/> + <reg32 offset="0x0511" name="RBBM_CFG_DBGBUS_TRACE_BUF4"/> + <reg32 offset="0x0512" name="RBBM_CFG_DBGBUS_MISR0"/> + <reg32 offset="0x0513" name="RBBM_CFG_DBGBUS_MISR1"/> + <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/> + <reg32 offset="0xf000" name="RBBM_SECVID_TRUST_CONFIG"/> + <reg32 offset="0xf400" name="RBBM_SECVID_TRUST_CNTL"/> + <reg32 offset="0xf800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/> + <reg32 offset="0xf801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/> + <reg32 offset="0xf802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/> + <reg32 offset="0xf803" name="RBBM_SECVID_TSB_CNTL"/> + <reg32 offset="0xf804" name="RBBM_SECVID_TSB_COMP_STATUS_LO"/> + <reg32 offset="0xf805" name="RBBM_SECVID_TSB_COMP_STATUS_HI"/> + <reg32 offset="0xf806" name="RBBM_SECVID_TSB_UCHE_STATUS_LO"/> + <reg32 offset="0xf807" name="RBBM_SECVID_TSB_UCHE_STATUS_HI"/> + <reg32 offset="0xf810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/> + + <!-- VSC registers --> + <reg32 offset="0x0bc2" name="VSC_BIN_SIZE"> + <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/> + <bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/> + <!-- b17 maybe BYPASS like RB_CNTL, but reg not written for bypass --> + </reg32> + <reg32 offset="0x0bc3" name="VSC_SIZE_ADDRESS_LO"/> + <reg32 offset="0x0bc4" name="VSC_SIZE_ADDRESS_HI"/> + <reg32 offset="0x0bc5" name="UNKNOWN_0BC5"/> <!-- always 00000000? --> + <reg32 offset="0x0bc6" name="UNKNOWN_0BC6"/> <!-- always 00000000? --> + <array offset="0x0bd0" name="VSC_PIPE_CONFIG" stride="1" length="16"> + <reg32 offset="0x0" name="REG"> + <doc> + Configures the mapping between VSC_PIPE buffer and + bin, X/Y specify the bin index in the horiz/vert + direction (0,0 is upper left, 0,1 is leftmost bin + on second row, and so on). W/H specify the number + of bins assigned to this VSC_PIPE in the horiz/vert + dimension. + </doc> + <bitfield name="X" low="0" high="9" type="uint"/> + <bitfield name="Y" low="10" high="19" type="uint"/> + <bitfield name="W" low="20" high="23" type="uint"/> + <bitfield name="H" low="24" high="27" type="uint"/> + </reg32> + </array> + <array offset="0x0be0" name="VSC_PIPE_DATA_ADDRESS" stride="2" length="16"> + <reg32 offset="0x0" name="LO"/> + <reg32 offset="0x1" name="HI"/> + </array> + <array offset="0x0c00" name="VSC_PIPE_DATA_LENGTH" stride="1" length="16"> + <reg32 offset="0x0" name="REG"/> + </array> + <reg32 offset="0x0c60" name="VSC_PERFCTR_VSC_SEL_0" type="a5xx_vsc_perfcounter_select"/> + <reg32 offset="0x0c61" name="VSC_PERFCTR_VSC_SEL_1" type="a5xx_vsc_perfcounter_select"/> + + <!-- used for some blits?? --> + <reg32 offset="0x0cdd" name="VSC_RESOLVE_CNTL" type="adreno_reg_xy"/> + + <!-- GRAS registers --> + <reg32 offset="0x0c81" name="GRAS_ADDR_MODE_CNTL"/> + <reg32 offset="0x0c90" name="GRAS_PERFCTR_TSE_SEL_0" type="a5xx_tse_perfcounter_select"/> + <reg32 offset="0x0c91" name="GRAS_PERFCTR_TSE_SEL_1" type="a5xx_tse_perfcounter_select"/> + <reg32 offset="0x0c92" name="GRAS_PERFCTR_TSE_SEL_2" type="a5xx_tse_perfcounter_select"/> + <reg32 offset="0x0c93" name="GRAS_PERFCTR_TSE_SEL_3" type="a5xx_tse_perfcounter_select"/> + <reg32 offset="0x0c94" name="GRAS_PERFCTR_RAS_SEL_0" type="a5xx_ras_perfcounter_select"/> + <reg32 offset="0x0c95" name="GRAS_PERFCTR_RAS_SEL_1" type="a5xx_ras_perfcounter_select"/> + <reg32 offset="0x0c96" name="GRAS_PERFCTR_RAS_SEL_2" type="a5xx_ras_perfcounter_select"/> + <reg32 offset="0x0c97" name="GRAS_PERFCTR_RAS_SEL_3" type="a5xx_ras_perfcounter_select"/> + <reg32 offset="0x0c98" name="GRAS_PERFCTR_LRZ_SEL_0" type="a5xx_lrz_perfcounter_select"/> + <reg32 offset="0x0c99" name="GRAS_PERFCTR_LRZ_SEL_1" type="a5xx_lrz_perfcounter_select"/> + <reg32 offset="0x0c9a" name="GRAS_PERFCTR_LRZ_SEL_2" type="a5xx_lrz_perfcounter_select"/> + <reg32 offset="0x0c9b" name="GRAS_PERFCTR_LRZ_SEL_3" type="a5xx_lrz_perfcounter_select"/> + + <reg32 offset="0x0cc4" name="RB_DBG_ECO_CNTL"/> <!-- always 00100000? --> + <reg32 offset="0x0cc5" name="RB_ADDR_MODE_CNTL"/> + <reg32 offset="0x0cc6" name="RB_MODE_CNTL"/> <!-- always 00000044? --> + <reg32 offset="0x0cc7" name="RB_CCU_CNTL"/> <!-- always b0056080 or 10000000? --> + <reg32 offset="0x0cd0" name="RB_PERFCTR_RB_SEL_0" type="a5xx_rb_perfcounter_select"/> + <reg32 offset="0x0cd1" name="RB_PERFCTR_RB_SEL_1" type="a5xx_rb_perfcounter_select"/> + <reg32 offset="0x0cd2" name="RB_PERFCTR_RB_SEL_2" type="a5xx_rb_perfcounter_select"/> + <reg32 offset="0x0cd3" name="RB_PERFCTR_RB_SEL_3" type="a5xx_rb_perfcounter_select"/> + <reg32 offset="0x0cd4" name="RB_PERFCTR_RB_SEL_4" type="a5xx_rb_perfcounter_select"/> + <reg32 offset="0x0cd5" name="RB_PERFCTR_RB_SEL_5" type="a5xx_rb_perfcounter_select"/> + <reg32 offset="0x0cd6" name="RB_PERFCTR_RB_SEL_6" type="a5xx_rb_perfcounter_select"/> + <reg32 offset="0x0cd7" name="RB_PERFCTR_RB_SEL_7" type="a5xx_rb_perfcounter_select"/> + <reg32 offset="0x0cd8" name="RB_PERFCTR_CCU_SEL_0" type="a5xx_ccu_perfcounter_select"/> + <reg32 offset="0x0cd9" name="RB_PERFCTR_CCU_SEL_1" type="a5xx_ccu_perfcounter_select"/> + <reg32 offset="0x0cda" name="RB_PERFCTR_CCU_SEL_2" type="a5xx_ccu_perfcounter_select"/> + <reg32 offset="0x0cdb" name="RB_PERFCTR_CCU_SEL_3" type="a5xx_ccu_perfcounter_select"/> + <reg32 offset="0x0ce0" name="RB_POWERCTR_RB_SEL_0"/> + <reg32 offset="0x0ce1" name="RB_POWERCTR_RB_SEL_1"/> + <reg32 offset="0x0ce2" name="RB_POWERCTR_RB_SEL_2"/> + <reg32 offset="0x0ce3" name="RB_POWERCTR_RB_SEL_3"/> + <reg32 offset="0x0ce4" name="RB_POWERCTR_CCU_SEL_0"/> + <reg32 offset="0x0ce5" name="RB_POWERCTR_CCU_SEL_1"/> + <reg32 offset="0x0cec" name="RB_PERFCTR_CMP_SEL_0" type="a5xx_cmp_perfcounter_select"/> + <reg32 offset="0x0ced" name="RB_PERFCTR_CMP_SEL_1" type="a5xx_cmp_perfcounter_select"/> + <reg32 offset="0x0cee" name="RB_PERFCTR_CMP_SEL_2" type="a5xx_cmp_perfcounter_select"/> + <reg32 offset="0x0cef" name="RB_PERFCTR_CMP_SEL_3" type="a5xx_cmp_perfcounter_select"/> + + <reg32 offset="0x0d00" name="PC_DBG_ECO_CNTL"> + <bitfield name="TWOPASSUSEWFI" pos="8" type="boolean"/> + </reg32> + <reg32 offset="0x0d01" name="PC_ADDR_MODE_CNTL"/> + <reg32 offset="0x0d02" name="PC_MODE_CNTL"/> <!-- always 0000001f? --> + <reg32 offset="0x0d04" name="PC_INDEX_BUF_LO"/> + <reg32 offset="0x0d05" name="PC_INDEX_BUF_HI"/> + <reg32 offset="0x0d06" name="PC_START_INDEX"/> + <reg32 offset="0x0d07" name="PC_MAX_INDEX"/> + <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR_LO"/> + <reg32 offset="0x0d09" name="PC_TESSFACTOR_ADDR_HI"/> + <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a5xx_pc_perfcounter_select"/> + <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a5xx_pc_perfcounter_select"/> + <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a5xx_pc_perfcounter_select"/> + <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a5xx_pc_perfcounter_select"/> + <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a5xx_pc_perfcounter_select"/> + <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a5xx_pc_perfcounter_select"/> + <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a5xx_pc_perfcounter_select"/> + <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a5xx_pc_perfcounter_select"/> + + <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD_0"/> + <reg32 offset="0x0e01" name="HLSQ_TIMEOUT_THRESHOLD_1"/> + <reg32 offset="0x0e04" name="HLSQ_DBG_ECO_CNTL"/> + <reg32 offset="0x0e05" name="HLSQ_ADDR_MODE_CNTL"/> + <reg32 offset="0x0e06" name="HLSQ_MODE_CNTL"/> <!-- always 00000001? --> + <reg32 offset="0x0e10" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a5xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e11" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a5xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e12" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a5xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e13" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a5xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e14" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a5xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e15" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a5xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e16" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a5xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0e17" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a5xx_hlsq_perfcounter_select"/> + <reg32 offset="0x0f08" name="HLSQ_SPTP_RDSEL"/> + <reg32 offset="0xbc00" name="HLSQ_DBG_READ_SEL"/> + <reg32 offset="0xa000" name="HLSQ_DBG_AHB_READ_APERTURE"/> + + <reg32 offset="0x0e41" name="VFD_ADDR_MODE_CNTL"/> + <reg32 offset="0x0e42" name="VFD_MODE_CNTL"/> <!-- always 00000000? --> + <reg32 offset="0x0e50" name="VFD_PERFCTR_VFD_SEL_0" type="a5xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e51" name="VFD_PERFCTR_VFD_SEL_1" type="a5xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e52" name="VFD_PERFCTR_VFD_SEL_2" type="a5xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e53" name="VFD_PERFCTR_VFD_SEL_3" type="a5xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e54" name="VFD_PERFCTR_VFD_SEL_4" type="a5xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e55" name="VFD_PERFCTR_VFD_SEL_5" type="a5xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e56" name="VFD_PERFCTR_VFD_SEL_6" type="a5xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e57" name="VFD_PERFCTR_VFD_SEL_7" type="a5xx_vfd_perfcounter_select"/> + <reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL"/> <!-- always 00000400? --> + <reg32 offset="0x0e61" name="VPC_ADDR_MODE_CNTL"/> + <reg32 offset="0x0e62" name="VPC_MODE_CNTL"> + <bitfield name="BINNING_PASS" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x0e64" name="VPC_PERFCTR_VPC_SEL_0" type="a5xx_vpc_perfcounter_select"/> + <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_1" type="a5xx_vpc_perfcounter_select"/> + <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_2" type="a5xx_vpc_perfcounter_select"/> + <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_3" type="a5xx_vpc_perfcounter_select"/> + + <reg32 offset="0x0e80" name="UCHE_ADDR_MODE_CNTL"/> + <reg32 offset="0x0e82" name="UCHE_SVM_CNTL"/> + <reg32 offset="0x0e87" name="UCHE_WRITE_THRU_BASE_LO"/> + <reg32 offset="0x0e88" name="UCHE_WRITE_THRU_BASE_HI"/> + <reg32 offset="0x0e89" name="UCHE_TRAP_BASE_LO"/> + <reg32 offset="0x0e8a" name="UCHE_TRAP_BASE_HI"/> + <reg32 offset="0x0e8b" name="UCHE_GMEM_RANGE_MIN_LO"/> + <reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/> + <reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/> + <reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/> + <reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/> + <reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/> + <reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/> + <reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/> + <reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/> + <reg32 offset="0x0e94" name="UCHE_CACHE_INVALIDATE_MAX_HI"/> + <reg32 offset="0x0e95" name="UCHE_CACHE_INVALIDATE"/> + <reg32 offset="0x0e96" name="UCHE_CACHE_WAYS"/> + <reg32 offset="0x0ea0" name="UCHE_PERFCTR_UCHE_SEL_0" type="a5xx_uche_perfcounter_select"/> + <reg32 offset="0x0ea1" name="UCHE_PERFCTR_UCHE_SEL_1" type="a5xx_uche_perfcounter_select"/> + <reg32 offset="0x0ea2" name="UCHE_PERFCTR_UCHE_SEL_2" type="a5xx_uche_perfcounter_select"/> + <reg32 offset="0x0ea3" name="UCHE_PERFCTR_UCHE_SEL_3" type="a5xx_uche_perfcounter_select"/> + <reg32 offset="0x0ea4" name="UCHE_PERFCTR_UCHE_SEL_4" type="a5xx_uche_perfcounter_select"/> + <reg32 offset="0x0ea5" name="UCHE_PERFCTR_UCHE_SEL_5" type="a5xx_uche_perfcounter_select"/> + <reg32 offset="0x0ea6" name="UCHE_PERFCTR_UCHE_SEL_6" type="a5xx_uche_perfcounter_select"/> + <reg32 offset="0x0ea7" name="UCHE_PERFCTR_UCHE_SEL_7" type="a5xx_uche_perfcounter_select"/> + <reg32 offset="0x0ea8" name="UCHE_POWERCTR_UCHE_SEL_0"/> + <reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/> + <reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/> + <reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/> + <reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/> + <reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/> + + <reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/> + <reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL"/> + <reg32 offset="0x0ec2" name="SP_MODE_CNTL"/> <!-- always 0000001e? --> + <reg32 offset="0x0ed0" name="SP_PERFCTR_SP_SEL_0" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0ed1" name="SP_PERFCTR_SP_SEL_1" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0ed2" name="SP_PERFCTR_SP_SEL_2" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0ed3" name="SP_PERFCTR_SP_SEL_3" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0ed4" name="SP_PERFCTR_SP_SEL_4" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0ed5" name="SP_PERFCTR_SP_SEL_5" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0ed6" name="SP_PERFCTR_SP_SEL_6" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0ed7" name="SP_PERFCTR_SP_SEL_7" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0ed8" name="SP_PERFCTR_SP_SEL_8" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0ed9" name="SP_PERFCTR_SP_SEL_9" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0eda" name="SP_PERFCTR_SP_SEL_10" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0edb" name="SP_PERFCTR_SP_SEL_11" type="a5xx_sp_perfcounter_select"/> + <reg32 offset="0x0edc" name="SP_POWERCTR_SP_SEL_0"/> + <reg32 offset="0x0edd" name="SP_POWERCTR_SP_SEL_1"/> + <reg32 offset="0x0ede" name="SP_POWERCTR_SP_SEL_2"/> + <reg32 offset="0x0edf" name="SP_POWERCTR_SP_SEL_3"/> + + <reg32 offset="0x0f01" name="TPL1_ADDR_MODE_CNTL"/> + <reg32 offset="0x0f02" name="TPL1_MODE_CNTL"/> <!-- always 00000544? --> + <reg32 offset="0x0f10" name="TPL1_PERFCTR_TP_SEL_0" type="a5xx_tp_perfcounter_select"/> + <reg32 offset="0x0f11" name="TPL1_PERFCTR_TP_SEL_1" type="a5xx_tp_perfcounter_select"/> + <reg32 offset="0x0f12" name="TPL1_PERFCTR_TP_SEL_2" type="a5xx_tp_perfcounter_select"/> + <reg32 offset="0x0f13" name="TPL1_PERFCTR_TP_SEL_3" type="a5xx_tp_perfcounter_select"/> + <reg32 offset="0x0f14" name="TPL1_PERFCTR_TP_SEL_4" type="a5xx_tp_perfcounter_select"/> + <reg32 offset="0x0f15" name="TPL1_PERFCTR_TP_SEL_5" type="a5xx_tp_perfcounter_select"/> + <reg32 offset="0x0f16" name="TPL1_PERFCTR_TP_SEL_6" type="a5xx_tp_perfcounter_select"/> + <reg32 offset="0x0f17" name="TPL1_PERFCTR_TP_SEL_7" type="a5xx_tp_perfcounter_select"/> + <reg32 offset="0x0f18" name="TPL1_POWERCTR_TP_SEL_0"/> + <reg32 offset="0x0f19" name="TPL1_POWERCTR_TP_SEL_1"/> + <reg32 offset="0x0f1a" name="TPL1_POWERCTR_TP_SEL_2"/> + <reg32 offset="0x0f1b" name="TPL1_POWERCTR_TP_SEL_3"/> + + <reg32 offset="0x3000" name="VBIF_VERSION"/> + <reg32 offset="0x3001" name="VBIF_CLKON"/> +<!-- +#define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_MASK 0x1 +#define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_SHIFT 0x1 + --> + <reg32 offset="0x3028" name="VBIF_ABIT_SORT"/> + <reg32 offset="0x3029" name="VBIF_ABIT_SORT_CONF"/> + <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/> + <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/> + <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/> + <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/> + <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/> +<!-- +#define A5XX_VBIF_XIN_HALT_CTRL0_MASK 0xF +#define A510_VBIF_XIN_HALT_CTRL0_MASK 0x7 + --> + <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/> + <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/> +<!-- +#define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_MASK 0x1 +#define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_SHIFT 0x0 + --> + <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/> + <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"/> +<!-- +#define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_MASK 0xF +#define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_SHIFT 0x0 + --> + <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/> + <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"/> +<!-- +#define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_MASK 0xF +#define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_SHIFT 0x0 + --> + <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/> + <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/> + <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/> + <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/> + <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/> + <reg32 offset="0x30c8" name="VBIF_PERF_CNT_CLR0"/> + <reg32 offset="0x30c9" name="VBIF_PERF_CNT_CLR1"/> + <reg32 offset="0x30ca" name="VBIF_PERF_CNT_CLR2"/> + <reg32 offset="0x30cb" name="VBIF_PERF_CNT_CLR3"/> + <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a5xx_vbif_perfcounter_select"/> + <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a5xx_vbif_perfcounter_select"/> + <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a5xx_vbif_perfcounter_select"/> + <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a5xx_vbif_perfcounter_select"/> + <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/> + <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/> + <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/> + <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/> + <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/> + <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/> + <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/> + <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/> + <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/> + <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/> + <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/> + <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/> + <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/> + <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/> + <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/> + <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/> + <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/> + + <reg32 offset="0x8800" name="GPMU_INST_RAM_BASE"/> + <reg32 offset="0x9800" name="GPMU_DATA_RAM_BASE"/> + <reg32 offset="0xa881" name="GPMU_SP_POWER_CNTL"/> + <reg32 offset="0xa886" name="GPMU_RBCCU_CLOCK_CNTL"/> + <reg32 offset="0xa887" name="GPMU_RBCCU_POWER_CNTL"/> + <reg32 offset="0xa88b" name="GPMU_SP_PWR_CLK_STATUS"> + <bitfield name="PWR_ON" pos="20" type="boolean"/> + </reg32> + <reg32 offset="0xa88d" name="GPMU_RBCCU_PWR_CLK_STATUS"> + <bitfield name="PWR_ON" pos="20" type="boolean"/> + </reg32> + <reg32 offset="0xa891" name="GPMU_PWR_COL_STAGGER_DELAY"/> + <reg32 offset="0xa892" name="GPMU_PWR_COL_INTER_FRAME_CTRL"/> + <reg32 offset="0xa893" name="GPMU_PWR_COL_INTER_FRAME_HYST"/> + <reg32 offset="0xa894" name="GPMU_PWR_COL_BINNING_CTRL"/> + <reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/> + <reg32 offset="0xa8c1" name="GPMU_WFI_CONFIG"/> + <reg32 offset="0xa8d6" name="GPMU_RBBM_INTR_INFO"/> + <reg32 offset="0xa8d8" name="GPMU_CM3_SYSRESET"/> + <reg32 offset="0xa8e0" name="GPMU_GENERAL_0"/> + <reg32 offset="0xa8e1" name="GPMU_GENERAL_1"/> + +<!-- +/* COUNTABLE FOR SP PERFCOUNTER */ +#define A5XX_SP_ALU_ACTIVE_CYCLES 0x1 +#define A5XX_SP0_ICL1_MISSES 0x35 +#define A5XX_SP_FS_CFLOW_INSTRUCTIONS 0x27 + +/* COUNTABLE FOR TSE PERFCOUNTER */ +#define A5XX_TSE_INPUT_PRIM_NUM 0x6 + --> + <reg32 offset="0xa840" name="SP_POWER_COUNTER_0_LO"/> + <reg32 offset="0xa841" name="SP_POWER_COUNTER_0_HI"/> + <reg32 offset="0xa842" name="SP_POWER_COUNTER_1_LO"/> + <reg32 offset="0xa843" name="SP_POWER_COUNTER_1_HI"/> + <reg32 offset="0xa844" name="SP_POWER_COUNTER_2_LO"/> + <reg32 offset="0xa845" name="SP_POWER_COUNTER_2_HI"/> + <reg32 offset="0xa846" name="SP_POWER_COUNTER_3_LO"/> + <reg32 offset="0xa847" name="SP_POWER_COUNTER_3_HI"/> + <reg32 offset="0xa848" name="TP_POWER_COUNTER_0_LO"/> + <reg32 offset="0xa849" name="TP_POWER_COUNTER_0_HI"/> + <reg32 offset="0xa84a" name="TP_POWER_COUNTER_1_LO"/> + <reg32 offset="0xa84b" name="TP_POWER_COUNTER_1_HI"/> + <reg32 offset="0xa84c" name="TP_POWER_COUNTER_2_LO"/> + <reg32 offset="0xa84d" name="TP_POWER_COUNTER_2_HI"/> + <reg32 offset="0xa84e" name="TP_POWER_COUNTER_3_LO"/> + <reg32 offset="0xa84f" name="TP_POWER_COUNTER_3_HI"/> + <reg32 offset="0xa850" name="RB_POWER_COUNTER_0_LO"/> + <reg32 offset="0xa851" name="RB_POWER_COUNTER_0_HI"/> + <reg32 offset="0xa852" name="RB_POWER_COUNTER_1_LO"/> + <reg32 offset="0xa853" name="RB_POWER_COUNTER_1_HI"/> + <reg32 offset="0xa854" name="RB_POWER_COUNTER_2_LO"/> + <reg32 offset="0xa855" name="RB_POWER_COUNTER_2_HI"/> + <reg32 offset="0xa856" name="RB_POWER_COUNTER_3_LO"/> + <reg32 offset="0xa857" name="RB_POWER_COUNTER_3_HI"/> + <reg32 offset="0xa858" name="CCU_POWER_COUNTER_0_LO"/> + <reg32 offset="0xa859" name="CCU_POWER_COUNTER_0_HI"/> + <reg32 offset="0xa85a" name="CCU_POWER_COUNTER_1_LO"/> + <reg32 offset="0xa85b" name="CCU_POWER_COUNTER_1_HI"/> + <reg32 offset="0xa85c" name="UCHE_POWER_COUNTER_0_LO"/> + <reg32 offset="0xa85d" name="UCHE_POWER_COUNTER_0_HI"/> + <reg32 offset="0xa85e" name="UCHE_POWER_COUNTER_1_LO"/> + <reg32 offset="0xa85f" name="UCHE_POWER_COUNTER_1_HI"/> + <reg32 offset="0xa860" name="UCHE_POWER_COUNTER_2_LO"/> + <reg32 offset="0xa861" name="UCHE_POWER_COUNTER_2_HI"/> + <reg32 offset="0xa862" name="UCHE_POWER_COUNTER_3_LO"/> + <reg32 offset="0xa863" name="UCHE_POWER_COUNTER_3_HI"/> + <reg32 offset="0xa864" name="CP_POWER_COUNTER_0_LO"/> + <reg32 offset="0xa865" name="CP_POWER_COUNTER_0_HI"/> + <reg32 offset="0xa866" name="CP_POWER_COUNTER_1_LO"/> + <reg32 offset="0xa867" name="CP_POWER_COUNTER_1_HI"/> + <reg32 offset="0xa868" name="CP_POWER_COUNTER_2_LO"/> + <reg32 offset="0xa869" name="CP_POWER_COUNTER_2_HI"/> + <reg32 offset="0xa86a" name="CP_POWER_COUNTER_3_LO"/> + <reg32 offset="0xa86b" name="CP_POWER_COUNTER_3_HI"/> + <reg32 offset="0xa86c" name="GPMU_POWER_COUNTER_0_LO"/> + <reg32 offset="0xa86d" name="GPMU_POWER_COUNTER_0_HI"/> + <reg32 offset="0xa86e" name="GPMU_POWER_COUNTER_1_LO"/> + <reg32 offset="0xa86f" name="GPMU_POWER_COUNTER_1_HI"/> + <reg32 offset="0xa870" name="GPMU_POWER_COUNTER_2_LO"/> + <reg32 offset="0xa871" name="GPMU_POWER_COUNTER_2_HI"/> + <reg32 offset="0xa872" name="GPMU_POWER_COUNTER_3_LO"/> + <reg32 offset="0xa873" name="GPMU_POWER_COUNTER_3_HI"/> + <reg32 offset="0xa874" name="GPMU_POWER_COUNTER_4_LO"/> + <reg32 offset="0xa875" name="GPMU_POWER_COUNTER_4_HI"/> + <reg32 offset="0xa876" name="GPMU_POWER_COUNTER_5_LO"/> + <reg32 offset="0xa877" name="GPMU_POWER_COUNTER_5_HI"/> + <reg32 offset="0xa878" name="GPMU_POWER_COUNTER_ENABLE"/> + <reg32 offset="0xa879" name="GPMU_ALWAYS_ON_COUNTER_LO"/> + <reg32 offset="0xa87a" name="GPMU_ALWAYS_ON_COUNTER_HI"/> + <reg32 offset="0xa87b" name="GPMU_ALWAYS_ON_COUNTER_RESET"/> + <reg32 offset="0xa87c" name="GPMU_POWER_COUNTER_SELECT_0"/> + <reg32 offset="0xa87d" name="GPMU_POWER_COUNTER_SELECT_1"/> + <reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/> + <reg32 offset="0xa8a8" name="GPMU_THROTTLE_UNMASK_FORCE_CTRL"/> + <reg32 offset="0xac00" name="GPMU_TEMP_SENSOR_ID"/> + <reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG"/> + <reg32 offset="0xac02" name="GPMU_TEMP_VAL"/> + <reg32 offset="0xac03" name="GPMU_DELTA_TEMP_THRESHOLD"/> + <reg32 offset="0xac05" name="GPMU_TEMP_THRESHOLD_INTR_STATUS"/> + <reg32 offset="0xac06" name="GPMU_TEMP_THRESHOLD_INTR_EN_MASK"/> + <reg32 offset="0xac40" name="GPMU_LEAKAGE_TEMP_COEFF_0_1"/> + <reg32 offset="0xac41" name="GPMU_LEAKAGE_TEMP_COEFF_2_3"/> + <reg32 offset="0xac42" name="GPMU_LEAKAGE_VTG_COEFF_0_1"/> + <reg32 offset="0xac43" name="GPMU_LEAKAGE_VTG_COEFF_2_3"/> + <reg32 offset="0xac46" name="GPMU_BASE_LEAKAGE"/> + <reg32 offset="0xac60" name="GPMU_GPMU_VOLTAGE"/> + <reg32 offset="0xac61" name="GPMU_GPMU_VOLTAGE_INTR_STATUS"/> + <reg32 offset="0xac62" name="GPMU_GPMU_VOLTAGE_INTR_EN_MASK"/> + <reg32 offset="0xac80" name="GPMU_GPMU_PWR_THRESHOLD"/> + <reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL"/> + <reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS"/> + <reg32 offset="0xb80c" name="GDPM_CONFIG1"/> + <reg32 offset="0xb80d" name="GDPM_CONFIG2"/> + <reg32 offset="0xb80f" name="GDPM_INT_EN"/> + <reg32 offset="0xb811" name="GDPM_INT_MASK"/> + <reg32 offset="0xb9a0" name="GPMU_BEC_ENABLE"/> + <reg32 offset="0xc41a" name="GPU_CS_SENSOR_GENERAL_STATUS"/> + <reg32 offset="0xc41d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/> + <reg32 offset="0xc41f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/> + <reg32 offset="0xc421" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/> + <reg32 offset="0xc520" name="GPU_CS_ENABLE_REG"/> + <reg32 offset="0xc557" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/> + + + <reg32 offset="0xe000" name="GRAS_CL_CNTL"> + <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/> + </reg32> + <reg32 offset="0xe001" name="UNKNOWN_E001"/> <!-- always 00000000? --> + <reg32 offset="0xe004" name="UNKNOWN_E004"/> <!-- always 00000000? --> + <reg32 offset="0xe005" name="GRAS_CNTL"> + <!-- see also RB_RENDER_CONTROL0 --> + <bitfield name="VARYING" pos="0" type="boolean"/> + <!-- + bit 3 set when blob turns on WCOORD.. which also corresponds to + register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which + shader does not use).. possibly providing wcoord in an alternate + way?? + Also, when that happens, VARYING bits are turned on as well. + --> + <bitfield name="UNK3" pos="3" type="boolean"/> + <bitfield name="XCOORD" pos="6" type="boolean"/> + <bitfield name="YCOORD" pos="7" type="boolean"/> + <bitfield name="ZCOORD" pos="8" type="boolean"/> + <bitfield name="WCOORD" pos="9" type="boolean"/> + </reg32> + <reg32 offset="0xe006" name="GRAS_CL_GUARDBAND_CLIP_ADJ"> + <bitfield name="HORZ" low="0" high="9" type="uint"/> + <bitfield name="VERT" low="10" high="19" type="uint"/> + </reg32> + <reg32 offset="0xe010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/> + <reg32 offset="0xe011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/> + <reg32 offset="0xe012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/> + <reg32 offset="0xe013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/> + <reg32 offset="0xe014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/> + <reg32 offset="0xe015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/> + <reg32 offset="0xe090" name="GRAS_SU_CNTL"> + <bitfield name="CULL_FRONT" pos="0" type="boolean"/> + <bitfield name="CULL_BACK" pos="1" type="boolean"/> + <bitfield name="FRONT_CW" pos="2" type="boolean"/> + <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/> + <bitfield name="POLY_OFFSET" pos="11" type="boolean"/> + <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/> + <!-- probably LINEHALFWIDTH is the same as a4xx.. --> + </reg32> + <reg32 offset="0xe091" name="GRAS_SU_POINT_MINMAX"> + <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> + <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> + </reg32> + <reg32 offset="0xe092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/> + <reg32 offset="0xe093" name="GRAS_SU_LAYERED"/> + <reg32 offset="0xe094" name="GRAS_SU_DEPTH_PLANE_CNTL"> + <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/> + <bitfield name="UNK1" pos="1" type="boolean"/> + </reg32> + <reg32 offset="0xe095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/> + <reg32 offset="0xe096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/> + <reg32 offset="0xe097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/> + <!-- duplicates RB_DEPTH_INFO0: --> + <reg32 offset="0xe098" name="GRAS_SU_DEPTH_BUFFER_INFO"> + <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/> + </reg32> + <reg32 offset="0xe099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL"/> <!-- always 00000000? --> + <!-- + guessing about window/screen/extent, I think they can in the end be + used interchangeably? + --> + <reg32 offset="0xe0a0" name="GRAS_SC_CNTL"> + <bitfield name="BINNING_PASS" pos="0" type="boolean"/> + <bitfield name="SAMPLES_PASSED" pos="15" type="boolean"/> + </reg32> + <!-- note, 0x4 for binning pass when frag writes z?? --> + <reg32 offset="0xe0a1" name="GRAS_SC_BIN_CNTL"/> <!-- always 00000000? --> + <reg32 offset="0xe0a2" name="GRAS_SC_RAS_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + </reg32> + <reg32 offset="0xe0a3" name="GRAS_SC_DEST_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> + </reg32> + <reg32 offset="0xe0a4" name="GRAS_SC_SCREEN_SCISSOR_CNTL"/> <!-- always 00000000? --> + <reg32 offset="0xe0aa" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/> + <reg32 offset="0xe0ab" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/> + <reg32 offset="0xe0ca" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/> + <reg32 offset="0xe0cb" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/> + <reg32 offset="0xe0ea" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/> + <reg32 offset="0xe0eb" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/> + + <doc> + LRZ: (Low Resolution Z ??) + ---- + + I think it serves two functions, early discard of primitives in binning + pass without needing full resolution depth buffer, and also functions as + a depth-prepass, used during the GMEM draws to discard primitives that + would not be visible due to later draws. + + The LRZ buffer always seems to be z16 format, regardless of actual + depth buffer format. + + Note that LRZ write should be disabled when blend/stencil/etc is enabled, + since the occluded primitive can still contribute to final color value + of a fragment. + + Only enabled for GL_LESS/GL_LEQUAL/GL_GREATER/GL_GEQUAL? + </doc> + <reg32 offset="0xe100" name="GRAS_LRZ_CNTL"> + <bitfield name="ENABLE" pos="0" type="boolean"/> + <doc>LRZ write also disabled for blend/etc.</doc> + <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> + <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc> + <bitfield name="GREATER" pos="2" type="boolean"/> + <!-- + b3 set sometimes, when depth buffer isn't cleared.. maybe it + invalidates the LRZ buffer? (Or just the covered positions? + --> + </reg32> + <reg32 offset="0xe101" name="GRAS_LRZ_BUFFER_BASE_LO"/> + <reg32 offset="0xe102" name="GRAS_LRZ_BUFFER_BASE_HI"/> + <!-- + lzr pitch is depth pitch (in pixels) / 8 (aligned to 32).. + --> + <doc> + Pitch is depth width (in pixels) / 8 (aligned to 32). Height + is also divided by 8 (ie. covers 8x8 pixels) + </doc> + <reg32 offset="0xe103" name="GRAS_LRZ_BUFFER_PITCH" shr="5" type="uint"/> + <reg32 offset="0xe104" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/> + <reg32 offset="0xe105" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/> + + <reg32 offset="0xe140" name="RB_CNTL"> + <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/> + <bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/> + <bitfield name="BYPASS" pos="17" type="boolean"/> + </reg32> + <reg32 offset="0xe141" name="RB_RENDER_CNTL"> +<!-- +bit 3 set for normal draws +bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set + for z32 with no stencil, but maybe in that case separate z/s not used? + see mrt-fbo-* zs=2) + --> + <bitfield name="BINNING_PASS" pos="0" type="boolean"/> + <bitfield name="SAMPLES_PASSED" pos="6" type="boolean"/> + <bitfield name="DISABLE_COLOR_PIPE" pos="7" type="boolean"/> + <!-- why everything twice?? maybe read vs write? --> + <!-- UBWC flag buffer enabled for depth/stencil: --> + <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/> + <bitfield name="FLAG_DEPTH2" pos="15" type="boolean"/> + <!-- bitmask of MRTs using UBWC flag buffer: --> + <bitfield name="FLAG_MRTS" low="16" high="23"/> + <bitfield name="FLAG_MRTS2" low="24" high="31"/> + </reg32> + <reg32 offset="0xe142" name="RB_RAS_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + </reg32> + <reg32 offset="0xe143" name="RB_DEST_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> + </reg32> + <!-- + note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL + name comes from kernel and is probably right) + --> + <reg32 offset="0xe144" name="RB_RENDER_CONTROL0"> + <!-- see also GRAS_CNTL --> + <bitfield name="VARYING" pos="0" type="boolean"/> + <!-- + bit 3 set when blob turns on WCOORD.. which also corresponds to + register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which + shader does not use).. possibly providing wcoord in an alternate + way?? + Also, when that happens, VARYING bits are turned on as well. + --> + <bitfield name="UNK3" pos="3" type="boolean"/> + <bitfield name="XCOORD" pos="6" type="boolean"/> + <bitfield name="YCOORD" pos="7" type="boolean"/> + <bitfield name="ZCOORD" pos="8" type="boolean"/> + <bitfield name="WCOORD" pos="9" type="boolean"/> + </reg32> + <reg32 offset="0xe145" name="RB_RENDER_CONTROL1"> + <bitfield name="SAMPLEMASK" pos="0" type="boolean"/> + <bitfield name="FACENESS" pos="1" type="boolean"/> + <bitfield name="SAMPLEID" pos="2" type="boolean"/> + </reg32> + <reg32 offset="0xe146" name="RB_FS_OUTPUT_CNTL"> + <!-- bit0 set except for binning pass.. --> + <bitfield name="MRT" low="0" high="3" type="uint"/> + <bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/> + </reg32> + <reg32 offset="0xe147" name="RB_RENDER_COMPONENTS"> + <bitfield name="RT0" low="0" high="3"/> + <bitfield name="RT1" low="4" high="7"/> + <bitfield name="RT2" low="8" high="11"/> + <bitfield name="RT3" low="12" high="15"/> + <bitfield name="RT4" low="16" high="19"/> + <bitfield name="RT5" low="20" high="23"/> + <bitfield name="RT6" low="24" high="27"/> + <bitfield name="RT7" low="28" high="31"/> + </reg32> + <array offset="0xe150" name="RB_MRT" stride="7" length="8"> + <reg32 offset="0x0" name="CONTROL"> + <bitfield name="BLEND" pos="0" type="boolean"/> + <bitfield name="BLEND2" pos="1" type="boolean"/> + <bitfield name="ROP_ENABLE" pos="2" type="boolean"/> + <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/> + <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/> + </reg32> + <reg32 offset="0x1" name="BLEND_CONTROL"> + <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/> + <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/> + <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/> + <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/> + </reg32> + <reg32 offset="0x2" name="BUF_INFO"> + <!-- + not sure if there is a separate COLOR_SWAP field like on a3xx/a4xx, + or if it is inherent in the format. Will have to play with bits + once we get things working and see what happens. If it is a diff + field, it doesn't seem to have the same encoding as a3xx/a4xx. + --> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/> + <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/> + <bitfield name="DITHER_MODE" low="11" high="12" type="adreno_rb_dither_mode"/> + <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> + <bitfield name="COLOR_SRGB" pos="15" type="boolean"/> + </reg32> + <!-- + at least in gmem, things seem to be aligned to pitch of 64.. + maybe an artifact of tiled format used in gmem? + --> + <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/> + <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/> + <reg32 offset="0x5" name="BASE_LO"/> + <reg32 offset="0x6" name="BASE_HI"/> + </array> + <reg32 offset="0xe1a0" name="RB_BLEND_RED"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="SINT" low="8" high="15" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0xe1a1" name="RB_BLEND_RED_F32" type="float"/> + <reg32 offset="0xe1a2" name="RB_BLEND_GREEN"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="SINT" low="8" high="15" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0xe1a3" name="RB_BLEND_GREEN_F32" type="float"/> + <reg32 offset="0xe1a4" name="RB_BLEND_BLUE"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="SINT" low="8" high="15" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0xe1a5" name="RB_BLEND_BLUE_F32" type="float"/> + <reg32 offset="0xe1a6" name="RB_BLEND_ALPHA"> + <bitfield name="UINT" low="0" high="7" type="hex"/> + <bitfield name="SINT" low="8" high="15" type="hex"/> + <bitfield name="FLOAT" low="16" high="31" type="float"/> + </reg32> + <reg32 offset="0xe1a7" name="RB_BLEND_ALPHA_F32" type="float"/> + <reg32 offset="0xe1a8" name="RB_ALPHA_CONTROL"> + <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> + <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> + <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> + </reg32> + <reg32 offset="0xe1a9" name="RB_BLEND_CNTL"> + <!-- per-mrt enable bit --> + <bitfield name="ENABLE_BLEND" low="0" high="7"/> + <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> + <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> + <!-- a guess? --> + <bitfield name="SAMPLE_MASK" low="16" high="31"/> + </reg32> + <reg32 offset="0xe1b0" name="RB_DEPTH_PLANE_CNTL"> + <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/> + <bitfield name="UNK1" pos="1" type="boolean"/> + </reg32> + <reg32 offset="0xe1b1" name="RB_DEPTH_CNTL"> + <bitfield name="Z_ENABLE" pos="0" type="boolean"/> + <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/> + <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/> + <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc> + <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/> + </reg32> + <reg32 offset="0xe1b2" name="RB_DEPTH_BUFFER_INFO"> + <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/> + </reg32> + <reg32 offset="0xe1b3" name="RB_DEPTH_BUFFER_BASE_LO"/> + <reg32 offset="0xe1b4" name="RB_DEPTH_BUFFER_BASE_HI"/> + <reg32 offset="0xe1b5" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint"> + <doc>stride of depth/stencil buffer</doc> + </reg32> + <reg32 offset="0xe1b6" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint"> + <doc>size of layer</doc> + </reg32> + <reg32 offset="0xe1c0" name="RB_STENCIL_CONTROL"> + <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> + <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> + <!-- + set for stencil operations that require read from stencil + buffer, but not for example for stencil clear (which does + not require read).. so guessing this is analogous to + READ_DEST_ENABLE for color buffer.. + --> + <bitfield name="STENCIL_READ" pos="2" type="boolean"/> + <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/> + <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/> + <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/> + <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/> + <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/> + <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/> + <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> + <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> + </reg32> + <reg32 offset="0xe1c1" name="RB_STENCIL_INFO"> + <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0xe1c2" name="RB_STENCIL_BASE_LO"/> + <reg32 offset="0xe1c3" name="RB_STENCIL_BASE_HI"/> + <reg32 offset="0xe1c4" name="RB_STENCIL_PITCH" shr="6" type="uint"/> + <reg32 offset="0xe1c5" name="RB_STENCIL_ARRAY_PITCH" shr="6" type="uint"/> + <reg32 offset="0xe1c6" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/> + <reg32 offset="0xe1c7" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/> + <reg32 offset="0xe1d0" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/> + <reg32 offset="0xe1d1" name="RB_SAMPLE_COUNT_CONTROL"> + <bitfield name="COPY" pos="1" type="boolean"/> + </reg32> + + <doc> + Blits: + ------ + + Blits are triggered by CP_EVENT_WRITE:BLIT, compared to previous + generations where they shared most of the gl pipeline and were + triggered by CP_DRAW_INDX* + + For gmem->mem blob uses RB_BLIT_CNTL.BUF to specify src of + blit (ie MRTn, ZS, etc) and RB_BLIT_DST_LO/HI for destination + gpuaddr. The gmem offset is taken from RB_MRT[n].BASE_LO/HI + + For mem->gmem blob uses just MRT0 or ZS and RB_BLIT_DST_LO/HI + for the GMEM offset, and gpuaddr from RB_MRT[0].BASE_LO/HI + (I suppose this is just to avoid trashing RB_MRT[1..7]??) + </doc> + <reg32 offset="0xe210" name="RB_BLIT_CNTL"> + <bitfield name="BUF" low="0" high="3" type="a5xx_blit_buf"/> + </reg32> + <reg32 offset="0xe211" name="RB_RESOLVE_CNTL_1" type="adreno_reg_xy"/> + <reg32 offset="0xe212" name="RB_RESOLVE_CNTL_2" type="adreno_reg_xy"/> + <reg32 offset="0xe213" name="RB_RESOLVE_CNTL_3"> + <!-- if b0 set, output is in TILE5_3 format --> + <bitfield name="TILED" pos="0" type="boolean"/> + <!-- + 0xe213: + 0x0 mem->gmem + 0xf gmem->mem with flag buffer (color) + 0x4 gmem->mem without flag buffer (color) + 0x7 BYPASS mode flag buffer result (ie. on readpix) + also for gmem->mem preserving tiling + --> + </reg32> + <reg32 offset="0xe214" name="RB_BLIT_DST_LO"/> + <reg32 offset="0xe215" name="RB_BLIT_DST_HI"/> + <reg32 offset="0xe216" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/> + <!-- array-pitch is size of layer --> + <reg32 offset="0xe217" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/> + <reg32 offset="0xe218" name="RB_CLEAR_COLOR_DW0"/> + <reg32 offset="0xe219" name="RB_CLEAR_COLOR_DW1"/> + <reg32 offset="0xe21a" name="RB_CLEAR_COLOR_DW2"/> + <reg32 offset="0xe21b" name="RB_CLEAR_COLOR_DW3"/> + <reg32 offset="0xe21c" name="RB_CLEAR_CNTL"> + <bitfield name="FAST_CLEAR" pos="1" type="boolean"/> + <bitfield name="MSAA_RESOLVE" pos="2" type="boolean"/> + <doc> + For MASK, if RB_BLIT_CNTL.BUF=BLIT_ZS: + 1 - depth + 2 - stencil + 3 - depth+stencil + if RB_BLIT_CNTL.BUF=BLIT_MRTn + then probably a component mask, I always see 0xf + </doc> + <bitfield name="MASK" low="4" high="7"/> + </reg32> + + <doc> + Buffer Metadata (flag buffers): + ------------------------------- + + Blob seems to stick some metadata at the front of the buffer, + both z/s and MRT. I think this is same as UBWC (bandwidth + compression) metadata that mdp 1.7 and later supports. See + 1d3fae5698ce5358caab87a15383b690941697e8 in downstream kernel. + UBWC seems to stand for "universal bandwidth compression". + + Before glReadPixels() it does a pair of BYPASS blits (at least + if metadata is used) presumably to resolve metadata. + + NOTES: see: getUBwcBlockSize(), getUBwcMetaBufferSize() at + https://android.googlesource.com/platform/hardware/qcom/display/+/android-6.0.1_r40/msm8994/libgralloc/alloc_controller.cpp + (note that bpp in bytes, not bits, so really cpp) + + Example Layout 2d w/ mipmap levels: + + 100x2000, ifmt=GL_RG, fmt=GL_RG16F, type=GL_FLOAT, meta=64x512@0x8000 (7x500) + base=c072e000, offset=16384, size=1703936 + + color flags + 0 c073a000 c0732000 - level 0 flags is address + 1 c0838000 c0834000 programmed in texture state + 2 c0879000 c0877000 + 3 c089a000 c0899000 + 4 c08ab000 c08aa000 + 5 c08b4000 c08b3000 + 6 c08b9000 c08b8000 + 7 c08bc000 c08bb000 + 8 c08be000 c08bd000 + 9 c08c0000 c08bf000 + 10 c08c2000 c08c1000 + + ARRAY_PITCH is the combined size of all the levels plus flags, + so 0xc08c3000 - 0xc0732000 = 0x00191000 (1642496); each level + takes up a minimum of 2 pages (since color and flags parts are + each page aligned. + + { TILE_MODE = TILE5_3 | SWIZ_X = A5XX_TEX_X | SWIZ_Y = A5XX_TEX_Y | SWIZ_Z = A5XX_TEX_ZERO | SWIZ_W = A5XX_TEX_ONE | MIPLVLS = 0 | FMT = TFMT5_16_16_FLOAT | SWAP = WZYX } + { WIDTH = 100 | HEIGHT = 2000 } + { FETCHSIZE = TFETCH5_4_BYTE | PITCH = 512 | TYPE = A5XX_TEX_2D } + { ARRAY_PITCH = 1642496 | 0x18800000 } - NOTE c2dc always has 0x18800000 but + { BASE_LO = 0xc0732000 } this varies for blob gles driver.. + { BASE_HI = 0 | DEPTH = 1 } not sure what it is + + + </doc> + <reg32 offset="0xe240" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/> + <reg32 offset="0xe241" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/> + <reg32 offset="0xe242" name="RB_DEPTH_FLAG_BUFFER_PITCH"> + </reg32> + <array offset="0xe243" name="RB_MRT_FLAG_BUFFER" stride="4" length="8"> + <reg32 offset="0" name="ADDR_LO"/> + <reg32 offset="1" name="ADDR_HI"/> + <reg32 offset="2" name="PITCH" shr="6" type="uint"/> + <!-- array-pitch is size of layer --> + <reg32 offset="3" name="ARRAY_PITCH" shr="6" type="uint"/> + </array> + <reg32 offset="0xe263" name="RB_BLIT_FLAG_DST_LO"/> + <reg32 offset="0xe264" name="RB_BLIT_FLAG_DST_HI"/> + <reg32 offset="0xe265" name="RB_BLIT_FLAG_DST_PITCH" shr="6" type="uint"/> + <!-- array-pitch is size of layer --> + <reg32 offset="0xe266" name="RB_BLIT_FLAG_DST_ARRAY_PITCH" shr="6" type="uint"/> + + <reg32 offset="0xe267" name="RB_SAMPLE_COUNT_ADDR_LO"/> + <reg32 offset="0xe268" name="RB_SAMPLE_COUNT_ADDR_HI"/> + + <reg32 offset="0xe280" name="VPC_CNTL_0"> + <doc> + num of varyings plus four for gl_Position (plus one if gl_PointSize) + plus # of transform-feedback (streamout) varyings if using the + hw streamout (rather than stg instructions in shader) + </doc> + <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/> + <bitfield name="VARYING" pos="11" type="boolean"/> + </reg32> + <array offset="0xe282" name="VPC_VARYING_INTERP" stride="1" length="8"> + <reg32 offset="0x0" name="MODE"/> + </array> + <array offset="0xe28a" name="VPC_VARYING_PS_REPL" stride="1" length="8"> + <reg32 offset="0x0" name="MODE"/> + </array> + <reg32 offset="0xe292" name="UNKNOWN_E292"/> + <reg32 offset="0xe293" name="UNKNOWN_E293"/> + <array offset="0xe294" name="VPC_VAR" stride="1" length="4"> + <!-- one bit per varying component: --> + <reg32 offset="0" name="DISABLE"/> + </array> + <reg32 offset="0xe298" name="VPC_GS_SIV_CNTL"/> + <reg32 offset="0xe29a" name="UNKNOWN_E29A"/> + <reg32 offset="0xe29d" name="VPC_PACK"> + <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> + <!-- + This seems to be the OUTLOC for the psize output. It could possibly + be the max-OUTLOC position, but it is only set when VS writes psize + (and blob always puts psize at highest OUTLOC) + --> + <bitfield name="PSIZELOC" low="8" high="15" type="uint"/> + </reg32> + <reg32 offset="0xe2a0" name="VPC_FS_PRIMITIVEID_CNTL"/> + + <doc> + Stream-Out: + ----------- + + VPC_SO[0..3] registers setup details about streamout buffers, and + number of components to write to each. + + VPC_SO_PROG provides the mapping between output varyings and the SO + buffers. It is written multiple times (via a CP_CONTEXT_REG_BUNCH + packet, not sure if that matters), each write can handle up to two + components of stream-out output. Order matches up to OUTLOC, + including padding. So, if outputting first 3 varyings: + + SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0x7 } + SP_VS_OUT[0x1].REG: { A_REGID = r1.w | A_COMPMASK = 0x3 | B_REGID = r2.y | B_COMPMASK = 0xf } + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 8 | OUTLOC3 = 12 } + + Then: + + VPC_SO_PROG: { A_BUF = 0 | A_OFF = 0 | A_EN | A_BUF = 0 | B_OFF = 4 | B_EN } + VPC_SO_PROG: { A_BUF = 0 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 12 | B_EN } + VPC_SO_PROG: { A_BUF = 2 | A_OFF = 0 | A_EN | A_BUF = 2 | B_OFF = 4 | B_EN } + VPC_SO_PROG: { A_BUF = 2 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 0 } + VPC_SO_PROG: { A_BUF = 1 | A_OFF = 0 | A_EN | A_BUF = 1 | B_OFF = 4 | B_EN } + + Note that varying order is OUTLOC0, OUTLOC2, OUTLOC1, and note + the padding between OUTLOC1 and OUTLOC2. + + The BUF bitfield indicates which of the four streamout buffers + to write into at the specified offset. + + The VPC_SO[n].FLUSH_BASE_LO/HI is used for hw to write back next + offset which gets loaded back into VPC_SO[n].BUFFER_OFFSET via a + CP_MEM_TO_REG. Probably can be ignored until we have GS/etc, at + which point we can't calculate the offset on the CPU. + </doc> + <reg32 offset="0xe2a1" name="VPC_SO_BUF_CNTL"> + <bitfield name="BUF0" pos="0" type="boolean"/> + <bitfield name="BUF1" pos="3" type="boolean"/> + <bitfield name="BUF2" pos="6" type="boolean"/> + <bitfield name="BUF3" pos="9" type="boolean"/> + <bitfield name="ENABLE" pos="15" type="boolean"/> + </reg32> + <reg32 offset="0xe2a2" name="VPC_SO_OVERRIDE"> + <bitfield name="SO_DISABLE" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0xe2a3" name="VPC_SO_CNTL"> + <!-- always 0x10000 when SO enabled.. --> + <bitfield name="ENABLE" pos="16" type="boolean"/> + </reg32> + <reg32 offset="0xe2a4" name="VPC_SO_PROG"> + <bitfield name="A_BUF" low="0" high="1" type="uint"/> + <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> + <bitfield name="A_EN" pos="11" type="boolean"/> + <bitfield name="B_BUF" low="12" high="13" type="uint"/> + <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> + <bitfield name="B_EN" pos="23" type="boolean"/> + </reg32> + <array offset="0xe2a7" name="VPC_SO" stride="7" length="4"> + <reg32 offset="0" name="BUFFER_BASE_LO"/> + <reg32 offset="1" name="BUFFER_BASE_HI"/> + <reg32 offset="2" name="BUFFER_SIZE"/> + <reg32 offset="3" name="NCOMP"/> <!-- component count --> + <reg32 offset="4" name="BUFFER_OFFSET"/> + <reg32 offset="5" name="FLUSH_BASE_LO"/> + <reg32 offset="6" name="FLUSH_BASE_HI"/> + </array> + + <reg32 offset="0xe384" name="PC_PRIMITIVE_CNTL"> + <!-- # of varyings plus four for gl_Position (plus one if gl_PointSize) --> + <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/> + <bitfield name="PRIMITIVE_RESTART" pos="8" type="boolean"/> + <bitfield name="COUNT_PRIMITIVES" pos="9" type="boolean"/><!-- enabled when gl_PrimitiveIDIn is used --> + <bitfield name="PROVOKING_VTX_LAST" pos="10" type="boolean"/> + </reg32> + <reg32 offset="0xe385" name="PC_PRIM_VTX_CNTL"> + <bitfield name="PSIZE" pos="11" type="boolean"/> + </reg32> + <reg32 offset="0xe388" name="PC_RASTER_CNTL"> + <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/> + <bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/> + <bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/> + </reg32> + <reg32 offset="0xe389" name="UNKNOWN_E389"/> + <reg32 offset="0xe38c" name="PC_RESTART_INDEX"/> + <reg32 offset="0xe38d" name="PC_GS_LAYERED"/> + <reg32 offset="0xe38e" name="PC_GS_PARAM"> + <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- vertices - 1 --> + <bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- invoc - 1 --> + <bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/> + </reg32> + <reg32 offset="0xe38f" name="PC_HS_PARAM"> + <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/> + <bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/> + <bitfield name="CW" pos="23" type="boolean"/> + <bitfield name="CONNECTED" pos="24" type="boolean"/> + </reg32> + <reg32 offset="0xe3b0" name="PC_POWER_CNTL"/> + + <reg32 offset="0xe400" name="VFD_CONTROL_0"> + <bitfield name="VTXCNT" low="0" high="5" type="uint"/> + </reg32> + <reg32 offset="0xe401" name="VFD_CONTROL_1"> + <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/> + <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/> + <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xe402" name="VFD_CONTROL_2"> + <bitfield name="REGID_PATCHID" low="0" high="7" type="a3xx_regid"/><!-- same as VFD_CONTROL_3.REGID_PATCHID? --> + </reg32> + <reg32 offset="0xe403" name="VFD_CONTROL_3"> + <bitfield name="REGID_PATCHID" low="8" high="15" type="a3xx_regid"/> + <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> + <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xe404" name="VFD_CONTROL_4"> + </reg32> + <reg32 offset="0xe405" name="VFD_CONTROL_5"> + <!-- b0 set if gl_PrimitiveID used in fs ?? --> + </reg32> + <reg32 offset="0xe408" name="VFD_INDEX_OFFSET"/> + <reg32 offset="0xe409" name="VFD_INSTANCE_START_OFFSET"/> + <array offset="0xe40a" name="VFD_FETCH" stride="4" length="32"> + <reg32 offset="0x0" name="BASE_LO"/> + <reg32 offset="0x1" name="BASE_HI"/> + <reg32 offset="0x2" name="SIZE" type="uint"/> + <reg32 offset="0x3" name="STRIDE" type="uint"/> + </array> + <array offset="0xe48a" name="VFD_DECODE" stride="2" length="32"> + <reg32 offset="0x0" name="INSTR"> + <!-- IDX appears to index into VFD_FETCH[] --> + <bitfield name="IDX" low="0" high="4" type="uint"/> + <bitfield name="INSTANCED" pos="17" type="boolean"/> + <bitfield name="FORMAT" low="20" high="27" type="a5xx_vtx_fmt"/> + <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/> + <bitfield name="UNK30" pos="30" type="boolean"/> + <bitfield name="FLOAT" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x1" name="STEP_RATE"/> <!-- ??? --> + </array> + <array offset="0xe4ca" name="VFD_DEST_CNTL" stride="1" length="32"> + <reg32 offset="0x0" name="INSTR"> + <bitfield name="WRITEMASK" low="0" high="3" type="hex"/> + <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/> + </reg32> + </array> + <reg32 offset="0xe4f0" name="VFD_POWER_CNTL"/> + + <!-- 0x0 for compute, 0x10 for 3d? --> + <reg32 offset="0xe580" name="SP_SP_CNTL"/> + + <bitset name="a5xx_xs_config" inline="yes"> + <bitfield name="ENABLED" pos="0" type="boolean"/> + <bitfield name="CONSTOBJECTOFFSET" low="1" high="7" type="uint"/> + <bitfield name="SHADEROBJOFFSET" low="8" high="14" type="uint"/> + </bitset> + <bitset name="a5xx_xs_cntl" inline="yes"> + <bitfield name="SSBO_ENABLE" pos="0" type="boolean"/> + <!-- + no idea high bit.. could be this is amount of on-chip memory used + rather than total size? + --> + <bitfield name="INSTRLEN" low="1" high="31" type="uint"/> + </bitset> + <bitset name="a5xx_sp_xs_ctrl_reg0" inline="yes"> + <!-- bit1 + bit2 set for "buffer" mode (ie. shader small enough to fit internally) --> + <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS --> + <bitfield name="THREADSIZE" pos="3" type="a3xx_threadsize"/> + <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/> + <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/> + <bitfield name="VARYING" pos="16" type="boolean"/> + <bitfield name="PIXLODENABLE" pos="20" type="boolean"/> + <!-- seems to be nesting level for flow control:.. --> + <bitfield name="BRANCHSTACK" low="25" high="31" type="uint"/> + </bitset> + <!-- assuming things appear in same relative order as a4xx: --> + <!-- duplicated exactly w/ corresponding HLSQ_ regs starting at 0xe78b.. --> + <reg32 offset="0xe584" name="SP_VS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe585" name="SP_FS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe586" name="SP_HS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe587" name="SP_DS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe588" name="SP_GS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe589" name="SP_CS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe58a" name="SP_VS_CONFIG_MAX_CONST"/> + <reg32 offset="0xe58b" name="SP_FS_CONFIG_MAX_CONST"/> + <reg32 offset="0xe590" name="SP_VS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xe592" name="SP_PRIMITIVE_CNTL"> + <!-- # of VS outputs including pos/psize --> + <bitfield name="VSOUT" low="0" high="4" type="uint"/> + </reg32> + <array offset="0xe593" name="SP_VS_OUT" stride="1" length="16"> + <reg32 offset="0x0" name="REG"> + <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> + <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> + <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> + </reg32> + </array> + <!-- + Starting with a5xx, position/psize outputs from shader end up in the + SP_VS_OUT map, with highest OUTLOCn position. (Generally they are + the last entries too, except when gl_PointCoord is used, blob inserts + an extra varying after, but with a lower OUTLOC position. If present, + psize is last, preceded by position. + --> + <array offset="0xe5a3" name="SP_VS_VPC_DST" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> + <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> + <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> + <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> + </reg32> + </array> + <reg32 offset="0xe5ab" name="UNKNOWN_E5AB"/> + <reg32 offset="0xe5ac" name="SP_VS_OBJ_START_LO"/> + <reg32 offset="0xe5ad" name="SP_VS_OBJ_START_HI"/> + <reg32 offset="0xe5c0" name="SP_FS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xe5c2" name="UNKNOWN_E5C2"/> + <reg32 offset="0xe5c3" name="SP_FS_OBJ_START_LO"/> + <reg32 offset="0xe5c4" name="SP_FS_OBJ_START_HI"/> + <reg32 offset="0xe5c9" name="SP_BLEND_CNTL"> + <bitfield name="ENABLED" pos="0" type="boolean"/> + <bitfield name="UNK8" pos="8" type="boolean"/> + <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> + </reg32> + <reg32 offset="0xe5ca" name="SP_FS_OUTPUT_CNTL"> + <bitfield name="MRT" low="0" high="3" type="uint"/> + <bitfield name="DEPTH_REGID" low="5" high="12" type="a3xx_regid"/> + <bitfield name="SAMPLEMASK_REGID" low="13" high="20" type="a3xx_regid"/> + </reg32> + <array offset="0xe5cb" name="SP_FS_OUTPUT" stride="1" length="8"> + <doc>per MRT</doc> + <reg32 offset="0x0" name="REG"> + <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="HALF_PRECISION" pos="8" type="boolean"/> + </reg32> + </array> + <array offset="0xe5d3" name="SP_FS_MRT" stride="1" length="8"> + <reg32 offset="0" name="REG"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/> + <bitfield name="COLOR_SINT" pos="8" type="boolean"/> + <bitfield name="COLOR_UINT" pos="9" type="boolean"/> + <bitfield name="COLOR_SRGB" pos="10" type="boolean"/> + </reg32> + </array> + <!-- + e5db/e5dc seems to look related to some optimization to do sample from + texture using varying value directly before shader thread starts? I + guess that could optimize common simple frag shaders.. + --> + <reg32 offset="0xe5db" name="UNKNOWN_E5DB"/> + <reg32 offset="0xe5f0" name="SP_CS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xe5f2" name="UNKNOWN_E5F2"/> + <reg32 offset="0xe5f3" name="SP_CS_OBJ_START_LO"/> + <reg32 offset="0xe5f4" name="SP_CS_OBJ_START_HI"/> + <!-- e5f9 something compute related.. seems to change when HLSQ_CS_CNTL_1 changes --> + + <reg32 offset="0xe600" name="SP_HS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xe602" name="UNKNOWN_E602"/> + <reg32 offset="0xe603" name="SP_HS_OBJ_START_LO"/> + <reg32 offset="0xe604" name="SP_HS_OBJ_START_HI"/> + <reg32 offset="0xe610" name="SP_DS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xe62b" name="UNKNOWN_E62B"/> + <reg32 offset="0xe62c" name="SP_DS_OBJ_START_LO"/> + <reg32 offset="0xe62d" name="SP_DS_OBJ_START_HI"/> + <reg32 offset="0xe640" name="SP_GS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xe65b" name="UNKNOWN_E65B"/> + <reg32 offset="0xe65c" name="SP_GS_OBJ_START_LO"/> + <reg32 offset="0xe65d" name="SP_GS_OBJ_START_HI"/> + + <reg32 offset="0xe704" name="TPL1_TP_RAS_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + </reg32> + <reg32 offset="0xe705" name="TPL1_TP_DEST_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> + </reg32> + <!-- either blob is doing it wrong, or this is not per-stage anymore: --> + <reg32 offset="0xe706" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_LO"/> + <reg32 offset="0xe707" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_HI"/> + + <!-- + so these have the same info that is normally in the CP_LOAD_STATE + packets.. not sure if they are normally written by pm4/me or if the + CP_LOAD_STATE mechanism is deprecated? + --> + <reg32 offset="0xe700" name="TPL1_VS_TEX_COUNT" type="uint"/> + <reg32 offset="0xe701" name="TPL1_HS_TEX_COUNT" type="uint"/> + <reg32 offset="0xe702" name="TPL1_DS_TEX_COUNT" type="uint"/> + <reg32 offset="0xe703" name="TPL1_GS_TEX_COUNT" type="uint"/> + + <reg32 offset="0xe722" name="TPL1_VS_TEX_SAMP_LO"/> + <reg32 offset="0xe723" name="TPL1_VS_TEX_SAMP_HI"/> + <reg32 offset="0xe724" name="TPL1_HS_TEX_SAMP_LO"/> + <reg32 offset="0xe725" name="TPL1_HS_TEX_SAMP_HI"/> + <reg32 offset="0xe726" name="TPL1_DS_TEX_SAMP_LO"/> + <reg32 offset="0xe727" name="TPL1_DS_TEX_SAMP_HI"/> + <reg32 offset="0xe728" name="TPL1_GS_TEX_SAMP_LO"/> + <reg32 offset="0xe729" name="TPL1_GS_TEX_SAMP_HI"/> + + <reg32 offset="0xe72a" name="TPL1_VS_TEX_CONST_LO"/> + <reg32 offset="0xe72b" name="TPL1_VS_TEX_CONST_HI"/> + <reg32 offset="0xe72c" name="TPL1_HS_TEX_CONST_LO"/> + <reg32 offset="0xe72d" name="TPL1_HS_TEX_CONST_HI"/> + <reg32 offset="0xe72e" name="TPL1_DS_TEX_CONST_LO"/> + <reg32 offset="0xe72f" name="TPL1_DS_TEX_CONST_HI"/> + <reg32 offset="0xe730" name="TPL1_GS_TEX_CONST_LO"/> + <reg32 offset="0xe731" name="TPL1_GS_TEX_CONST_HI"/> + + <reg32 offset="0xe750" name="TPL1_FS_TEX_COUNT" type="uint"/> + <reg32 offset="0xe751" name="TPL1_CS_TEX_COUNT" type="uint"/> + + <reg32 offset="0xe75a" name="TPL1_FS_TEX_SAMP_LO"/> + <reg32 offset="0xe75b" name="TPL1_FS_TEX_SAMP_HI"/> + <reg32 offset="0xe75c" name="TPL1_CS_TEX_SAMP_LO"/> + <reg32 offset="0xe75d" name="TPL1_CS_TEX_SAMP_HI"/> + <reg32 offset="0xe75e" name="TPL1_FS_TEX_CONST_LO"/> + <reg32 offset="0xe75f" name="TPL1_FS_TEX_CONST_HI"/> + <reg32 offset="0xe760" name="TPL1_CS_TEX_CONST_LO"/> + <reg32 offset="0xe761" name="TPL1_CS_TEX_CONST_HI"/> + + <reg32 offset="0xe764" name="TPL1_TP_FS_ROTATION_CNTL"/> + + <reg32 offset="0xe784" name="HLSQ_CONTROL_0_REG"> + <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS --> + <bitfield name="FSTHREADSIZE" pos="0" type="a3xx_threadsize"/> + <bitfield name="CSTHREADSIZE" pos="2" type="a3xx_threadsize"/> + </reg32> + <reg32 offset="0xe785" name="HLSQ_CONTROL_1_REG"> + <!-- I guess.. not set exactly same as a4xx, but similar: --> + <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="5" type="uint"/> + </reg32> + <reg32 offset="0xe786" name="HLSQ_CONTROL_2_REG"> + <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> + <!-- SAMPLEID is loaded into a half-precision register: --> + <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> + <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xe787" name="HLSQ_CONTROL_3_REG"> + <!-- register loaded with position (bary.f) --> + <bitfield name="FRAGCOORDXYREGID" low="0" high="7" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xe788" name="HLSQ_CONTROL_4_REG"> + <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/> + <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> + </reg32> + <!-- + 0x020fffff for normal draws, 0x1f00000 for compute.. maybe what state + is enabled? We could probably try disabling different bits and see + what breaks to figure out which is what: + --> + <reg32 offset="0xe78a" name="HLSQ_UPDATE_CNTL"/> + <reg32 offset="0xe78b" name="HLSQ_VS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe78c" name="HLSQ_FS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe78d" name="HLSQ_HS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe78e" name="HLSQ_DS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe78f" name="HLSQ_GS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe790" name="HLSQ_CS_CONFIG" type="a5xx_xs_config"/> + <reg32 offset="0xe791" name="HLSQ_VS_CNTL" type="a5xx_xs_cntl"/> + <reg32 offset="0xe792" name="HLSQ_FS_CNTL" type="a5xx_xs_cntl"/> + <reg32 offset="0xe793" name="HLSQ_HS_CNTL" type="a5xx_xs_cntl"/> + <reg32 offset="0xe794" name="HLSQ_DS_CNTL" type="a5xx_xs_cntl"/> + <reg32 offset="0xe795" name="HLSQ_GS_CNTL" type="a5xx_xs_cntl"/> + <reg32 offset="0xe796" name="HLSQ_CS_CNTL" type="a5xx_xs_cntl"/> + <reg32 offset="0xe7b9" name="HLSQ_CS_KERNEL_GROUP_X"/> + <reg32 offset="0xe7ba" name="HLSQ_CS_KERNEL_GROUP_Y"/> + <reg32 offset="0xe7bb" name="HLSQ_CS_KERNEL_GROUP_Z"/> + <reg32 offset="0xe7b0" name="HLSQ_CS_NDRANGE_0"> + <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> + <!-- localsize is value minus one: --> + <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> + <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> + <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> + </reg32> + <reg32 offset="0xe7b1" name="HLSQ_CS_NDRANGE_1"> + <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xe7b2" name="HLSQ_CS_NDRANGE_2"> + <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xe7b3" name="HLSQ_CS_NDRANGE_3"> + <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xe7b4" name="HLSQ_CS_NDRANGE_4"> + <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xe7b5" name="HLSQ_CS_NDRANGE_5"> + <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xe7b6" name="HLSQ_CS_NDRANGE_6"> + <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xe7b7" name="HLSQ_CS_CNTL_0"> + <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> + <!-- possibly one of these is KERNELDIMCONSTID? --> + <!-- + UNK0 appears to be NUMWGCONSTID.. but only works in certain + cases? Blob doesn't appear to use it, but instead emits + these via const (uniform). Which requires some shenanigans + for indirect draws when the offset is not strongly aligned + enough to use as EXT_SRC_ADDR in CP_LOAD_STATE + --> + <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/> + <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/> + <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xe7b8" name="HLSQ_CS_CNTL_1"/> + <reg32 offset="0xe7c0" name="UNKNOWN_E7C0"/> + <reg32 offset="0xe7c3" name="HLSQ_VS_CONSTLEN" type="uint"/> + <reg32 offset="0xe7c4" name="HLSQ_VS_INSTRLEN" type="uint"/> + <reg32 offset="0xe7c5" name="UNKNOWN_E7C5"/> + <reg32 offset="0xe7c8" name="HLSQ_HS_CONSTLEN" type="uint"/> + <reg32 offset="0xe7c9" name="HLSQ_HS_INSTRLEN" type="uint"/> + <reg32 offset="0xe7ca" name="UNKNOWN_E7CA"/> + <reg32 offset="0xe7cd" name="HLSQ_DS_CONSTLEN" type="uint"/> + <reg32 offset="0xe7ce" name="HLSQ_DS_INSTRLEN" type="uint"/> + <reg32 offset="0xe7cf" name="UNKNOWN_E7CF"/> + <reg32 offset="0xe7d2" name="HLSQ_GS_CONSTLEN" type="uint"/> + <reg32 offset="0xe7d3" name="HLSQ_GS_INSTRLEN" type="uint"/> + <reg32 offset="0xe7d4" name="UNKNOWN_E7D4"/> + <reg32 offset="0xe7d7" name="HLSQ_FS_CONSTLEN" type="uint"/> + <reg32 offset="0xe7d8" name="HLSQ_FS_INSTRLEN" type="uint"/> + <reg32 offset="0xe7d9" name="UNKNOWN_E7D9"/> + <reg32 offset="0xe7dc" name="HLSQ_CS_CONSTLEN" type="uint"/> + <reg32 offset="0xe7dd" name="HLSQ_CS_INSTRLEN" type="uint"/> + + <!-- + Separate blit/2d or dma engine? Seems to get used sometimes for + texture uploads, where a4xx blob would use normal draws. Used + in render-mode 0x5.. + + Note seems mostly to be used for small blits, large blits seem + to use the CP_EVENT_WRITE:BLIT style of doing things. See + cubemap-0003 (40x40) vs cubemap-0004 (256x256). + + see cube-0000, cubemap-(1..3 but not 4+), quad-textured-10..17 + + Other nearby registers are probably color formats, etc. The + blit coords are in CP packet. Play more w/ glTexSubImage2D() + to work it out. + + Separate this into a different domain?? Would that help to + restrict which registers we dump based on mode? + + regs 0x2000 to 0x2004 (plus all-zero regs 0x2005-0x2009) look + like 2nd source for blending? Used in mipmap generation.. but + maybe layout is a bit different. (Possibly used for reading + src via sampler, to enable scaling??) 0x2040 also used in this + case. + --> + <reg32 offset="0x2100" name="RB_2D_BLIT_CNTL"/> <!-- same as 0x2180 --> + <reg32 offset="0x2101" name="RB_2D_SRC_SOLID_DW0"/> + <reg32 offset="0x2102" name="RB_2D_SRC_SOLID_DW1"/> + <reg32 offset="0x2103" name="RB_2D_SRC_SOLID_DW2"/> + <reg32 offset="0x2104" name="RB_2D_SRC_SOLID_DW3"/> + <reg32 offset="0x2107" name="RB_2D_SRC_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/> + <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> + <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled --> + <bitfield name="FLAGS" pos="12" type="boolean"/> + </reg32> + <reg32 offset="0x2108" name="RB_2D_SRC_LO"/> + <reg32 offset="0x2109" name="RB_2D_SRC_HI"/> + <reg32 offset="0x210a" name="RB_2D_SRC_SIZE"> + <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/> + <bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/> + </reg32> + <reg32 offset="0x2110" name="RB_2D_DST_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/> + <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> + <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled --> + <bitfield name="FLAGS" pos="12" type="boolean"/> + </reg32> + <reg32 offset="0x2111" name="RB_2D_DST_LO"/> + <reg32 offset="0x2112" name="RB_2D_DST_HI"/> + <reg32 offset="0x2113" name="RB_2D_DST_SIZE"> + <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/> + <bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/> + </reg32> + <reg32 offset="0x2140" name="RB_2D_SRC_FLAGS_LO"/> + <reg32 offset="0x2141" name="RB_2D_SRC_FLAGS_HI"/> + <reg32 offset="0x2143" name="RB_2D_DST_FLAGS_LO"/> + <reg32 offset="0x2144" name="RB_2D_DST_FLAGS_HI"/> + <reg32 offset="0x2180" name="GRAS_2D_BLIT_CNTL"/> <!-- same as 0x2100 --> + <!-- looks same as 0x2107: --> + <reg32 offset="0x2181" name="GRAS_2D_SRC_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/> + <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> + <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled --> + <bitfield name="FLAGS" pos="12" type="boolean"/> + </reg32> + <!-- looks same as 0x2110: --> + <reg32 offset="0x2182" name="GRAS_2D_DST_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/> + <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> + <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled --> + <bitfield name="FLAGS" pos="12" type="boolean"/> + </reg32> +<!-- +0x2100 and 0x2180 look like same thing (RB and GRAS versions).. + 0x86000000 for copy, 0x00000000 for fill? + +0x2184 0x9 for copy, 0x1 for blit (maybe bitmask of enabled src/dst???) + --> + <reg32 offset="0x2100" name="UNKNOWN_2100"/> + <reg32 offset="0x2180" name="UNKNOWN_2180"/> + <reg32 offset="0x2184" name="UNKNOWN_2184"/> +</domain> + +<domain name="A5XX_TEX_SAMP" width="32"> + <doc>Texture sampler dwords</doc> + <enum name="a5xx_tex_filter"> <!-- same as a4xx? --> + <value name="A5XX_TEX_NEAREST" value="0"/> + <value name="A5XX_TEX_LINEAR" value="1"/> + <value name="A5XX_TEX_ANISO" value="2"/> + </enum> + <enum name="a5xx_tex_clamp"> <!-- same as a4xx? --> + <value name="A5XX_TEX_REPEAT" value="0"/> + <value name="A5XX_TEX_CLAMP_TO_EDGE" value="1"/> + <value name="A5XX_TEX_MIRROR_REPEAT" value="2"/> + <value name="A5XX_TEX_CLAMP_TO_BORDER" value="3"/> + <value name="A5XX_TEX_MIRROR_CLAMP" value="4"/> + </enum> + <enum name="a5xx_tex_aniso"> <!-- same as a4xx? --> + <value name="A5XX_TEX_ANISO_1" value="0"/> + <value name="A5XX_TEX_ANISO_2" value="1"/> + <value name="A5XX_TEX_ANISO_4" value="2"/> + <value name="A5XX_TEX_ANISO_8" value="3"/> + <value name="A5XX_TEX_ANISO_16" value="4"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> + <bitfield name="XY_MAG" low="1" high="2" type="a5xx_tex_filter"/> + <bitfield name="XY_MIN" low="3" high="4" type="a5xx_tex_filter"/> + <bitfield name="WRAP_S" low="5" high="7" type="a5xx_tex_clamp"/> + <bitfield name="WRAP_T" low="8" high="10" type="a5xx_tex_clamp"/> + <bitfield name="WRAP_R" low="11" high="13" type="a5xx_tex_clamp"/> + <bitfield name="ANISO" low="14" high="16" type="a5xx_tex_aniso"/> + <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real --> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/> + <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/> + <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/> + <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/> + <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/> + <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/> + </reg32> + <reg32 offset="2" name="2"> + <!-- + offset into border-color buffer? Blob always uses 0x80 for FS state + if both VS and FS have border-color. +Seems like when both VS and FS have bcolor, one starts 0x300 after other.. +and 0x80 in TEX_SAMP.2 .. blob doesn't seem to be able to cope w/ multiple +different border-color states per texture.. Looks something like: +0000: 3f000000 00000000 00000000 3f800000 00008000 ffff0000 00004000 7fff0000 +0020: 00003800 3c000000 80100010 0000f008 ff000080 7f000040 c0000200 00800000 +0040: 00003800 3c000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +0300: 3f800000 3f800000 3f800000 3f800000 ffffffff ffffffff 7fff7fff 7fff7fff +0320: 3c003c00 3c003c00 ffffffff 0000ffff ffffffff 7f7f7f7f ffffffff 00ffffff +0340: 3c003c00 3c003c00 00000000 00000000 00000000 00000000 00000000 00000000 + + --> + <bitfield name="BCOLOR_OFFSET" low="4" high="31"/> + </reg32> + <reg32 offset="3" name="3"/> +</domain> + +<domain name="A5XX_TEX_CONST" width="32"> + <doc>Texture constant dwords</doc> + <enum name="a5xx_tex_swiz"> <!-- same as a4xx? --> + <value name="A5XX_TEX_X" value="0"/> + <value name="A5XX_TEX_Y" value="1"/> + <value name="A5XX_TEX_Z" value="2"/> + <value name="A5XX_TEX_W" value="3"/> + <value name="A5XX_TEX_ZERO" value="4"/> + <value name="A5XX_TEX_ONE" value="5"/> + </enum> + <enum name="a5xx_tex_type"> <!-- same as a4xx? --> + <value name="A5XX_TEX_1D" value="0"/> + <value name="A5XX_TEX_2D" value="1"/> + <value name="A5XX_TEX_CUBE" value="2"/> + <value name="A5XX_TEX_3D" value="3"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="TILE_MODE" low="0" high="1" type="a5xx_tile_mode"/> + <bitfield name="SRGB" pos="2" type="boolean"/> + <bitfield name="SWIZ_X" low="4" high="6" type="a5xx_tex_swiz"/> + <bitfield name="SWIZ_Y" low="7" high="9" type="a5xx_tex_swiz"/> + <bitfield name="SWIZ_Z" low="10" high="12" type="a5xx_tex_swiz"/> + <bitfield name="SWIZ_W" low="13" high="15" type="a5xx_tex_swiz"/> + <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> + <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/> + <bitfield name="FMT" low="22" high="29" type="a5xx_tex_fmt"/> + <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="WIDTH" low="0" high="14" type="uint"/> + <bitfield name="HEIGHT" low="15" high="29" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="FETCHSIZE" low="0" high="3" type="a5xx_tex_fetchsize"/> + <doc>Pitch in bytes (so actually stride)</doc> + <bitfield name="PITCH" low="7" high="28" type="uint"/> + <bitfield name="TYPE" low="29" high="30" type="a5xx_tex_type"/> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/> + <bitfield name="FLAG" pos="28" type="boolean"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="BASE_LO" low="5" high="31" shr="5"/> + </reg32> + <reg32 offset="5" name="5"> + <bitfield name="BASE_HI" low="0" high="16"/> + <bitfield name="DEPTH" low="17" high="29" type="uint"/> + </reg32> + <reg32 offset="6" name="6"/> + <reg32 offset="7" name="7"/> + <reg32 offset="8" name="8"/> + <reg32 offset="9" name="9"/> + <reg32 offset="10" name="10"/> + <reg32 offset="11" name="11"/> +</domain> + +<!-- +Note the "SSBO" state blocks are actually used for both images and SSBOs, +naming is just because I r/e'd SSBOs first. I should probably come up +with a better name. +--> +<domain name="A5XX_SSBO_0" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="BASE_LO" low="5" high="31" shr="5"/> + </reg32> + <reg32 offset="1" name="1"> + <!-- no BASE_HI here? Maybe this is only used for 32b mode? --> + <doc>Pitch in bytes (so actually stride)</doc> + <bitfield name="PITCH" low="0" high="21" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/> + </reg32> + <reg32 offset="3" name="3"> + <!-- bytes per pixel: --> + <bitfield name="CPP" low="0" high="5" type="uint"/> + </reg32> +</domain> + +<domain name="A5XX_SSBO_1" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="FMT" low="8" high="15" type="a5xx_tex_fmt"/> + <bitfield name="WIDTH" low="16" high="31" type="uint"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="HEIGHT" low="0" high="15" type="uint"/> + <bitfield name="DEPTH" low="16" high="31" type="uint"/> + </reg32> +</domain> + +<domain name="A5XX_SSBO_2" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="BASE_LO" low="0" high="31"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="BASE_HI" low="0" high="31"/> + </reg32> +</domain> + +<domain name="A5XX_UBO" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="BASE_LO" low="0" high="31"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="BASE_HI" low="0" high="16"/> + <!-- size probably in high bits --> + </reg32> +</domain> + +</database> diff --git a/src/freedreno/registers/a5xx.xml.h b/src/freedreno/registers/a5xx.xml.h deleted file mode 100644 index 98ac09b88de..00000000000 --- a/src/freedreno/registers/a5xx.xml.h +++ /dev/null @@ -1,5244 +0,0 @@ -#ifndef A5XX_XML -#define A5XX_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2019 by the following authors: -- Rob Clark <[email protected]> (robclark) -- Ilia Mirkin <[email protected]> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum a5xx_color_fmt { - RB5_A8_UNORM = 2, - RB5_R8_UNORM = 3, - RB5_R8_SNORM = 4, - RB5_R8_UINT = 5, - RB5_R8_SINT = 6, - RB5_R4G4B4A4_UNORM = 8, - RB5_R5G5B5A1_UNORM = 10, - RB5_R5G6B5_UNORM = 14, - RB5_R8G8_UNORM = 15, - RB5_R8G8_SNORM = 16, - RB5_R8G8_UINT = 17, - RB5_R8G8_SINT = 18, - RB5_R16_UNORM = 21, - RB5_R16_SNORM = 22, - RB5_R16_FLOAT = 23, - RB5_R16_UINT = 24, - RB5_R16_SINT = 25, - RB5_R8G8B8A8_UNORM = 48, - RB5_R8G8B8_UNORM = 49, - RB5_R8G8B8A8_SNORM = 50, - RB5_R8G8B8A8_UINT = 51, - RB5_R8G8B8A8_SINT = 52, - RB5_R10G10B10A2_UNORM = 55, - RB5_R10G10B10A2_UINT = 58, - RB5_R11G11B10_FLOAT = 66, - RB5_R16G16_UNORM = 67, - RB5_R16G16_SNORM = 68, - RB5_R16G16_FLOAT = 69, - RB5_R16G16_UINT = 70, - RB5_R16G16_SINT = 71, - RB5_R32_FLOAT = 74, - RB5_R32_UINT = 75, - RB5_R32_SINT = 76, - RB5_R16G16B16A16_UNORM = 96, - RB5_R16G16B16A16_SNORM = 97, - RB5_R16G16B16A16_FLOAT = 98, - RB5_R16G16B16A16_UINT = 99, - RB5_R16G16B16A16_SINT = 100, - RB5_R32G32_FLOAT = 103, - RB5_R32G32_UINT = 104, - RB5_R32G32_SINT = 105, - RB5_R32G32B32A32_FLOAT = 130, - RB5_R32G32B32A32_UINT = 131, - RB5_R32G32B32A32_SINT = 132, -}; - -enum a5xx_tile_mode { - TILE5_LINEAR = 0, - TILE5_2 = 2, - TILE5_3 = 3, -}; - -enum a5xx_vtx_fmt { - VFMT5_8_UNORM = 3, - VFMT5_8_SNORM = 4, - VFMT5_8_UINT = 5, - VFMT5_8_SINT = 6, - VFMT5_8_8_UNORM = 15, - VFMT5_8_8_SNORM = 16, - VFMT5_8_8_UINT = 17, - VFMT5_8_8_SINT = 18, - VFMT5_16_UNORM = 21, - VFMT5_16_SNORM = 22, - VFMT5_16_FLOAT = 23, - VFMT5_16_UINT = 24, - VFMT5_16_SINT = 25, - VFMT5_8_8_8_UNORM = 33, - VFMT5_8_8_8_SNORM = 34, - VFMT5_8_8_8_UINT = 35, - VFMT5_8_8_8_SINT = 36, - VFMT5_8_8_8_8_UNORM = 48, - VFMT5_8_8_8_8_SNORM = 50, - VFMT5_8_8_8_8_UINT = 51, - VFMT5_8_8_8_8_SINT = 52, - VFMT5_10_10_10_2_UNORM = 54, - VFMT5_10_10_10_2_SNORM = 57, - VFMT5_10_10_10_2_UINT = 58, - VFMT5_10_10_10_2_SINT = 59, - VFMT5_11_11_10_FLOAT = 66, - VFMT5_16_16_UNORM = 67, - VFMT5_16_16_SNORM = 68, - VFMT5_16_16_FLOAT = 69, - VFMT5_16_16_UINT = 70, - VFMT5_16_16_SINT = 71, - VFMT5_32_UNORM = 72, - VFMT5_32_SNORM = 73, - VFMT5_32_FLOAT = 74, - VFMT5_32_UINT = 75, - VFMT5_32_SINT = 76, - VFMT5_32_FIXED = 77, - VFMT5_16_16_16_UNORM = 88, - VFMT5_16_16_16_SNORM = 89, - VFMT5_16_16_16_FLOAT = 90, - VFMT5_16_16_16_UINT = 91, - VFMT5_16_16_16_SINT = 92, - VFMT5_16_16_16_16_UNORM = 96, - VFMT5_16_16_16_16_SNORM = 97, - VFMT5_16_16_16_16_FLOAT = 98, - VFMT5_16_16_16_16_UINT = 99, - VFMT5_16_16_16_16_SINT = 100, - VFMT5_32_32_UNORM = 101, - VFMT5_32_32_SNORM = 102, - VFMT5_32_32_FLOAT = 103, - VFMT5_32_32_UINT = 104, - VFMT5_32_32_SINT = 105, - VFMT5_32_32_FIXED = 106, - VFMT5_32_32_32_UNORM = 112, - VFMT5_32_32_32_SNORM = 113, - VFMT5_32_32_32_UINT = 114, - VFMT5_32_32_32_SINT = 115, - VFMT5_32_32_32_FLOAT = 116, - VFMT5_32_32_32_FIXED = 117, - VFMT5_32_32_32_32_UNORM = 128, - VFMT5_32_32_32_32_SNORM = 129, - VFMT5_32_32_32_32_FLOAT = 130, - VFMT5_32_32_32_32_UINT = 131, - VFMT5_32_32_32_32_SINT = 132, - VFMT5_32_32_32_32_FIXED = 133, -}; - -enum a5xx_tex_fmt { - TFMT5_A8_UNORM = 2, - TFMT5_8_UNORM = 3, - TFMT5_8_SNORM = 4, - TFMT5_8_UINT = 5, - TFMT5_8_SINT = 6, - TFMT5_4_4_4_4_UNORM = 8, - TFMT5_5_5_5_1_UNORM = 10, - TFMT5_5_6_5_UNORM = 14, - TFMT5_8_8_UNORM = 15, - TFMT5_8_8_SNORM = 16, - TFMT5_8_8_UINT = 17, - TFMT5_8_8_SINT = 18, - TFMT5_L8_A8_UNORM = 19, - TFMT5_16_UNORM = 21, - TFMT5_16_SNORM = 22, - TFMT5_16_FLOAT = 23, - TFMT5_16_UINT = 24, - TFMT5_16_SINT = 25, - TFMT5_8_8_8_8_UNORM = 48, - TFMT5_8_8_8_UNORM = 49, - TFMT5_8_8_8_8_SNORM = 50, - TFMT5_8_8_8_8_UINT = 51, - TFMT5_8_8_8_8_SINT = 52, - TFMT5_9_9_9_E5_FLOAT = 53, - TFMT5_10_10_10_2_UNORM = 54, - TFMT5_10_10_10_2_UINT = 58, - TFMT5_11_11_10_FLOAT = 66, - TFMT5_16_16_UNORM = 67, - TFMT5_16_16_SNORM = 68, - TFMT5_16_16_FLOAT = 69, - TFMT5_16_16_UINT = 70, - TFMT5_16_16_SINT = 71, - TFMT5_32_FLOAT = 74, - TFMT5_32_UINT = 75, - TFMT5_32_SINT = 76, - TFMT5_16_16_16_16_UNORM = 96, - TFMT5_16_16_16_16_SNORM = 97, - TFMT5_16_16_16_16_FLOAT = 98, - TFMT5_16_16_16_16_UINT = 99, - TFMT5_16_16_16_16_SINT = 100, - TFMT5_32_32_FLOAT = 103, - TFMT5_32_32_UINT = 104, - TFMT5_32_32_SINT = 105, - TFMT5_32_32_32_UINT = 114, - TFMT5_32_32_32_SINT = 115, - TFMT5_32_32_32_FLOAT = 116, - TFMT5_32_32_32_32_FLOAT = 130, - TFMT5_32_32_32_32_UINT = 131, - TFMT5_32_32_32_32_SINT = 132, - TFMT5_X8Z24_UNORM = 160, - TFMT5_ETC2_RG11_UNORM = 171, - TFMT5_ETC2_RG11_SNORM = 172, - TFMT5_ETC2_R11_UNORM = 173, - TFMT5_ETC2_R11_SNORM = 174, - TFMT5_ETC1 = 175, - TFMT5_ETC2_RGB8 = 176, - TFMT5_ETC2_RGBA8 = 177, - TFMT5_ETC2_RGB8A1 = 178, - TFMT5_DXT1 = 179, - TFMT5_DXT3 = 180, - TFMT5_DXT5 = 181, - TFMT5_RGTC1_UNORM = 183, - TFMT5_RGTC1_SNORM = 184, - TFMT5_RGTC2_UNORM = 187, - TFMT5_RGTC2_SNORM = 188, - TFMT5_BPTC_UFLOAT = 190, - TFMT5_BPTC_FLOAT = 191, - TFMT5_BPTC = 192, - TFMT5_ASTC_4x4 = 193, - TFMT5_ASTC_5x4 = 194, - TFMT5_ASTC_5x5 = 195, - TFMT5_ASTC_6x5 = 196, - TFMT5_ASTC_6x6 = 197, - TFMT5_ASTC_8x5 = 198, - TFMT5_ASTC_8x6 = 199, - TFMT5_ASTC_8x8 = 200, - TFMT5_ASTC_10x5 = 201, - TFMT5_ASTC_10x6 = 202, - TFMT5_ASTC_10x8 = 203, - TFMT5_ASTC_10x10 = 204, - TFMT5_ASTC_12x10 = 205, - TFMT5_ASTC_12x12 = 206, -}; - -enum a5xx_tex_fetchsize { - TFETCH5_1_BYTE = 0, - TFETCH5_2_BYTE = 1, - TFETCH5_4_BYTE = 2, - TFETCH5_8_BYTE = 3, - TFETCH5_16_BYTE = 4, -}; - -enum a5xx_depth_format { - DEPTH5_NONE = 0, - DEPTH5_16 = 1, - DEPTH5_24_8 = 2, - DEPTH5_32 = 4, -}; - -enum a5xx_blit_buf { - BLIT_MRT0 = 0, - BLIT_MRT1 = 1, - BLIT_MRT2 = 2, - BLIT_MRT3 = 3, - BLIT_MRT4 = 4, - BLIT_MRT5 = 5, - BLIT_MRT6 = 6, - BLIT_MRT7 = 7, - BLIT_ZS = 8, - BLIT_S = 9, -}; - -enum a5xx_cp_perfcounter_select { - PERF_CP_ALWAYS_COUNT = 0, - PERF_CP_BUSY_GFX_CORE_IDLE = 1, - PERF_CP_BUSY_CYCLES = 2, - PERF_CP_PFP_IDLE = 3, - PERF_CP_PFP_BUSY_WORKING = 4, - PERF_CP_PFP_STALL_CYCLES_ANY = 5, - PERF_CP_PFP_STARVE_CYCLES_ANY = 6, - PERF_CP_PFP_ICACHE_MISS = 7, - PERF_CP_PFP_ICACHE_HIT = 8, - PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9, - PERF_CP_ME_BUSY_WORKING = 10, - PERF_CP_ME_IDLE = 11, - PERF_CP_ME_STARVE_CYCLES_ANY = 12, - PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13, - PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14, - PERF_CP_ME_FIFO_FULL_ME_BUSY = 15, - PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16, - PERF_CP_ME_STALL_CYCLES_ANY = 17, - PERF_CP_ME_ICACHE_MISS = 18, - PERF_CP_ME_ICACHE_HIT = 19, - PERF_CP_NUM_PREEMPTIONS = 20, - PERF_CP_PREEMPTION_REACTION_DELAY = 21, - PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22, - PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23, - PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24, - PERF_CP_PREDICATED_DRAWS_KILLED = 25, - PERF_CP_MODE_SWITCH = 26, - PERF_CP_ZPASS_DONE = 27, - PERF_CP_CONTEXT_DONE = 28, - PERF_CP_CACHE_FLUSH = 29, - PERF_CP_LONG_PREEMPTIONS = 30, -}; - -enum a5xx_rbbm_perfcounter_select { - PERF_RBBM_ALWAYS_COUNT = 0, - PERF_RBBM_ALWAYS_ON = 1, - PERF_RBBM_TSE_BUSY = 2, - PERF_RBBM_RAS_BUSY = 3, - PERF_RBBM_PC_DCALL_BUSY = 4, - PERF_RBBM_PC_VSD_BUSY = 5, - PERF_RBBM_STATUS_MASKED = 6, - PERF_RBBM_COM_BUSY = 7, - PERF_RBBM_DCOM_BUSY = 8, - PERF_RBBM_VBIF_BUSY = 9, - PERF_RBBM_VSC_BUSY = 10, - PERF_RBBM_TESS_BUSY = 11, - PERF_RBBM_UCHE_BUSY = 12, - PERF_RBBM_HLSQ_BUSY = 13, -}; - -enum a5xx_pc_perfcounter_select { - PERF_PC_BUSY_CYCLES = 0, - PERF_PC_WORKING_CYCLES = 1, - PERF_PC_STALL_CYCLES_VFD = 2, - PERF_PC_STALL_CYCLES_TSE = 3, - PERF_PC_STALL_CYCLES_VPC = 4, - PERF_PC_STALL_CYCLES_UCHE = 5, - PERF_PC_STALL_CYCLES_TESS = 6, - PERF_PC_STALL_CYCLES_TSE_ONLY = 7, - PERF_PC_STALL_CYCLES_VPC_ONLY = 8, - PERF_PC_PASS1_TF_STALL_CYCLES = 9, - PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, - PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, - PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, - PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, - PERF_PC_STARVE_CYCLES_DI = 14, - PERF_PC_VIS_STREAMS_LOADED = 15, - PERF_PC_INSTANCES = 16, - PERF_PC_VPC_PRIMITIVES = 17, - PERF_PC_DEAD_PRIM = 18, - PERF_PC_LIVE_PRIM = 19, - PERF_PC_VERTEX_HITS = 20, - PERF_PC_IA_VERTICES = 21, - PERF_PC_IA_PRIMITIVES = 22, - PERF_PC_GS_PRIMITIVES = 23, - PERF_PC_HS_INVOCATIONS = 24, - PERF_PC_DS_INVOCATIONS = 25, - PERF_PC_VS_INVOCATIONS = 26, - PERF_PC_GS_INVOCATIONS = 27, - PERF_PC_DS_PRIMITIVES = 28, - PERF_PC_VPC_POS_DATA_TRANSACTION = 29, - PERF_PC_3D_DRAWCALLS = 30, - PERF_PC_2D_DRAWCALLS = 31, - PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, - PERF_TESS_BUSY_CYCLES = 33, - PERF_TESS_WORKING_CYCLES = 34, - PERF_TESS_STALL_CYCLES_PC = 35, - PERF_TESS_STARVE_CYCLES_PC = 36, -}; - -enum a5xx_vfd_perfcounter_select { - PERF_VFD_BUSY_CYCLES = 0, - PERF_VFD_STALL_CYCLES_UCHE = 1, - PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, - PERF_VFD_STALL_CYCLES_MISS_VB = 3, - PERF_VFD_STALL_CYCLES_MISS_Q = 4, - PERF_VFD_STALL_CYCLES_SP_INFO = 5, - PERF_VFD_STALL_CYCLES_SP_ATTR = 6, - PERF_VFD_STALL_CYCLES_VFDP_VB = 7, - PERF_VFD_STALL_CYCLES_VFDP_Q = 8, - PERF_VFD_DECODER_PACKER_STALL = 9, - PERF_VFD_STARVE_CYCLES_UCHE = 10, - PERF_VFD_RBUFFER_FULL = 11, - PERF_VFD_ATTR_INFO_FIFO_FULL = 12, - PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13, - PERF_VFD_NUM_ATTRIBUTES = 14, - PERF_VFD_INSTRUCTIONS = 15, - PERF_VFD_UPPER_SHADER_FIBERS = 16, - PERF_VFD_LOWER_SHADER_FIBERS = 17, - PERF_VFD_MODE_0_FIBERS = 18, - PERF_VFD_MODE_1_FIBERS = 19, - PERF_VFD_MODE_2_FIBERS = 20, - PERF_VFD_MODE_3_FIBERS = 21, - PERF_VFD_MODE_4_FIBERS = 22, - PERF_VFD_TOTAL_VERTICES = 23, - PERF_VFD_NUM_ATTR_MISS = 24, - PERF_VFD_1_BURST_REQ = 25, - PERF_VFDP_STALL_CYCLES_VFD = 26, - PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27, - PERF_VFDP_STALL_CYCLES_VFD_PROG = 28, - PERF_VFDP_STARVE_CYCLES_PC = 29, - PERF_VFDP_VS_STAGE_32_WAVES = 30, -}; - -enum a5xx_hlsq_perfcounter_select { - PERF_HLSQ_BUSY_CYCLES = 0, - PERF_HLSQ_STALL_CYCLES_UCHE = 1, - PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, - PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, - PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, - PERF_HLSQ_UCHE_LATENCY_COUNT = 5, - PERF_HLSQ_FS_STAGE_32_WAVES = 6, - PERF_HLSQ_FS_STAGE_64_WAVES = 7, - PERF_HLSQ_QUADS = 8, - PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9, - PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10, - PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11, - PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12, - PERF_HLSQ_CS_INVOCATIONS = 13, - PERF_HLSQ_COMPUTE_DRAWCALLS = 14, -}; - -enum a5xx_vpc_perfcounter_select { - PERF_VPC_BUSY_CYCLES = 0, - PERF_VPC_WORKING_CYCLES = 1, - PERF_VPC_STALL_CYCLES_UCHE = 2, - PERF_VPC_STALL_CYCLES_VFD_WACK = 3, - PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, - PERF_VPC_STALL_CYCLES_PC = 5, - PERF_VPC_STALL_CYCLES_SP_LM = 6, - PERF_VPC_POS_EXPORT_STALL_CYCLES = 7, - PERF_VPC_STARVE_CYCLES_SP = 8, - PERF_VPC_STARVE_CYCLES_LRZ = 9, - PERF_VPC_PC_PRIMITIVES = 10, - PERF_VPC_SP_COMPONENTS = 11, - PERF_VPC_SP_LM_PRIMITIVES = 12, - PERF_VPC_SP_LM_COMPONENTS = 13, - PERF_VPC_SP_LM_DWORDS = 14, - PERF_VPC_STREAMOUT_COMPONENTS = 15, - PERF_VPC_GRANT_PHASES = 16, -}; - -enum a5xx_tse_perfcounter_select { - PERF_TSE_BUSY_CYCLES = 0, - PERF_TSE_CLIPPING_CYCLES = 1, - PERF_TSE_STALL_CYCLES_RAS = 2, - PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, - PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, - PERF_TSE_STARVE_CYCLES_PC = 5, - PERF_TSE_INPUT_PRIM = 6, - PERF_TSE_INPUT_NULL_PRIM = 7, - PERF_TSE_TRIVAL_REJ_PRIM = 8, - PERF_TSE_CLIPPED_PRIM = 9, - PERF_TSE_ZERO_AREA_PRIM = 10, - PERF_TSE_FACENESS_CULLED_PRIM = 11, - PERF_TSE_ZERO_PIXEL_PRIM = 12, - PERF_TSE_OUTPUT_NULL_PRIM = 13, - PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, - PERF_TSE_CINVOCATION = 15, - PERF_TSE_CPRIMITIVES = 16, - PERF_TSE_2D_INPUT_PRIM = 17, - PERF_TSE_2D_ALIVE_CLCLES = 18, -}; - -enum a5xx_ras_perfcounter_select { - PERF_RAS_BUSY_CYCLES = 0, - PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, - PERF_RAS_STALL_CYCLES_LRZ = 2, - PERF_RAS_STARVE_CYCLES_TSE = 3, - PERF_RAS_SUPER_TILES = 4, - PERF_RAS_8X4_TILES = 5, - PERF_RAS_MASKGEN_ACTIVE = 6, - PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, - PERF_RAS_FULLY_COVERED_8X4_TILES = 8, - PERF_RAS_PRIM_KILLED_INVISILBE = 9, -}; - -enum a5xx_lrz_perfcounter_select { - PERF_LRZ_BUSY_CYCLES = 0, - PERF_LRZ_STARVE_CYCLES_RAS = 1, - PERF_LRZ_STALL_CYCLES_RB = 2, - PERF_LRZ_STALL_CYCLES_VSC = 3, - PERF_LRZ_STALL_CYCLES_VPC = 4, - PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, - PERF_LRZ_STALL_CYCLES_UCHE = 6, - PERF_LRZ_LRZ_READ = 7, - PERF_LRZ_LRZ_WRITE = 8, - PERF_LRZ_READ_LATENCY = 9, - PERF_LRZ_MERGE_CACHE_UPDATING = 10, - PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, - PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, - PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, - PERF_LRZ_FULL_8X8_TILES = 14, - PERF_LRZ_PARTIAL_8X8_TILES = 15, - PERF_LRZ_TILE_KILLED = 16, - PERF_LRZ_TOTAL_PIXEL = 17, - PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, -}; - -enum a5xx_uche_perfcounter_select { - PERF_UCHE_BUSY_CYCLES = 0, - PERF_UCHE_STALL_CYCLES_VBIF = 1, - PERF_UCHE_VBIF_LATENCY_CYCLES = 2, - PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, - PERF_UCHE_VBIF_READ_BEATS_TP = 4, - PERF_UCHE_VBIF_READ_BEATS_VFD = 5, - PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, - PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, - PERF_UCHE_VBIF_READ_BEATS_SP = 8, - PERF_UCHE_READ_REQUESTS_TP = 9, - PERF_UCHE_READ_REQUESTS_VFD = 10, - PERF_UCHE_READ_REQUESTS_HLSQ = 11, - PERF_UCHE_READ_REQUESTS_LRZ = 12, - PERF_UCHE_READ_REQUESTS_SP = 13, - PERF_UCHE_WRITE_REQUESTS_LRZ = 14, - PERF_UCHE_WRITE_REQUESTS_SP = 15, - PERF_UCHE_WRITE_REQUESTS_VPC = 16, - PERF_UCHE_WRITE_REQUESTS_VSC = 17, - PERF_UCHE_EVICTS = 18, - PERF_UCHE_BANK_REQ0 = 19, - PERF_UCHE_BANK_REQ1 = 20, - PERF_UCHE_BANK_REQ2 = 21, - PERF_UCHE_BANK_REQ3 = 22, - PERF_UCHE_BANK_REQ4 = 23, - PERF_UCHE_BANK_REQ5 = 24, - PERF_UCHE_BANK_REQ6 = 25, - PERF_UCHE_BANK_REQ7 = 26, - PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, - PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, - PERF_UCHE_GMEM_READ_BEATS = 29, - PERF_UCHE_FLAG_COUNT = 30, -}; - -enum a5xx_tp_perfcounter_select { - PERF_TP_BUSY_CYCLES = 0, - PERF_TP_STALL_CYCLES_UCHE = 1, - PERF_TP_LATENCY_CYCLES = 2, - PERF_TP_LATENCY_TRANS = 3, - PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, - PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, - PERF_TP_L1_CACHELINE_REQUESTS = 6, - PERF_TP_L1_CACHELINE_MISSES = 7, - PERF_TP_SP_TP_TRANS = 8, - PERF_TP_TP_SP_TRANS = 9, - PERF_TP_OUTPUT_PIXELS = 10, - PERF_TP_FILTER_WORKLOAD_16BIT = 11, - PERF_TP_FILTER_WORKLOAD_32BIT = 12, - PERF_TP_QUADS_RECEIVED = 13, - PERF_TP_QUADS_OFFSET = 14, - PERF_TP_QUADS_SHADOW = 15, - PERF_TP_QUADS_ARRAY = 16, - PERF_TP_QUADS_GRADIENT = 17, - PERF_TP_QUADS_1D = 18, - PERF_TP_QUADS_2D = 19, - PERF_TP_QUADS_BUFFER = 20, - PERF_TP_QUADS_3D = 21, - PERF_TP_QUADS_CUBE = 22, - PERF_TP_STATE_CACHE_REQUESTS = 23, - PERF_TP_STATE_CACHE_MISSES = 24, - PERF_TP_DIVERGENT_QUADS_RECEIVED = 25, - PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26, - PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27, - PERF_TP_PRT_NON_RESIDENT_EVENTS = 28, - PERF_TP_OUTPUT_PIXELS_POINT = 29, - PERF_TP_OUTPUT_PIXELS_BILINEAR = 30, - PERF_TP_OUTPUT_PIXELS_MIP = 31, - PERF_TP_OUTPUT_PIXELS_ANISO = 32, - PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33, - PERF_TP_FLAG_CACHE_REQUESTS = 34, - PERF_TP_FLAG_CACHE_MISSES = 35, - PERF_TP_L1_5_L2_REQUESTS = 36, - PERF_TP_2D_OUTPUT_PIXELS = 37, - PERF_TP_2D_OUTPUT_PIXELS_POINT = 38, - PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39, - PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40, - PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41, -}; - -enum a5xx_sp_perfcounter_select { - PERF_SP_BUSY_CYCLES = 0, - PERF_SP_ALU_WORKING_CYCLES = 1, - PERF_SP_EFU_WORKING_CYCLES = 2, - PERF_SP_STALL_CYCLES_VPC = 3, - PERF_SP_STALL_CYCLES_TP = 4, - PERF_SP_STALL_CYCLES_UCHE = 5, - PERF_SP_STALL_CYCLES_RB = 6, - PERF_SP_SCHEDULER_NON_WORKING = 7, - PERF_SP_WAVE_CONTEXTS = 8, - PERF_SP_WAVE_CONTEXT_CYCLES = 9, - PERF_SP_FS_STAGE_WAVE_CYCLES = 10, - PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, - PERF_SP_VS_STAGE_WAVE_CYCLES = 12, - PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, - PERF_SP_FS_STAGE_DURATION_CYCLES = 14, - PERF_SP_VS_STAGE_DURATION_CYCLES = 15, - PERF_SP_WAVE_CTRL_CYCLES = 16, - PERF_SP_WAVE_LOAD_CYCLES = 17, - PERF_SP_WAVE_EMIT_CYCLES = 18, - PERF_SP_WAVE_NOP_CYCLES = 19, - PERF_SP_WAVE_WAIT_CYCLES = 20, - PERF_SP_WAVE_FETCH_CYCLES = 21, - PERF_SP_WAVE_IDLE_CYCLES = 22, - PERF_SP_WAVE_END_CYCLES = 23, - PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, - PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, - PERF_SP_WAVE_JOIN_CYCLES = 26, - PERF_SP_LM_LOAD_INSTRUCTIONS = 27, - PERF_SP_LM_STORE_INSTRUCTIONS = 28, - PERF_SP_LM_ATOMICS = 29, - PERF_SP_GM_LOAD_INSTRUCTIONS = 30, - PERF_SP_GM_STORE_INSTRUCTIONS = 31, - PERF_SP_GM_ATOMICS = 32, - PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, - PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34, - PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35, - PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36, - PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37, - PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38, - PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39, - PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40, - PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41, - PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42, - PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43, - PERF_SP_VS_INSTRUCTIONS = 44, - PERF_SP_FS_INSTRUCTIONS = 45, - PERF_SP_ADDR_LOCK_COUNT = 46, - PERF_SP_UCHE_READ_TRANS = 47, - PERF_SP_UCHE_WRITE_TRANS = 48, - PERF_SP_EXPORT_VPC_TRANS = 49, - PERF_SP_EXPORT_RB_TRANS = 50, - PERF_SP_PIXELS_KILLED = 51, - PERF_SP_ICL1_REQUESTS = 52, - PERF_SP_ICL1_MISSES = 53, - PERF_SP_ICL0_REQUESTS = 54, - PERF_SP_ICL0_MISSES = 55, - PERF_SP_HS_INSTRUCTIONS = 56, - PERF_SP_DS_INSTRUCTIONS = 57, - PERF_SP_GS_INSTRUCTIONS = 58, - PERF_SP_CS_INSTRUCTIONS = 59, - PERF_SP_GPR_READ = 60, - PERF_SP_GPR_WRITE = 61, - PERF_SP_LM_CH0_REQUESTS = 62, - PERF_SP_LM_CH1_REQUESTS = 63, - PERF_SP_LM_BANK_CONFLICTS = 64, -}; - -enum a5xx_rb_perfcounter_select { - PERF_RB_BUSY_CYCLES = 0, - PERF_RB_STALL_CYCLES_CCU = 1, - PERF_RB_STALL_CYCLES_HLSQ = 2, - PERF_RB_STALL_CYCLES_FIFO0_FULL = 3, - PERF_RB_STALL_CYCLES_FIFO1_FULL = 4, - PERF_RB_STALL_CYCLES_FIFO2_FULL = 5, - PERF_RB_STARVE_CYCLES_SP = 6, - PERF_RB_STARVE_CYCLES_LRZ_TILE = 7, - PERF_RB_STARVE_CYCLES_CCU = 8, - PERF_RB_STARVE_CYCLES_Z_PLANE = 9, - PERF_RB_STARVE_CYCLES_BARY_PLANE = 10, - PERF_RB_Z_WORKLOAD = 11, - PERF_RB_HLSQ_ACTIVE = 12, - PERF_RB_Z_READ = 13, - PERF_RB_Z_WRITE = 14, - PERF_RB_C_READ = 15, - PERF_RB_C_WRITE = 16, - PERF_RB_TOTAL_PASS = 17, - PERF_RB_Z_PASS = 18, - PERF_RB_Z_FAIL = 19, - PERF_RB_S_FAIL = 20, - PERF_RB_BLENDED_FXP_COMPONENTS = 21, - PERF_RB_BLENDED_FP16_COMPONENTS = 22, - RB_RESERVED = 23, - PERF_RB_2D_ALIVE_CYCLES = 24, - PERF_RB_2D_STALL_CYCLES_A2D = 25, - PERF_RB_2D_STARVE_CYCLES_SRC = 26, - PERF_RB_2D_STARVE_CYCLES_SP = 27, - PERF_RB_2D_STARVE_CYCLES_DST = 28, - PERF_RB_2D_VALID_PIXELS = 29, -}; - -enum a5xx_rb_samples_perfcounter_select { - TOTAL_SAMPLES = 0, - ZPASS_SAMPLES = 1, - ZFAIL_SAMPLES = 2, - SFAIL_SAMPLES = 3, -}; - -enum a5xx_vsc_perfcounter_select { - PERF_VSC_BUSY_CYCLES = 0, - PERF_VSC_WORKING_CYCLES = 1, - PERF_VSC_STALL_CYCLES_UCHE = 2, - PERF_VSC_EOT_NUM = 3, -}; - -enum a5xx_ccu_perfcounter_select { - PERF_CCU_BUSY_CYCLES = 0, - PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, - PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, - PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, - PERF_CCU_DEPTH_BLOCKS = 4, - PERF_CCU_COLOR_BLOCKS = 5, - PERF_CCU_DEPTH_BLOCK_HIT = 6, - PERF_CCU_COLOR_BLOCK_HIT = 7, - PERF_CCU_PARTIAL_BLOCK_READ = 8, - PERF_CCU_GMEM_READ = 9, - PERF_CCU_GMEM_WRITE = 10, - PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, - PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, - PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, - PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, - PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, - PERF_CCU_COLOR_READ_FLAG0_COUNT = 16, - PERF_CCU_COLOR_READ_FLAG1_COUNT = 17, - PERF_CCU_COLOR_READ_FLAG2_COUNT = 18, - PERF_CCU_COLOR_READ_FLAG3_COUNT = 19, - PERF_CCU_COLOR_READ_FLAG4_COUNT = 20, - PERF_CCU_2D_BUSY_CYCLES = 21, - PERF_CCU_2D_RD_REQ = 22, - PERF_CCU_2D_WR_REQ = 23, - PERF_CCU_2D_REORDER_STARVE_CYCLES = 24, - PERF_CCU_2D_PIXELS = 25, -}; - -enum a5xx_cmp_perfcounter_select { - PERF_CMPDECMP_STALL_CYCLES_VBIF = 0, - PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, - PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, - PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, - PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, - PERF_CMPDECMP_VBIF_READ_REQUEST = 5, - PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, - PERF_CMPDECMP_VBIF_READ_DATA = 7, - PERF_CMPDECMP_VBIF_WRITE_DATA = 8, - PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, - PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, - PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, - PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, - PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, - PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, - PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15, - PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16, - PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17, - PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18, - PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19, - PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20, - PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21, - PERF_CMPDECMP_2D_RD_DATA = 22, - PERF_CMPDECMP_2D_WR_DATA = 23, -}; - -enum a5xx_vbif_perfcounter_select { - AXI_READ_REQUESTS_ID_0 = 0, - AXI_READ_REQUESTS_ID_1 = 1, - AXI_READ_REQUESTS_ID_2 = 2, - AXI_READ_REQUESTS_ID_3 = 3, - AXI_READ_REQUESTS_ID_4 = 4, - AXI_READ_REQUESTS_ID_5 = 5, - AXI_READ_REQUESTS_ID_6 = 6, - AXI_READ_REQUESTS_ID_7 = 7, - AXI_READ_REQUESTS_ID_8 = 8, - AXI_READ_REQUESTS_ID_9 = 9, - AXI_READ_REQUESTS_ID_10 = 10, - AXI_READ_REQUESTS_ID_11 = 11, - AXI_READ_REQUESTS_ID_12 = 12, - AXI_READ_REQUESTS_ID_13 = 13, - AXI_READ_REQUESTS_ID_14 = 14, - AXI_READ_REQUESTS_ID_15 = 15, - AXI0_READ_REQUESTS_TOTAL = 16, - AXI1_READ_REQUESTS_TOTAL = 17, - AXI2_READ_REQUESTS_TOTAL = 18, - AXI3_READ_REQUESTS_TOTAL = 19, - AXI_READ_REQUESTS_TOTAL = 20, - AXI_WRITE_REQUESTS_ID_0 = 21, - AXI_WRITE_REQUESTS_ID_1 = 22, - AXI_WRITE_REQUESTS_ID_2 = 23, - AXI_WRITE_REQUESTS_ID_3 = 24, - AXI_WRITE_REQUESTS_ID_4 = 25, - AXI_WRITE_REQUESTS_ID_5 = 26, - AXI_WRITE_REQUESTS_ID_6 = 27, - AXI_WRITE_REQUESTS_ID_7 = 28, - AXI_WRITE_REQUESTS_ID_8 = 29, - AXI_WRITE_REQUESTS_ID_9 = 30, - AXI_WRITE_REQUESTS_ID_10 = 31, - AXI_WRITE_REQUESTS_ID_11 = 32, - AXI_WRITE_REQUESTS_ID_12 = 33, - AXI_WRITE_REQUESTS_ID_13 = 34, - AXI_WRITE_REQUESTS_ID_14 = 35, - AXI_WRITE_REQUESTS_ID_15 = 36, - AXI0_WRITE_REQUESTS_TOTAL = 37, - AXI1_WRITE_REQUESTS_TOTAL = 38, - AXI2_WRITE_REQUESTS_TOTAL = 39, - AXI3_WRITE_REQUESTS_TOTAL = 40, - AXI_WRITE_REQUESTS_TOTAL = 41, - AXI_TOTAL_REQUESTS = 42, - AXI_READ_DATA_BEATS_ID_0 = 43, - AXI_READ_DATA_BEATS_ID_1 = 44, - AXI_READ_DATA_BEATS_ID_2 = 45, - AXI_READ_DATA_BEATS_ID_3 = 46, - AXI_READ_DATA_BEATS_ID_4 = 47, - AXI_READ_DATA_BEATS_ID_5 = 48, - AXI_READ_DATA_BEATS_ID_6 = 49, - AXI_READ_DATA_BEATS_ID_7 = 50, - AXI_READ_DATA_BEATS_ID_8 = 51, - AXI_READ_DATA_BEATS_ID_9 = 52, - AXI_READ_DATA_BEATS_ID_10 = 53, - AXI_READ_DATA_BEATS_ID_11 = 54, - AXI_READ_DATA_BEATS_ID_12 = 55, - AXI_READ_DATA_BEATS_ID_13 = 56, - AXI_READ_DATA_BEATS_ID_14 = 57, - AXI_READ_DATA_BEATS_ID_15 = 58, - AXI0_READ_DATA_BEATS_TOTAL = 59, - AXI1_READ_DATA_BEATS_TOTAL = 60, - AXI2_READ_DATA_BEATS_TOTAL = 61, - AXI3_READ_DATA_BEATS_TOTAL = 62, - AXI_READ_DATA_BEATS_TOTAL = 63, - AXI_WRITE_DATA_BEATS_ID_0 = 64, - AXI_WRITE_DATA_BEATS_ID_1 = 65, - AXI_WRITE_DATA_BEATS_ID_2 = 66, - AXI_WRITE_DATA_BEATS_ID_3 = 67, - AXI_WRITE_DATA_BEATS_ID_4 = 68, - AXI_WRITE_DATA_BEATS_ID_5 = 69, - AXI_WRITE_DATA_BEATS_ID_6 = 70, - AXI_WRITE_DATA_BEATS_ID_7 = 71, - AXI_WRITE_DATA_BEATS_ID_8 = 72, - AXI_WRITE_DATA_BEATS_ID_9 = 73, - AXI_WRITE_DATA_BEATS_ID_10 = 74, - AXI_WRITE_DATA_BEATS_ID_11 = 75, - AXI_WRITE_DATA_BEATS_ID_12 = 76, - AXI_WRITE_DATA_BEATS_ID_13 = 77, - AXI_WRITE_DATA_BEATS_ID_14 = 78, - AXI_WRITE_DATA_BEATS_ID_15 = 79, - AXI0_WRITE_DATA_BEATS_TOTAL = 80, - AXI1_WRITE_DATA_BEATS_TOTAL = 81, - AXI2_WRITE_DATA_BEATS_TOTAL = 82, - AXI3_WRITE_DATA_BEATS_TOTAL = 83, - AXI_WRITE_DATA_BEATS_TOTAL = 84, - AXI_DATA_BEATS_TOTAL = 85, -}; - -enum a5xx_tex_filter { - A5XX_TEX_NEAREST = 0, - A5XX_TEX_LINEAR = 1, - A5XX_TEX_ANISO = 2, -}; - -enum a5xx_tex_clamp { - A5XX_TEX_REPEAT = 0, - A5XX_TEX_CLAMP_TO_EDGE = 1, - A5XX_TEX_MIRROR_REPEAT = 2, - A5XX_TEX_CLAMP_TO_BORDER = 3, - A5XX_TEX_MIRROR_CLAMP = 4, -}; - -enum a5xx_tex_aniso { - A5XX_TEX_ANISO_1 = 0, - A5XX_TEX_ANISO_2 = 1, - A5XX_TEX_ANISO_4 = 2, - A5XX_TEX_ANISO_8 = 3, - A5XX_TEX_ANISO_16 = 4, -}; - -enum a5xx_tex_swiz { - A5XX_TEX_X = 0, - A5XX_TEX_Y = 1, - A5XX_TEX_Z = 2, - A5XX_TEX_W = 3, - A5XX_TEX_ZERO = 4, - A5XX_TEX_ONE = 5, -}; - -enum a5xx_tex_type { - A5XX_TEX_1D = 0, - A5XX_TEX_2D = 1, - A5XX_TEX_CUBE = 2, - A5XX_TEX_3D = 3, -}; - -#define A5XX_INT0_RBBM_GPU_IDLE 0x00000001 -#define A5XX_INT0_RBBM_AHB_ERROR 0x00000002 -#define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004 -#define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 -#define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 -#define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020 -#define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 -#define A5XX_INT0_RBBM_GPC_ERROR 0x00000080 -#define A5XX_INT0_CP_SW 0x00000100 -#define A5XX_INT0_CP_HW_ERROR 0x00000200 -#define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400 -#define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800 -#define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000 -#define A5XX_INT0_CP_IB2 0x00002000 -#define A5XX_INT0_CP_IB1 0x00004000 -#define A5XX_INT0_CP_RB 0x00008000 -#define A5XX_INT0_CP_UNUSED_1 0x00010000 -#define A5XX_INT0_CP_RB_DONE_TS 0x00020000 -#define A5XX_INT0_CP_WT_DONE_TS 0x00040000 -#define A5XX_INT0_UNKNOWN_1 0x00080000 -#define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000 -#define A5XX_INT0_UNUSED_2 0x00200000 -#define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000 -#define A5XX_INT0_MISC_HANG_DETECT 0x00800000 -#define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000 -#define A5XX_INT0_UCHE_TRAP_INTR 0x02000000 -#define A5XX_INT0_DEBBUS_INTR_0 0x04000000 -#define A5XX_INT0_DEBBUS_INTR_1 0x08000000 -#define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000 -#define A5XX_INT0_GPMU_FIRMWARE 0x20000000 -#define A5XX_INT0_ISDB_CPU_IRQ 0x40000000 -#define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000 -#define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001 -#define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002 -#define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 -#define A5XX_CP_INT_CP_DMA_ERROR 0x00000008 -#define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 -#define A5XX_CP_INT_CP_AHB_ERROR 0x00000020 -#define REG_A5XX_CP_RB_BASE 0x00000800 - -#define REG_A5XX_CP_RB_BASE_HI 0x00000801 - -#define REG_A5XX_CP_RB_CNTL 0x00000802 - -#define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804 - -#define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805 - -#define REG_A5XX_CP_RB_RPTR 0x00000806 - -#define REG_A5XX_CP_RB_WPTR 0x00000807 - -#define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808 - -#define REG_A5XX_CP_PFP_STAT_DATA 0x00000809 - -#define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b - -#define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c - -#define REG_A5XX_CP_ME_NRT_ADDR_LO 0x0000080d - -#define REG_A5XX_CP_ME_NRT_ADDR_HI 0x0000080e - -#define REG_A5XX_CP_ME_NRT_DATA 0x00000810 - -#define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817 - -#define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818 - -#define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819 - -#define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a - -#define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f - -#define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820 - -#define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821 - -#define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822 - -#define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823 - -#define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824 - -#define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825 - -#define REG_A5XX_CP_MERCIU_SIZE 0x00000826 - -#define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827 - -#define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828 - -#define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829 - -#define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a - -#define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b - -#define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f - -#define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830 - -#define REG_A5XX_CP_CNTL 0x00000831 - -#define REG_A5XX_CP_PFP_ME_CNTL 0x00000832 - -#define REG_A5XX_CP_CHICKEN_DBG 0x00000833 - -#define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835 - -#define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836 - -#define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838 - -#define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839 - -#define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b - -#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c - -#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d - -#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e - -#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f - -#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840 - -#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841 - -#define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860 - -#define REG_A5XX_CP_ME_STAT_DATA 0x00000b14 - -#define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15 - -#define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18 - -#define REG_A5XX_CP_HW_FAULT 0x00000b1a - -#define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c - -#define REG_A5XX_CP_IB1_BASE 0x00000b1f - -#define REG_A5XX_CP_IB1_BASE_HI 0x00000b20 - -#define REG_A5XX_CP_IB1_BUFSZ 0x00000b21 - -#define REG_A5XX_CP_IB2_BASE 0x00000b22 - -#define REG_A5XX_CP_IB2_BASE_HI 0x00000b23 - -#define REG_A5XX_CP_IB2_BUFSZ 0x00000b24 - -static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } - -static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } - -static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } - -static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } -#define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff -#define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 -static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) -{ - return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; -} -#define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 -#define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 -static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) -{ - return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; -} -#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 -#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000 - -#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0 - -#define REG_A5XX_CP_AHB_FAULT 0x00000b1b - -#define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0 - -#define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1 - -#define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2 - -#define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3 - -#define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4 - -#define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5 - -#define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6 - -#define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7 - -#define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1 - -#define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba - -#define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb - -#define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc - -#define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd - -#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004 - -#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005 - -#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006 - -#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007 - -#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008 - -#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009 - -#define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018 - -#define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a - -#define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b - -#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c - -#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d - -#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e - -#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f - -#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010 - -#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011 - -#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012 - -#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013 - -#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014 - -#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015 - -#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016 - -#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017 - -#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018 - -#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019 - -#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a - -#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b - -#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c - -#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d - -#define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e - -#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f - -#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020 - -#define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021 - -#define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022 - -#define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023 - -#define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024 - -#define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f - -#define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037 - -#define REG_A5XX_RBBM_INT_0_MASK 0x00000038 -#define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 -#define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002 -#define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004 -#define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008 -#define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010 -#define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020 -#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 -#define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 -#define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100 -#define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 -#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 -#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 -#define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 -#define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 -#define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 -#define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000 -#define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 -#define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 -#define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 -#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 -#define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000 -#define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 -#define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 -#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 -#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 -#define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000 -#define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000 -#define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 -#define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 - -#define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f - -#define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041 - -#define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043 - -#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 - -#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 - -#define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048 - -#define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049 - -#define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a - -#define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b - -#define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c - -#define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d - -#define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e - -#define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f - -#define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050 - -#define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051 - -#define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052 - -#define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053 - -#define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054 - -#define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055 - -#define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059 - -#define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a - -#define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b - -#define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c - -#define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d - -#define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e - -#define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f - -#define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060 - -#define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061 - -#define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062 - -#define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063 - -#define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064 - -#define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065 - -#define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066 - -#define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067 - -#define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068 - -#define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069 - -#define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a - -#define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b - -#define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c - -#define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d - -#define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e - -#define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f - -#define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070 - -#define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071 - -#define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072 - -#define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073 - -#define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074 - -#define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075 - -#define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076 - -#define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077 - -#define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078 - -#define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079 - -#define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a - -#define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b - -#define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c - -#define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d - -#define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e - -#define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f - -#define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080 - -#define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081 - -#define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082 - -#define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083 - -#define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084 - -#define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085 - -#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086 - -#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087 - -#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088 - -#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089 - -#define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a - -#define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b - -#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c - -#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d - -#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e - -#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f - -#define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090 - -#define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091 - -#define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092 - -#define REG_A5XX_RBBM_AHB_CNTL0 0x00000093 - -#define REG_A5XX_RBBM_AHB_CNTL1 0x00000094 - -#define REG_A5XX_RBBM_AHB_CNTL2 0x00000095 - -#define REG_A5XX_RBBM_AHB_CMD 0x00000096 - -#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c - -#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d - -#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e - -#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f - -#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0 - -#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1 - -#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2 - -#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3 - -#define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4 - -#define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5 - -#define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6 - -#define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7 - -#define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8 - -#define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9 - -#define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa - -#define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab - -#define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac - -#define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad - -#define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae - -#define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af - -#define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0 - -#define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1 - -#define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2 - -#define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3 - -#define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4 - -#define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5 - -#define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6 - -#define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7 - -#define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8 - -#define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9 - -#define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba - -#define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb - -#define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8 - -#define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9 - -#define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca - -#define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0 - -#define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1 - -#define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2 - -#define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3 - -#define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4 - -#define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5 - -#define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6 - -#define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7 - -#define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8 - -#define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9 - -#define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa - -#define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab - -#define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac - -#define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad - -#define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae - -#define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af - -#define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0 - -#define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1 - -#define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2 - -#define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3 - -#define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4 - -#define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5 - -#define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6 - -#define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7 - -#define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8 - -#define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9 - -#define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba - -#define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb - -#define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc - -#define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd - -#define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be - -#define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf - -#define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0 - -#define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1 - -#define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2 - -#define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3 - -#define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4 - -#define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5 - -#define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6 - -#define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7 - -#define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8 - -#define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9 - -#define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca - -#define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb - -#define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc - -#define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd - -#define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce - -#define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf - -#define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0 - -#define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1 - -#define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2 - -#define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3 - -#define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4 - -#define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5 - -#define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6 - -#define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6 - -#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7 - -#define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8 - -#define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9 - -#define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea - -#define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb - -#define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec - -#define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed - -#define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee - -#define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef - -#define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0 - -#define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1 - -#define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2 - -#define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3 - -#define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4 - -#define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5 - -#define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6 - -#define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7 - -#define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8 - -#define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9 - -#define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa - -#define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb - -#define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc - -#define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd - -#define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe - -#define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff - -#define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400 - -#define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401 - -#define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402 - -#define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403 - -#define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404 - -#define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405 - -#define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406 - -#define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a - -#define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b - -#define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c - -#define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d - -#define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e - -#define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f - -#define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416 - -#define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417 - -#define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418 - -#define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419 - -#define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a - -#define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b - -#define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c - -#define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d - -#define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e - -#define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f - -#define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420 - -#define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421 - -#define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422 - -#define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423 - -#define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424 - -#define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425 - -#define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426 - -#define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427 - -#define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428 - -#define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429 - -#define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a - -#define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b - -#define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c - -#define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d - -#define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e - -#define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f - -#define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430 - -#define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431 - -#define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432 - -#define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433 - -#define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434 - -#define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435 - -#define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436 - -#define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437 - -#define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438 - -#define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439 - -#define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a - -#define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b - -#define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c - -#define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d - -#define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e - -#define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f - -#define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440 - -#define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441 - -#define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442 - -#define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443 - -#define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444 - -#define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445 - -#define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446 - -#define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447 - -#define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448 - -#define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449 - -#define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a - -#define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b - -#define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c - -#define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d - -#define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e - -#define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f - -#define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450 - -#define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451 - -#define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452 - -#define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453 - -#define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454 - -#define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455 - -#define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456 - -#define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457 - -#define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458 - -#define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459 - -#define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a - -#define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b - -#define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c - -#define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d - -#define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e - -#define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f - -#define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460 - -#define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461 - -#define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462 - -#define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463 - -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b - -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c - -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d - -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e - -#define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2 - -#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3 - -#define REG_A5XX_RBBM_STATUS 0x000004f5 -#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000 -#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000 -#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 -#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000 -#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000 -#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000 -#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000 -#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000 -#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000 -#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000 -#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000 -#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 -#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 -#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000 -#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000 -#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000 -#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000 -#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000 -#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000 -#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000 -#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800 -#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400 -#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200 -#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100 -#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080 -#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040 -#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020 -#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010 -#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008 -#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 -#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 -#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001 - -#define REG_A5XX_RBBM_STATUS3 0x00000530 - -#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1 - -#define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0 - -#define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1 - -#define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3 - -#define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4 - -#define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464 - -#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465 - -#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466 - -#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467 - -#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468 - -#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469 - -#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a - -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b - -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c - -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d - -#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e - -#define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f - -#define REG_A5XX_RBBM_AHB_ERROR 0x000004ed - -#define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504 - -#define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505 - -#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506 - -#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507 - -#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508 - -#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509 - -#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a - -#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b - -#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c - -#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d - -#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e - -#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f - -#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510 - -#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511 - -#define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512 - -#define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513 - -#define REG_A5XX_RBBM_ISDB_CNT 0x00000533 - -#define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000 - -#define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 - -#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 - -#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 - -#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 - -#define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803 - -#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804 - -#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805 - -#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806 - -#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807 - -#define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 - -#define REG_A5XX_VSC_BIN_SIZE 0x00000bc2 -#define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff -#define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 -static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; -} -#define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00 -#define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9 -static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; -} - -#define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3 - -#define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4 - -#define REG_A5XX_UNKNOWN_0BC5 0x00000bc5 - -#define REG_A5XX_UNKNOWN_0BC6 0x00000bc6 - -static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } - -static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } -#define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff -#define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 -static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) -{ - return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK; -} -#define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 -#define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 -static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) -{ - return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK; -} -#define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 -#define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 -static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) -{ - return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK; -} -#define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 -#define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 -static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) -{ - return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK; -} - -static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } - -static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; } - -static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; } - -static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } - -static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; } - -#define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60 - -#define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61 - -#define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd -#define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff -#define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0 -static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val) -{ - return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK; -} -#define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000 -#define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16 -static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) -{ - return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK; -} - -#define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81 - -#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90 - -#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91 - -#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92 - -#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93 - -#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94 - -#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95 - -#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96 - -#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97 - -#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98 - -#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99 - -#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a - -#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b - -#define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4 - -#define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5 - -#define REG_A5XX_RB_MODE_CNTL 0x00000cc6 - -#define REG_A5XX_RB_CCU_CNTL 0x00000cc7 - -#define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0 - -#define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1 - -#define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2 - -#define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3 - -#define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4 - -#define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5 - -#define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6 - -#define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7 - -#define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8 - -#define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9 - -#define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda - -#define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb - -#define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0 - -#define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1 - -#define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2 - -#define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3 - -#define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4 - -#define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5 - -#define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec - -#define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced - -#define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee - -#define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef - -#define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00 -#define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100 - -#define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01 - -#define REG_A5XX_PC_MODE_CNTL 0x00000d02 - -#define REG_A5XX_PC_INDEX_BUF_LO 0x00000d04 - -#define REG_A5XX_PC_INDEX_BUF_HI 0x00000d05 - -#define REG_A5XX_PC_START_INDEX 0x00000d06 - -#define REG_A5XX_PC_MAX_INDEX 0x00000d07 - -#define REG_A5XX_PC_TESSFACTOR_ADDR_LO 0x00000d08 - -#define REG_A5XX_PC_TESSFACTOR_ADDR_HI 0x00000d09 - -#define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10 - -#define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11 - -#define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12 - -#define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13 - -#define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14 - -#define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15 - -#define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16 - -#define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17 - -#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00 - -#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01 - -#define REG_A5XX_HLSQ_DBG_ECO_CNTL 0x00000e04 - -#define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05 - -#define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06 - -#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10 - -#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11 - -#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12 - -#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13 - -#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14 - -#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15 - -#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16 - -#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17 - -#define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08 - -#define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00 - -#define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000 - -#define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41 - -#define REG_A5XX_VFD_MODE_CNTL 0x00000e42 - -#define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50 - -#define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51 - -#define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52 - -#define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53 - -#define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54 - -#define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55 - -#define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56 - -#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57 - -#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60 - -#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61 - -#define REG_A5XX_VPC_MODE_CNTL 0x00000e62 -#define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001 - -#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64 - -#define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65 - -#define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66 - -#define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67 - -#define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 - -#define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 - -#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 - -#define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88 - -#define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89 - -#define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a - -#define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b - -#define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c - -#define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d - -#define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e - -#define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f - -#define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90 - -#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91 - -#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92 - -#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93 - -#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94 - -#define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95 - -#define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96 - -#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0 - -#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1 - -#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2 - -#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3 - -#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4 - -#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5 - -#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6 - -#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7 - -#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8 - -#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9 - -#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa - -#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab - -#define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1 - -#define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2 - -#define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0 - -#define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1 - -#define REG_A5XX_SP_MODE_CNTL 0x00000ec2 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9 - -#define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda - -#define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb - -#define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc - -#define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd - -#define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede - -#define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf - -#define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01 - -#define REG_A5XX_TPL1_MODE_CNTL 0x00000f02 - -#define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10 - -#define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11 - -#define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12 - -#define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13 - -#define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14 - -#define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15 - -#define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16 - -#define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17 - -#define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18 - -#define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19 - -#define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a - -#define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b - -#define REG_A5XX_VBIF_VERSION 0x00003000 - -#define REG_A5XX_VBIF_CLKON 0x00003001 - -#define REG_A5XX_VBIF_ABIT_SORT 0x00003028 - -#define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029 - -#define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 - -#define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a - -#define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c - -#define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d - -#define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080 - -#define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081 - -#define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 - -#define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085 - -#define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086 - -#define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087 - -#define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088 - -#define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c - -#define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0 - -#define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1 - -#define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2 - -#define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3 - -#define REG_A5XX_VBIF_PERF_CNT_CLR0 0x000030c8 - -#define REG_A5XX_VBIF_PERF_CNT_CLR1 0x000030c9 - -#define REG_A5XX_VBIF_PERF_CNT_CLR2 0x000030ca - -#define REG_A5XX_VBIF_PERF_CNT_CLR3 0x000030cb - -#define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0 - -#define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1 - -#define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2 - -#define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3 - -#define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8 - -#define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9 - -#define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da - -#define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db - -#define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0 - -#define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1 - -#define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2 - -#define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3 - -#define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 - -#define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 - -#define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 - -#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 - -#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 - -#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 - -#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 - -#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 - -#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a - -#define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800 - -#define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800 - -#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881 - -#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886 - -#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887 - -#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b -#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000 - -#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d -#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000 - -#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891 - -#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892 - -#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893 - -#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894 - -#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 - -#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1 - -#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6 - -#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8 - -#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0 - -#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1 - -#define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840 - -#define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841 - -#define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842 - -#define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843 - -#define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844 - -#define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845 - -#define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846 - -#define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847 - -#define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848 - -#define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849 - -#define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a - -#define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b - -#define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c - -#define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d - -#define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e - -#define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f - -#define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850 - -#define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851 - -#define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852 - -#define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853 - -#define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854 - -#define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855 - -#define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856 - -#define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857 - -#define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858 - -#define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859 - -#define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a - -#define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b - -#define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c - -#define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d - -#define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e - -#define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f - -#define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860 - -#define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861 - -#define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862 - -#define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863 - -#define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864 - -#define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865 - -#define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866 - -#define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867 - -#define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868 - -#define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869 - -#define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a - -#define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b - -#define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c - -#define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d - -#define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e - -#define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f - -#define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870 - -#define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871 - -#define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872 - -#define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873 - -#define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874 - -#define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875 - -#define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876 - -#define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877 - -#define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878 - -#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879 - -#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a - -#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b - -#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c - -#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d - -#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 - -#define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8 - -#define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00 - -#define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01 - -#define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02 - -#define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03 - -#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05 - -#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06 - -#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40 - -#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41 - -#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42 - -#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43 - -#define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46 - -#define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60 - -#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61 - -#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62 - -#define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80 - -#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4 - -#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5 - -#define REG_A5XX_GDPM_CONFIG1 0x0000b80c - -#define REG_A5XX_GDPM_CONFIG2 0x0000b80d - -#define REG_A5XX_GDPM_INT_EN 0x0000b80f - -#define REG_A5XX_GDPM_INT_MASK 0x0000b811 - -#define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0 - -#define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a - -#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d - -#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f - -#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421 - -#define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520 - -#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557 - -#define REG_A5XX_GRAS_CL_CNTL 0x0000e000 -#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 - -#define REG_A5XX_UNKNOWN_E001 0x0000e001 - -#define REG_A5XX_UNKNOWN_E004 0x0000e004 - -#define REG_A5XX_GRAS_CNTL 0x0000e005 -#define A5XX_GRAS_CNTL_VARYING 0x00000001 -#define A5XX_GRAS_CNTL_UNK3 0x00000008 -#define A5XX_GRAS_CNTL_XCOORD 0x00000040 -#define A5XX_GRAS_CNTL_YCOORD 0x00000080 -#define A5XX_GRAS_CNTL_ZCOORD 0x00000100 -#define A5XX_GRAS_CNTL_WCOORD 0x00000200 - -#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006 -#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff -#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 -static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) -{ - return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; -} -#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 -#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 -static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) -{ - return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; -} - -#define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010 -#define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff -#define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 -static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) -{ - return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK; -} - -#define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011 -#define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff -#define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 -static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) -{ - return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK; -} - -#define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012 -#define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff -#define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 -static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) -{ - return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK; -} - -#define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013 -#define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff -#define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 -static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) -{ - return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK; -} - -#define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014 -#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff -#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 -static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) -{ - return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; -} - -#define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015 -#define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff -#define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 -static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) -{ - return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK; -} - -#define REG_A5XX_GRAS_SU_CNTL 0x0000e090 -#define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 -#define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 -#define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 -#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 -#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 -static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) -{ - return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; -} -#define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 -#define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 - -#define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091 -#define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff -#define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 -static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) -{ - return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK; -} -#define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 -#define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 -static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) -{ - return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK; -} - -#define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092 -#define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff -#define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0 -static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) -{ - return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK; -} - -#define REG_A5XX_GRAS_SU_LAYERED 0x0000e093 - -#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094 -#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 -#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002 - -#define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095 -#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff -#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 -static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) -{ - return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; -} - -#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096 -#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff -#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 -static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) -{ - return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; -} - -#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097 -#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff -#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 -static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) -{ - return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; -} - -#define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098 -#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 -#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 -static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) -{ - return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; -} - -#define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099 - -#define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0 -#define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001 -#define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000 - -#define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1 - -#define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2 -#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK; -} - -#define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3 -#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK; -} -#define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 - -#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4 - -#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa -#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff -#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 -static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; -} -#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 -#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 -static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; -} - -#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab -#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff -#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 -static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; -} -#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 -#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 -static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; -} - -#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 -static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; -} -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 -static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; -} - -#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 -static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; -} -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 -#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 -static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; -} - -#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea -#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff -#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 -static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; -} -#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 -#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 -static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; -} - -#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb -#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff -#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 -static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; -} -#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 -#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 -static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) -{ - return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; -} - -#define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100 -#define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 -#define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 -#define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004 - -#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101 - -#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102 - -#define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103 -#define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff -#define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0 -static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK; -} - -#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104 - -#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105 - -#define REG_A5XX_RB_CNTL 0x0000e140 -#define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff -#define A5XX_RB_CNTL_WIDTH__SHIFT 0 -static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; -} -#define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00 -#define A5XX_RB_CNTL_HEIGHT__SHIFT 9 -static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; -} -#define A5XX_RB_CNTL_BYPASS 0x00020000 - -#define REG_A5XX_RB_RENDER_CNTL 0x0000e141 -#define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001 -#define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040 -#define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080 -#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 -#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000 -#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 -#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 -static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; -} -#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000 -#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24 -static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK; -} - -#define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142 -#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; -} - -#define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143 -#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; -} -#define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 - -#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144 -#define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001 -#define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008 -#define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 -#define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 -#define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 -#define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 - -#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145 -#define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 -#define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002 -#define A5XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000004 - -#define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146 -#define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f -#define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0 -static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) -{ - return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK; -} -#define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020 - -#define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147 -#define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f -#define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 -static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK; -} -#define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 -#define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 -static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK; -} -#define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 -#define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 -static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK; -} -#define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 -#define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 -static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK; -} -#define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 -#define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 -static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK; -} -#define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 -#define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 -static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK; -} -#define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 -#define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 -static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK; -} -#define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 -#define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 -static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) -{ - return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK; -} - -static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } - -static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } -#define A5XX_RB_MRT_CONTROL_BLEND 0x00000001 -#define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002 -#define A5XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 -#define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 -#define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 -static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) -{ - return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK; -} -#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 -#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 -static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) -{ - return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; -} - -static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; } -#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f -#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 -static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; -} -#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 -#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 -static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; -} -#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 -#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 -static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; -} -#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 -#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 -static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; -} -#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 -#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 -static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; -} -#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 -#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 -static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; -} - -static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; } -#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) -{ - return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; -} -#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 -#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 -static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) -{ - return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; -} -#define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00001800 -#define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 11 -static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) -{ - return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; -} -#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 -#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 -static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; -} -#define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000 - -static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; } -#define A5XX_RB_MRT_PITCH__MASK 0xffffffff -#define A5XX_RB_MRT_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; -} - -static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } -#define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff -#define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; -} - -static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } - -static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; } - -#define REG_A5XX_RB_BLEND_RED 0x0000e1a0 -#define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff -#define A5XX_RB_BLEND_RED_UINT__SHIFT 0 -static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK; -} -#define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 -#define A5XX_RB_BLEND_RED_SINT__SHIFT 8 -static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK; -} -#define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 -#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16 -static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; -} - -#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1 -#define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff -#define A5XX_RB_BLEND_RED_F32__SHIFT 0 -static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) -{ - return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK; -} - -#define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2 -#define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff -#define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0 -static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK; -} -#define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 -#define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8 -static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK; -} -#define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 -#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 -static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; -} - -#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3 -#define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff -#define A5XX_RB_BLEND_GREEN_F32__SHIFT 0 -static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) -{ - return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK; -} - -#define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4 -#define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff -#define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0 -static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK; -} -#define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 -#define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8 -static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK; -} -#define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 -#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 -static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; -} - -#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5 -#define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff -#define A5XX_RB_BLEND_BLUE_F32__SHIFT 0 -static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) -{ - return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK; -} - -#define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6 -#define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff -#define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0 -static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK; -} -#define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 -#define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8 -static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK; -} -#define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 -#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 -static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) -{ - return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; -} - -#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7 -#define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff -#define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0 -static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) -{ - return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK; -} - -#define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8 -#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff -#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 -static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) -{ - return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; -} -#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 -#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 -#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 -static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) -{ - return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; -} - -#define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9 -#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff -#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 -static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; -} -#define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 -#define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 -#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 -#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 -static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) -{ - return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; -} - -#define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0 -#define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 -#define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002 - -#define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1 -#define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 -#define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 -#define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c -#define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 -static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) -{ - return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK; -} -#define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 - -#define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2 -#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 -#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 -static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) -{ - return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; -} - -#define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3 - -#define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4 - -#define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5 -#define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff -#define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; -} - -#define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6 -#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff -#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; -} - -#define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0 -#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 -#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 -#define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 -#define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 -#define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 -static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) -{ - return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK; -} -#define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 -#define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 -static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) -{ - return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK; -} -#define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 -#define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 -static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) -{ - return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK; -} -#define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 -#define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 -static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) -{ - return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK; -} -#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 -#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 -static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) -{ - return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; -} -#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 -#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 -static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; -} -#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 -#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 -static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) -{ - return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; -} -#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 -#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 -static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; -} - -#define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1 -#define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 - -#define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2 - -#define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3 - -#define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4 -#define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff -#define A5XX_RB_STENCIL_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; -} - -#define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5 -#define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff -#define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; -} - -#define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6 -#define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff -#define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 -static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) -{ - return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK; -} -#define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 -#define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 -static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) -{ - return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK; -} -#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 -#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 -static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) -{ - return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; -} - -#define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7 -#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff -#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 -static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) -{ - return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; -} -#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 -#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 -static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) -{ - return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; -} -#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 -#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 -static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) -{ - return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; -} - -#define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0 -#define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff -#define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0 -static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) -{ - return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK; -} -#define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 -#define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16 -static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) -{ - return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1 -#define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 - -#define REG_A5XX_RB_BLIT_CNTL 0x0000e210 -#define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f -#define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0 -static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) -{ - return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK; -} - -#define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211 -#define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff -#define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0 -static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) -{ - return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK; -} -#define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 -#define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16 -static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) -{ - return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK; -} - -#define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212 -#define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 -#define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff -#define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0 -static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) -{ - return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK; -} -#define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 -#define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16 -static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) -{ - return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK; -} - -#define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213 -#define A5XX_RB_RESOLVE_CNTL_3_TILED 0x00000001 - -#define REG_A5XX_RB_BLIT_DST_LO 0x0000e214 - -#define REG_A5XX_RB_BLIT_DST_HI 0x0000e215 - -#define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216 -#define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff -#define A5XX_RB_BLIT_DST_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; -} - -#define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217 -#define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff -#define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; -} - -#define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218 - -#define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219 - -#define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a - -#define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b - -#define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c -#define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002 -#define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE 0x00000004 -#define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0 -#define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4 -static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) -{ - return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK; -} - -#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240 - -#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241 - -#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242 - -static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; } - -static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; } - -static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; } - -static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; } -#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff -#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; -} - -static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; } -#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff -#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; -} - -#define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263 - -#define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264 - -#define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265 -#define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff -#define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; -} - -#define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266 -#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff -#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; -} - -#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267 - -#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268 - -#define REG_A5XX_VPC_CNTL_0 0x0000e280 -#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f -#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0 -static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) -{ - return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK; -} -#define A5XX_VPC_CNTL_0_VARYING 0x00000800 - -static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } - -static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } - -static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } - -static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } - -#define REG_A5XX_UNKNOWN_E292 0x0000e292 - -#define REG_A5XX_UNKNOWN_E293 0x0000e293 - -static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } - -static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } - -#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298 - -#define REG_A5XX_UNKNOWN_E29A 0x0000e29a - -#define REG_A5XX_VPC_PACK 0x0000e29d -#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff -#define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0 -static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) -{ - return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK; -} -#define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00 -#define A5XX_VPC_PACK_PSIZELOC__SHIFT 8 -static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val) -{ - return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK; -} - -#define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0 - -#define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1 -#define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 -#define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 -#define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 -#define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 -#define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 - -#define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2 -#define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001 - -#define REG_A5XX_VPC_SO_CNTL 0x0000e2a3 -#define A5XX_VPC_SO_CNTL_ENABLE 0x00010000 - -#define REG_A5XX_VPC_SO_PROG 0x0000e2a4 -#define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 -#define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0 -static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val) -{ - return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK; -} -#define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc -#define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2 -static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK; -} -#define A5XX_VPC_SO_PROG_A_EN 0x00000800 -#define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 -#define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12 -static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val) -{ - return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK; -} -#define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 -#define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14 -static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK; -} -#define A5XX_VPC_SO_PROG_B_EN 0x00800000 - -static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } - -static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } - -static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; } - -static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; } - -static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; } - -static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; } - -static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; } - -static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; } - -#define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384 -#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f -#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0 -static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) -{ - return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; -} -#define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100 -#define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES 0x00000200 -#define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400 - -#define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385 -#define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800 - -#define REG_A5XX_PC_RASTER_CNTL 0x0000e388 -#define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x00000007 -#define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 0 -static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK; -} -#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038 -#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3 -static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK; -} -#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040 - -#define REG_A5XX_UNKNOWN_E389 0x0000e389 - -#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c - -#define REG_A5XX_PC_GS_LAYERED 0x0000e38d - -#define REG_A5XX_PC_GS_PARAM 0x0000e38e -#define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff -#define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 -static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) -{ - return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK; -} -#define A5XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 -#define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 -static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) -{ - return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK; -} -#define A5XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 -#define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 -static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK; -} - -#define REG_A5XX_PC_HS_PARAM 0x0000e38f -#define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f -#define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 -static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) -{ - return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK; -} -#define A5XX_PC_HS_PARAM_SPACING__MASK 0x00600000 -#define A5XX_PC_HS_PARAM_SPACING__SHIFT 21 -static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) -{ - return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK; -} -#define A5XX_PC_HS_PARAM_CW 0x00800000 -#define A5XX_PC_HS_PARAM_CONNECTED 0x01000000 - -#define REG_A5XX_PC_POWER_CNTL 0x0000e3b0 - -#define REG_A5XX_VFD_CONTROL_0 0x0000e400 -#define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f -#define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 -static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) -{ - return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK; -} - -#define REG_A5XX_VFD_CONTROL_1 0x0000e401 -#define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff -#define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 -static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) -{ - return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK; -} -#define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 -#define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 -static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) -{ - return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK; -} -#define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 -#define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 -static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) -{ - return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK; -} - -#define REG_A5XX_VFD_CONTROL_2 0x0000e402 -#define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff -#define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0 -static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) -{ - return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK; -} - -#define REG_A5XX_VFD_CONTROL_3 0x0000e403 -#define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00 -#define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8 -static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) -{ - return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK; -} -#define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 -#define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 -static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) -{ - return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK; -} -#define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 -#define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 -static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) -{ - return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK; -} - -#define REG_A5XX_VFD_CONTROL_4 0x0000e404 - -#define REG_A5XX_VFD_CONTROL_5 0x0000e405 - -#define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408 - -#define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409 - -static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } - -static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } - -static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; } - -static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; } - -static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } - -static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } - -static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } -#define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f -#define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0 -static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) -{ - return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK; -} -#define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 -#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 -#define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 -static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) -{ - return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK; -} -#define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 -#define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 -static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK; -} -#define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000 -#define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000 - -static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } - -static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } - -static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } -#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f -#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 -static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) -{ - return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; -} -#define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 -#define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 -static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) -{ - return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK; -} - -#define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0 - -#define REG_A5XX_SP_SP_CNTL 0x0000e580 - -#define REG_A5XX_SP_VS_CONFIG 0x0000e584 -#define A5XX_SP_VS_CONFIG_ENABLED 0x00000001 -#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_SP_FS_CONFIG 0x0000e585 -#define A5XX_SP_FS_CONFIG_ENABLED 0x00000001 -#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_SP_HS_CONFIG 0x0000e586 -#define A5XX_SP_HS_CONFIG_ENABLED 0x00000001 -#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_SP_DS_CONFIG 0x0000e587 -#define A5XX_SP_DS_CONFIG_ENABLED 0x00000001 -#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_SP_GS_CONFIG 0x0000e588 -#define A5XX_SP_GS_CONFIG_ENABLED 0x00000001 -#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_SP_CS_CONFIG 0x0000e589 -#define A5XX_SP_CS_CONFIG_ENABLED 0x00000001 -#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a - -#define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b - -#define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590 -#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008 -#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3 -static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; -} -#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000 -#define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000 -#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 -#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25 -static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; -} - -#define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592 -#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f -#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0 -static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) -{ - return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; -} - -static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } - -static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } -#define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff -#define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 -static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) -{ - return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK; -} -#define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 -#define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 -static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) -{ - return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK; -} -#define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 -#define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 -static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) -{ - return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK; -} -#define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 -#define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 -static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) -{ - return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK; -} - -static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } - -static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } -#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff -#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) -{ - return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 -#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) -{ - return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 -#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) -{ - return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 -#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) -{ - return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab - -#define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac - -#define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad - -#define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0 -#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008 -#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3 -static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; -} -#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000 -#define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000 -#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 -#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25 -static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; -} - -#define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2 - -#define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3 - -#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4 - -#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9 -#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001 -#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100 -#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 - -#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca -#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f -#define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0 -static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) -{ - return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK; -} -#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0 -#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5 -static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) -{ - return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK; -} -#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000 -#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13 -static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) -{ - return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK; -} - -static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } - -static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } -#define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff -#define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 -static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) -{ - return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK; -} -#define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 - -static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } - -static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } -#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff -#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) -{ - return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; -} -#define A5XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 -#define A5XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 -#define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400 - -#define REG_A5XX_UNKNOWN_E5DB 0x0000e5db - -#define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0 -#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008 -#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3 -static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; -} -#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000 -#define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000 -#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 -#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25 -static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; -} - -#define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2 - -#define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3 - -#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4 - -#define REG_A5XX_SP_HS_CTRL_REG0 0x0000e600 -#define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00000008 -#define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 3 -static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; -} -#define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A5XX_SP_HS_CTRL_REG0_VARYING 0x00010000 -#define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x00100000 -#define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 -#define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 25 -static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; -} - -#define REG_A5XX_UNKNOWN_E602 0x0000e602 - -#define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603 - -#define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604 - -#define REG_A5XX_SP_DS_CTRL_REG0 0x0000e610 -#define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00000008 -#define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 3 -static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; -} -#define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A5XX_SP_DS_CTRL_REG0_VARYING 0x00010000 -#define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x00100000 -#define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 -#define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 25 -static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; -} - -#define REG_A5XX_UNKNOWN_E62B 0x0000e62b - -#define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c - -#define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d - -#define REG_A5XX_SP_GS_CTRL_REG0 0x0000e640 -#define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00000008 -#define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 3 -static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; -} -#define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 -#define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 -static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 -#define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 -static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A5XX_SP_GS_CTRL_REG0_VARYING 0x00010000 -#define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x00100000 -#define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 -#define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 25 -static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; -} - -#define REG_A5XX_UNKNOWN_E65B 0x0000e65b - -#define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c - -#define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d - -#define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704 -#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK; -} - -#define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705 -#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK; -} -#define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 - -#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706 - -#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707 - -#define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700 - -#define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701 - -#define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702 - -#define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703 - -#define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722 - -#define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723 - -#define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724 - -#define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725 - -#define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726 - -#define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727 - -#define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728 - -#define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729 - -#define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a - -#define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b - -#define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c - -#define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d - -#define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e - -#define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f - -#define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730 - -#define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731 - -#define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750 - -#define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751 - -#define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a - -#define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b - -#define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c - -#define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d - -#define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e - -#define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f - -#define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760 - -#define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761 - -#define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764 - -#define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784 -#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001 -#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; -} -#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004 -#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2 -static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK; -} - -#define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785 -#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f -#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; -} - -#define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786 -#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff -#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; -} -#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 -#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 -static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; -} -#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 -#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 -static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; -} - -#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787 -#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff -#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK; -} - -#define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788 -#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 -#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 -static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; -} -#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 -#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 -static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; -} - -#define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a - -#define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b -#define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001 -#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c -#define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001 -#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d -#define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001 -#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e -#define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001 -#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f -#define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001 -#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790 -#define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001 -#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe -#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 -static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK; -} -#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 -#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8 -static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK; -} - -#define REG_A5XX_HLSQ_VS_CNTL 0x0000e791 -#define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001 -#define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe -#define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1 -static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) -{ - return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK; -} - -#define REG_A5XX_HLSQ_FS_CNTL 0x0000e792 -#define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001 -#define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe -#define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1 -static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) -{ - return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK; -} - -#define REG_A5XX_HLSQ_HS_CNTL 0x0000e793 -#define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001 -#define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe -#define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1 -static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) -{ - return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK; -} - -#define REG_A5XX_HLSQ_DS_CNTL 0x0000e794 -#define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001 -#define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe -#define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1 -static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) -{ - return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK; -} - -#define REG_A5XX_HLSQ_GS_CNTL 0x0000e795 -#define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001 -#define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe -#define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1 -static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) -{ - return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK; -} - -#define REG_A5XX_HLSQ_CS_CNTL 0x0000e796 -#define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001 -#define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe -#define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1 -static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK; -} - -#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9 - -#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba - -#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb - -#define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0 -#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 -#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; -} -#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc -#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; -} -#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 -#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; -} -#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 -#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; -} - -#define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1 -#define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff -#define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; -} - -#define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2 -#define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff -#define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; -} - -#define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3 -#define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff -#define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; -} - -#define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4 -#define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff -#define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; -} - -#define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5 -#define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff -#define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; -} - -#define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6 -#define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff -#define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; -} - -#define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7 -#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff -#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 -static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; -} -#define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 -#define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 -static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK; -} -#define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 -#define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 -static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK; -} -#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 -#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 -static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) -{ - return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; -} - -#define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8 - -#define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0 - -#define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3 - -#define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4 - -#define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5 - -#define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8 - -#define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9 - -#define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca - -#define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd - -#define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce - -#define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf - -#define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2 - -#define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3 - -#define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4 - -#define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7 - -#define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8 - -#define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9 - -#define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc - -#define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd - -#define REG_A5XX_RB_2D_BLIT_CNTL 0x00002100 - -#define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101 - -#define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102 - -#define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103 - -#define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104 - -#define REG_A5XX_RB_2D_SRC_INFO 0x00002107 -#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) -{ - return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK; -} -#define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 -#define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT 8 -static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) -{ - return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK; -} -#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 -static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK; -} -#define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000 - -#define REG_A5XX_RB_2D_SRC_LO 0x00002108 - -#define REG_A5XX_RB_2D_SRC_HI 0x00002109 - -#define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a -#define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff -#define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK; -} -#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000 -#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16 -static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK; -} - -#define REG_A5XX_RB_2D_DST_INFO 0x00002110 -#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) -{ - return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; -} -#define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 -#define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 -static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) -{ - return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK; -} -#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 -static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; -} -#define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000 - -#define REG_A5XX_RB_2D_DST_LO 0x00002111 - -#define REG_A5XX_RB_2D_DST_HI 0x00002112 - -#define REG_A5XX_RB_2D_DST_SIZE 0x00002113 -#define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff -#define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 -static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK; -} -#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000 -#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16 -static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK; -} - -#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140 - -#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141 - -#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143 - -#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144 - -#define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180 - -#define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181 -#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) -{ - return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK; -} -#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 -#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT 8 -static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) -{ - return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK; -} -#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 -static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK; -} -#define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000 - -#define REG_A5XX_GRAS_2D_DST_INFO 0x00002182 -#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) -{ - return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK; -} -#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK 0x00000300 -#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT 8 -static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) -{ - return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK; -} -#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10 -static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK; -} -#define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000 - -#define REG_A5XX_UNKNOWN_2100 0x00002100 - -#define REG_A5XX_UNKNOWN_2180 0x00002180 - -#define REG_A5XX_UNKNOWN_2184 0x00002184 - -#define REG_A5XX_TEX_SAMP_0 0x00000000 -#define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 -#define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 -#define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1 -static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) -{ - return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK; -} -#define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 -#define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3 -static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) -{ - return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK; -} -#define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 -#define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5 -static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) -{ - return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK; -} -#define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 -#define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8 -static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) -{ - return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK; -} -#define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 -#define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11 -static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) -{ - return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK; -} -#define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 -#define A5XX_TEX_SAMP_0_ANISO__SHIFT 14 -static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) -{ - return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK; -} -#define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 -#define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 -static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) -{ - return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK; -} - -#define REG_A5XX_TEX_SAMP_1 0x00000001 -#define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e -#define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 -static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) -{ - return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK; -} -#define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 -#define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 -#define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 -#define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 -#define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 -static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) -{ - return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK; -} -#define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 -#define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 -static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) -{ - return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK; -} - -#define REG_A5XX_TEX_SAMP_2 0x00000002 -#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0 -#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4 -static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) -{ - return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; -} - -#define REG_A5XX_TEX_SAMP_3 0x00000003 - -#define REG_A5XX_TEX_CONST_0 0x00000000 -#define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 -#define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0 -static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) -{ - return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK; -} -#define A5XX_TEX_CONST_0_SRGB 0x00000004 -#define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 -#define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4 -static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) -{ - return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK; -} -#define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 -#define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 -static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) -{ - return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK; -} -#define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 -#define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 -static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) -{ - return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK; -} -#define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 -#define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13 -static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) -{ - return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK; -} -#define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 -#define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16 -static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val) -{ - return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK; -} -#define A5XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 -#define A5XX_TEX_CONST_0_SAMPLES__SHIFT 20 -static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK; -} -#define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000 -#define A5XX_TEX_CONST_0_FMT__SHIFT 22 -static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) -{ - return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK; -} -#define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000 -#define A5XX_TEX_CONST_0_SWAP__SHIFT 30 -static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK; -} - -#define REG_A5XX_TEX_CONST_1 0x00000001 -#define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff -#define A5XX_TEX_CONST_1_WIDTH__SHIFT 0 -static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) -{ - return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK; -} -#define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 -#define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15 -static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) -{ - return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK; -} - -#define REG_A5XX_TEX_CONST_2 0x00000002 -#define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f -#define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 -static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val) -{ - return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK; -} -#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 -#define A5XX_TEX_CONST_2_PITCH__SHIFT 7 -static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) -{ - return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK; -} -#define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000 -#define A5XX_TEX_CONST_2_TYPE__SHIFT 29 -static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) -{ - return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK; -} - -#define REG_A5XX_TEX_CONST_3 0x00000003 -#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff -#define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; -} -#define A5XX_TEX_CONST_3_FLAG 0x10000000 - -#define REG_A5XX_TEX_CONST_4 0x00000004 -#define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 -#define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5 -static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; -} - -#define REG_A5XX_TEX_CONST_5 0x00000005 -#define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff -#define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0 -static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val) -{ - return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK; -} -#define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 -#define A5XX_TEX_CONST_5_DEPTH__SHIFT 17 -static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) -{ - return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK; -} - -#define REG_A5XX_TEX_CONST_6 0x00000006 - -#define REG_A5XX_TEX_CONST_7 0x00000007 - -#define REG_A5XX_TEX_CONST_8 0x00000008 - -#define REG_A5XX_TEX_CONST_9 0x00000009 - -#define REG_A5XX_TEX_CONST_10 0x0000000a - -#define REG_A5XX_TEX_CONST_11 0x0000000b - -#define REG_A5XX_SSBO_0_0 0x00000000 -#define A5XX_SSBO_0_0_BASE_LO__MASK 0xffffffe0 -#define A5XX_SSBO_0_0_BASE_LO__SHIFT 5 -static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK; -} - -#define REG_A5XX_SSBO_0_1 0x00000001 -#define A5XX_SSBO_0_1_PITCH__MASK 0x003fffff -#define A5XX_SSBO_0_1_PITCH__SHIFT 0 -static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val) -{ - return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK; -} - -#define REG_A5XX_SSBO_0_2 0x00000002 -#define A5XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000 -#define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12 -static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK; -} - -#define REG_A5XX_SSBO_0_3 0x00000003 -#define A5XX_SSBO_0_3_CPP__MASK 0x0000003f -#define A5XX_SSBO_0_3_CPP__SHIFT 0 -static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val) -{ - return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK; -} - -#define REG_A5XX_SSBO_1_0 0x00000000 -#define A5XX_SSBO_1_0_FMT__MASK 0x0000ff00 -#define A5XX_SSBO_1_0_FMT__SHIFT 8 -static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val) -{ - return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK; -} -#define A5XX_SSBO_1_0_WIDTH__MASK 0xffff0000 -#define A5XX_SSBO_1_0_WIDTH__SHIFT 16 -static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val) -{ - return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK; -} - -#define REG_A5XX_SSBO_1_1 0x00000001 -#define A5XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff -#define A5XX_SSBO_1_1_HEIGHT__SHIFT 0 -static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val) -{ - return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK; -} -#define A5XX_SSBO_1_1_DEPTH__MASK 0xffff0000 -#define A5XX_SSBO_1_1_DEPTH__SHIFT 16 -static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val) -{ - return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK; -} - -#define REG_A5XX_SSBO_2_0 0x00000000 -#define A5XX_SSBO_2_0_BASE_LO__MASK 0xffffffff -#define A5XX_SSBO_2_0_BASE_LO__SHIFT 0 -static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val) -{ - return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK; -} - -#define REG_A5XX_SSBO_2_1 0x00000001 -#define A5XX_SSBO_2_1_BASE_HI__MASK 0xffffffff -#define A5XX_SSBO_2_1_BASE_HI__SHIFT 0 -static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val) -{ - return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK; -} - -#define REG_A5XX_UBO_0 0x00000000 -#define A5XX_UBO_0_BASE_LO__MASK 0xffffffff -#define A5XX_UBO_0_BASE_LO__SHIFT 0 -static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val) -{ - return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK; -} - -#define REG_A5XX_UBO_1 0x00000001 -#define A5XX_UBO_1_BASE_HI__MASK 0x0001ffff -#define A5XX_UBO_1_BASE_HI__SHIFT 0 -static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val) -{ - return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK; -} - - -#endif /* A5XX_XML */ diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml new file mode 100644 index 00000000000..a001c9ae631 --- /dev/null +++ b/src/freedreno/registers/a6xx.xml @@ -0,0 +1,3311 @@ +<?xml version="1.0" encoding="UTF-8"?> +<database xmlns="http://nouveau.freedesktop.org/" +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" +xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> +<import file="freedreno_copyright.xml"/> +<import file="adreno/adreno_common.xml"/> +<import file="adreno/adreno_pm4.xml"/> + +<!-- these might be same as a5xx --> +<enum name="a6xx_color_fmt"> + <value value="0x02" name="RB6_A8_UNORM"/> + <value value="0x03" name="RB6_R8_UNORM"/> + <value value="0x04" name="RB6_R8_SNORM"/> + <value value="0x05" name="RB6_R8_UINT"/> + <value value="0x06" name="RB6_R8_SINT"/> + <value value="0x08" name="RB6_R4G4B4A4_UNORM"/> + <value value="0x0a" name="RB6_R5G5B5A1_UNORM"/> + <value value="0x0e" name="RB6_R5G6B5_UNORM"/> + <value value="0x0f" name="RB6_R8G8_UNORM"/> + <value value="0x10" name="RB6_R8G8_SNORM"/> + <value value="0x11" name="RB6_R8G8_UINT"/> + <value value="0x12" name="RB6_R8G8_SINT"/> + <value value="0x15" name="RB6_R16_UNORM"/> + <value value="0x16" name="RB6_R16_SNORM"/> + <value value="0x17" name="RB6_R16_FLOAT"/> + <value value="0x18" name="RB6_R16_UINT"/> + <value value="0x19" name="RB6_R16_SINT"/> + <value value="0x30" name="RB6_R8G8B8A8_UNORM"/> + <value value="0x31" name="RB6_R8G8B8_UNORM"/> + <value value="0x32" name="RB6_R8G8B8A8_SNORM"/> + <value value="0x33" name="RB6_R8G8B8A8_UINT"/> + <value value="0x34" name="RB6_R8G8B8A8_SINT"/> + <value value="0x37" name="RB6_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 --> + <value value="0x3a" name="RB6_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI --> + <value value="0x42" name="RB6_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F --> + <value value="0x43" name="RB6_R16G16_UNORM"/> + <value value="0x44" name="RB6_R16G16_SNORM"/> + <value value="0x45" name="RB6_R16G16_FLOAT"/> + <value value="0x46" name="RB6_R16G16_UINT"/> + <value value="0x47" name="RB6_R16G16_SINT"/> + <value value="0x4a" name="RB6_R32_FLOAT"/> + <value value="0x4b" name="RB6_R32_UINT"/> + <value value="0x4c" name="RB6_R32_SINT"/> + <value value="0x60" name="RB6_R16G16B16A16_UNORM"/> + <value value="0x61" name="RB6_R16G16B16A16_SNORM"/> + <value value="0x62" name="RB6_R16G16B16A16_FLOAT"/> + <value value="0x63" name="RB6_R16G16B16A16_UINT"/> + <value value="0x64" name="RB6_R16G16B16A16_SINT"/> + <value value="0x67" name="RB6_R32G32_FLOAT"/> + <value value="0x68" name="RB6_R32G32_UINT"/> + <value value="0x69" name="RB6_R32G32_SINT"/> + <value value="0x82" name="RB6_R32G32B32A32_FLOAT"/> + <value value="0x83" name="RB6_R32G32B32A32_UINT"/> + <value value="0x84" name="RB6_R32G32B32A32_SINT"/> + <value value="0x91" name="RB6_Z24_UNORM_S8_UINT"/> + <value value="0xa0" name="RB6_X8Z24_UNORM"/> +</enum> + +<!-- these might be same as a5xx --> +<enum name="a6xx_tile_mode"> + <value name="TILE6_LINEAR" value="0"/> + <value name="TILE6_2" value="2"/> + <value name="TILE6_3" value="3"/> +</enum> + +<!-- these might be same as a5xx --> +<enum name="a6xx_vtx_fmt" prefix="chipset"> + <value value="0x03" name="VFMT6_8_UNORM"/> + <value value="0x04" name="VFMT6_8_SNORM"/> + <value value="0x05" name="VFMT6_8_UINT"/> + <value value="0x06" name="VFMT6_8_SINT"/> + + <value value="0x0f" name="VFMT6_8_8_UNORM"/> + <value value="0x10" name="VFMT6_8_8_SNORM"/> + <value value="0x11" name="VFMT6_8_8_UINT"/> + <value value="0x12" name="VFMT6_8_8_SINT"/> + + <value value="0x15" name="VFMT6_16_UNORM"/> + <value value="0x16" name="VFMT6_16_SNORM"/> + <value value="0x17" name="VFMT6_16_FLOAT"/> + <value value="0x18" name="VFMT6_16_UINT"/> + <value value="0x19" name="VFMT6_16_SINT"/> + + <value value="0x21" name="VFMT6_8_8_8_UNORM"/> + <value value="0x22" name="VFMT6_8_8_8_SNORM"/> + <value value="0x23" name="VFMT6_8_8_8_UINT"/> + <value value="0x24" name="VFMT6_8_8_8_SINT"/> + + <value value="0x30" name="VFMT6_8_8_8_8_UNORM"/> + <value value="0x32" name="VFMT6_8_8_8_8_SNORM"/> + <value value="0x33" name="VFMT6_8_8_8_8_UINT"/> + <value value="0x34" name="VFMT6_8_8_8_8_SINT"/> + + <value value="0x36" name="VFMT6_10_10_10_2_UNORM"/> + <value value="0x39" name="VFMT6_10_10_10_2_SNORM"/> + <value value="0x3a" name="VFMT6_10_10_10_2_UINT"/> + <value value="0x3b" name="VFMT6_10_10_10_2_SINT"/> + + <value value="0x42" name="VFMT6_11_11_10_FLOAT"/> + + <value value="0x43" name="VFMT6_16_16_UNORM"/> + <value value="0x44" name="VFMT6_16_16_SNORM"/> + <value value="0x45" name="VFMT6_16_16_FLOAT"/> + <value value="0x46" name="VFMT6_16_16_UINT"/> + <value value="0x47" name="VFMT6_16_16_SINT"/> + + <value value="0x48" name="VFMT6_32_UNORM"/> + <value value="0x49" name="VFMT6_32_SNORM"/> + <value value="0x4a" name="VFMT6_32_FLOAT"/> + <value value="0x4b" name="VFMT6_32_UINT"/> + <value value="0x4c" name="VFMT6_32_SINT"/> + <value value="0x4d" name="VFMT6_32_FIXED"/> + + <value value="0x58" name="VFMT6_16_16_16_UNORM"/> + <value value="0x59" name="VFMT6_16_16_16_SNORM"/> + <value value="0x5a" name="VFMT6_16_16_16_FLOAT"/> + <value value="0x5b" name="VFMT6_16_16_16_UINT"/> + <value value="0x5c" name="VFMT6_16_16_16_SINT"/> + + <value value="0x60" name="VFMT6_16_16_16_16_UNORM"/> + <value value="0x61" name="VFMT6_16_16_16_16_SNORM"/> + <value value="0x62" name="VFMT6_16_16_16_16_FLOAT"/> + <value value="0x63" name="VFMT6_16_16_16_16_UINT"/> + <value value="0x64" name="VFMT6_16_16_16_16_SINT"/> + + <value value="0x65" name="VFMT6_32_32_UNORM"/> + <value value="0x66" name="VFMT6_32_32_SNORM"/> + <value value="0x67" name="VFMT6_32_32_FLOAT"/> + <value value="0x68" name="VFMT6_32_32_UINT"/> + <value value="0x69" name="VFMT6_32_32_SINT"/> + <value value="0x6a" name="VFMT6_32_32_FIXED"/> + + <value value="0x70" name="VFMT6_32_32_32_UNORM"/> + <value value="0x71" name="VFMT6_32_32_32_SNORM"/> + <value value="0x72" name="VFMT6_32_32_32_UINT"/> + <value value="0x73" name="VFMT6_32_32_32_SINT"/> + <value value="0x74" name="VFMT6_32_32_32_FLOAT"/> + <value value="0x75" name="VFMT6_32_32_32_FIXED"/> + + <value value="0x80" name="VFMT6_32_32_32_32_UNORM"/> + <value value="0x81" name="VFMT6_32_32_32_32_SNORM"/> + <value value="0x82" name="VFMT6_32_32_32_32_FLOAT"/> + <value value="0x83" name="VFMT6_32_32_32_32_UINT"/> + <value value="0x84" name="VFMT6_32_32_32_32_SINT"/> + <value value="0x85" name="VFMT6_32_32_32_32_FIXED"/> +</enum> + +<enum name="a6xx_tex_fmt"> + <value value="0x02" name="TFMT6_A8_UNORM"/> + <value value="0x03" name="TFMT6_8_UNORM"/> + <value value="0x04" name="TFMT6_8_SNORM"/> + <value value="0x05" name="TFMT6_8_UINT"/> + <value value="0x06" name="TFMT6_8_SINT"/> + <value value="0x08" name="TFMT6_4_4_4_4_UNORM"/> + <value value="0x0a" name="TFMT6_5_5_5_1_UNORM"/> + <value value="0x0e" name="TFMT6_5_6_5_UNORM"/> + <value value="0x0f" name="TFMT6_8_8_UNORM"/> + <value value="0x10" name="TFMT6_8_8_SNORM"/> + <value value="0x11" name="TFMT6_8_8_UINT"/> + <value value="0x12" name="TFMT6_8_8_SINT"/> + <value value="0x13" name="TFMT6_L8_A8_UNORM"/> + <value value="0x15" name="TFMT6_16_UNORM"/> + <value value="0x16" name="TFMT6_16_SNORM"/> + <value value="0x17" name="TFMT6_16_FLOAT"/> + <value value="0x18" name="TFMT6_16_UINT"/> + <value value="0x19" name="TFMT6_16_SINT"/> + <value value="0x30" name="TFMT6_8_8_8_8_UNORM"/> + <value value="0x31" name="TFMT6_8_8_8_UNORM"/> + <value value="0x32" name="TFMT6_8_8_8_8_SNORM"/> + <value value="0x33" name="TFMT6_8_8_8_8_UINT"/> + <value value="0x34" name="TFMT6_8_8_8_8_SINT"/> + <value value="0x35" name="TFMT6_9_9_9_E5_FLOAT"/> + <value value="0x36" name="TFMT6_10_10_10_2_UNORM"/> + <value value="0x3a" name="TFMT6_10_10_10_2_UINT"/> + <value value="0x42" name="TFMT6_11_11_10_FLOAT"/> + <value value="0x43" name="TFMT6_16_16_UNORM"/> + <value value="0x44" name="TFMT6_16_16_SNORM"/> + <value value="0x45" name="TFMT6_16_16_FLOAT"/> + <value value="0x46" name="TFMT6_16_16_UINT"/> + <value value="0x47" name="TFMT6_16_16_SINT"/> + <value value="0x4a" name="TFMT6_32_FLOAT"/> + <value value="0x4b" name="TFMT6_32_UINT"/> + <value value="0x4c" name="TFMT6_32_SINT"/> + <value value="0x60" name="TFMT6_16_16_16_16_UNORM"/> + <value value="0x61" name="TFMT6_16_16_16_16_SNORM"/> + <value value="0x62" name="TFMT6_16_16_16_16_FLOAT"/> + <value value="0x63" name="TFMT6_16_16_16_16_UINT"/> + <value value="0x64" name="TFMT6_16_16_16_16_SINT"/> + <value value="0x67" name="TFMT6_32_32_FLOAT"/> + <value value="0x68" name="TFMT6_32_32_UINT"/> + <value value="0x69" name="TFMT6_32_32_SINT"/> + <value value="0x72" name="TFMT6_32_32_32_UINT"/> + <value value="0x73" name="TFMT6_32_32_32_SINT"/> + <value value="0x74" name="TFMT6_32_32_32_FLOAT"/> + <value value="0x82" name="TFMT6_32_32_32_32_FLOAT"/> + <value value="0x83" name="TFMT6_32_32_32_32_UINT"/> + <value value="0x84" name="TFMT6_32_32_32_32_SINT"/> + <value value="0x91" name="TFMT6_Z24_UNORM_S8_UINT"/> + <value value="0xa0" name="TFMT6_X8Z24_UNORM"/> + + <value value="0xab" name="TFMT6_ETC2_RG11_UNORM"/> + <value value="0xac" name="TFMT6_ETC2_RG11_SNORM"/> + <value value="0xad" name="TFMT6_ETC2_R11_UNORM"/> + <value value="0xae" name="TFMT6_ETC2_R11_SNORM"/> + <value value="0xaf" name="TFMT6_ETC1"/> + <value value="0xb0" name="TFMT6_ETC2_RGB8"/> + <value value="0xb1" name="TFMT6_ETC2_RGBA8"/> + <value value="0xb2" name="TFMT6_ETC2_RGB8A1"/> + <value value="0xb3" name="TFMT6_DXT1"/> + <value value="0xb4" name="TFMT6_DXT3"/> + <value value="0xb5" name="TFMT6_DXT5"/> + <value value="0xb7" name="TFMT6_RGTC1_UNORM"/> + <value value="0xb8" name="TFMT6_RGTC1_SNORM"/> + <value value="0xbb" name="TFMT6_RGTC2_UNORM"/> + <value value="0xbc" name="TFMT6_RGTC2_SNORM"/> + <value value="0xbe" name="TFMT6_BPTC_UFLOAT"/> + <value value="0xbf" name="TFMT6_BPTC_FLOAT"/> + <value value="0xc0" name="TFMT6_BPTC"/> + <value value="0xc1" name="TFMT6_ASTC_4x4"/> + <value value="0xc2" name="TFMT6_ASTC_5x4"/> + <value value="0xc3" name="TFMT6_ASTC_5x5"/> + <value value="0xc4" name="TFMT6_ASTC_6x5"/> + <value value="0xc5" name="TFMT6_ASTC_6x6"/> + <value value="0xc6" name="TFMT6_ASTC_8x5"/> + <value value="0xc7" name="TFMT6_ASTC_8x6"/> + <value value="0xc8" name="TFMT6_ASTC_8x8"/> + <value value="0xc9" name="TFMT6_ASTC_10x5"/> + <value value="0xca" name="TFMT6_ASTC_10x6"/> + <value value="0xcb" name="TFMT6_ASTC_10x8"/> + <value value="0xcc" name="TFMT6_ASTC_10x10"/> + <value value="0xcd" name="TFMT6_ASTC_12x10"/> + <value value="0xce" name="TFMT6_ASTC_12x12"/> +</enum> + +<enum name="a6xx_tex_fetchsize"> + <value name="TFETCH6_1_BYTE" value="0"/> + <value name="TFETCH6_2_BYTE" value="1"/> + <value name="TFETCH6_4_BYTE" value="2"/> + <value name="TFETCH6_8_BYTE" value="3"/> + <value name="TFETCH6_16_BYTE" value="4"/> +</enum> + +<!-- probably same as a5xx --> +<enum name="a6xx_depth_format"> + <value name="DEPTH6_NONE" value="0"/> + <value name="DEPTH6_16" value="1"/> + <value name="DEPTH6_24_8" value="2"/> + <value name="DEPTH6_32" value="4"/> +</enum> + +<bitset name="a6x_cp_protect" inline="yes"> + <bitfield name="BASE_ADDR" low="0" high="17"/> + <bitfield name="MASK_LEN" low="18" high="30"/> + <bitfield name="READ" pos="31"/> +</bitset> + +<enum name="a6xx_shader_id"> + <value value="0x9" name="A6XX_TP0_TMO_DATA"/> + <value value="0xa" name="A6XX_TP0_SMO_DATA"/> + <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/> + <value value="0x19" name="A6XX_TP1_TMO_DATA"/> + <value value="0x1a" name="A6XX_TP1_SMO_DATA"/> + <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/> + <value value="0x29" name="A6XX_SP_INST_DATA"/> + <value value="0x2a" name="A6XX_SP_LB_0_DATA"/> + <value value="0x2b" name="A6XX_SP_LB_1_DATA"/> + <value value="0x2c" name="A6XX_SP_LB_2_DATA"/> + <value value="0x2d" name="A6XX_SP_LB_3_DATA"/> + <value value="0x2e" name="A6XX_SP_LB_4_DATA"/> + <value value="0x2f" name="A6XX_SP_LB_5_DATA"/> + <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/> + <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/> + <value value="0x32" name="A6XX_SP_UAV_DATA"/> + <value value="0x33" name="A6XX_SP_INST_TAG"/> + <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/> + <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/> + <value value="0x36" name="A6XX_SP_SMO_TAG"/> + <value value="0x37" name="A6XX_SP_STATE_DATA"/> + <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/> + <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/> + <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/> + <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/> + <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> + <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> + <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/> + <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/> + <value value="0x52" name="A6XX_HLSQ_INST_RAM"/> + <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/> + <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/> + <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/> + <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/> + <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/> + <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> + <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> + <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/> + <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/> + <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/> + <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/> + <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/> + <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/> +</enum> + +<enum name="a6xx_debugbus_id"> + <value value="0x1" name="A6XX_DBGBUS_CP"/> + <value value="0x2" name="A6XX_DBGBUS_RBBM"/> + <value value="0x3" name="A6XX_DBGBUS_VBIF"/> + <value value="0x4" name="A6XX_DBGBUS_HLSQ"/> + <value value="0x5" name="A6XX_DBGBUS_UCHE"/> + <value value="0x6" name="A6XX_DBGBUS_DPM"/> + <value value="0x7" name="A6XX_DBGBUS_TESS"/> + <value value="0x8" name="A6XX_DBGBUS_PC"/> + <value value="0x9" name="A6XX_DBGBUS_VFDP"/> + <value value="0xa" name="A6XX_DBGBUS_VPC"/> + <value value="0xb" name="A6XX_DBGBUS_TSE"/> + <value value="0xc" name="A6XX_DBGBUS_RAS"/> + <value value="0xd" name="A6XX_DBGBUS_VSC"/> + <value value="0xe" name="A6XX_DBGBUS_COM"/> + <value value="0x10" name="A6XX_DBGBUS_LRZ"/> + <value value="0x11" name="A6XX_DBGBUS_A2D"/> + <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/> + <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/> + <value value="0x14" name="A6XX_DBGBUS_RBP"/> + <value value="0x15" name="A6XX_DBGBUS_DCS"/> + <value value="0x16" name="A6XX_DBGBUS_DBGC"/> + <value value="0x17" name="A6XX_DBGBUS_CX"/> + <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/> + <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/> + <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/> + <value value="0x1d" name="A6XX_DBGBUS_GPC"/> + <value value="0x1e" name="A6XX_DBGBUS_LARC"/> + <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/> + <value value="0x20" name="A6XX_DBGBUS_RB_0"/> + <value value="0x21" name="A6XX_DBGBUS_RB_1"/> + <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/> + <value value="0x28" name="A6XX_DBGBUS_CCU_0"/> + <value value="0x29" name="A6XX_DBGBUS_CCU_1"/> + <value value="0x38" name="A6XX_DBGBUS_VFD_0"/> + <value value="0x39" name="A6XX_DBGBUS_VFD_1"/> + <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/> + <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/> + <value value="0x40" name="A6XX_DBGBUS_SP_0"/> + <value value="0x41" name="A6XX_DBGBUS_SP_1"/> + <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/> + <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/> + <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/> + <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/> +</enum> + +<enum name="a6xx_cp_perfcounter_select"> + <value value="0" name="PERF_CP_ALWAYS_COUNT"/> + <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> + <value value="2" name="PERF_CP_BUSY_CYCLES"/> + <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/> + <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> + <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> + <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> + <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> + <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/> + <value value="9" name="PERF_CP_MODE_SWITCH"/> + <value value="10" name="PERF_CP_ZPASS_DONE"/> + <value value="11" name="PERF_CP_CONTEXT_DONE"/> + <value value="12" name="PERF_CP_CACHE_FLUSH"/> + <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/> + <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/> + <value value="15" name="PERF_CP_SQE_IDLE"/> + <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/> + <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/> + <value value="18" name="PERF_CP_SQE_MRB_STARVE"/> + <value value="19" name="PERF_CP_SQE_RRB_STARVE"/> + <value value="20" name="PERF_CP_SQE_VSD_STARVE"/> + <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/> + <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/> + <value value="23" name="PERF_CP_SQE_SYNC_STALL"/> + <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/> + <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/> + <value value="26" name="PERF_CP_SQE_T4_EXEC"/> + <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/> + <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/> + <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/> + <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> + <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/> + <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/> + <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/> + <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> + <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> + <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/> + <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/> + <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/> + <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/> + <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/> + <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/> + <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/> + <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/> + <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/> + <value value="45" name="PERF_CP_PM4_DATA"/> + <value value="46" name="PERF_CP_PM4_HEADERS"/> + <value value="47" name="PERF_CP_VBIF_READ_BEATS"/> + <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/> + <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/> +</enum> + +<enum name="a6xx_rbbm_perfcounter_select"> + <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/> + <value value="1" name="PERF_RBBM_ALWAYS_ON"/> + <value value="2" name="PERF_RBBM_TSE_BUSY"/> + <value value="3" name="PERF_RBBM_RAS_BUSY"/> + <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/> + <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/> + <value value="6" name="PERF_RBBM_STATUS_MASKED"/> + <value value="7" name="PERF_RBBM_COM_BUSY"/> + <value value="8" name="PERF_RBBM_DCOM_BUSY"/> + <value value="9" name="PERF_RBBM_VBIF_BUSY"/> + <value value="10" name="PERF_RBBM_VSC_BUSY"/> + <value value="11" name="PERF_RBBM_TESS_BUSY"/> + <value value="12" name="PERF_RBBM_UCHE_BUSY"/> + <value value="13" name="PERF_RBBM_HLSQ_BUSY"/> +</enum> + +<enum name="a6xx_pc_perfcounter_select"> + <value value="0" name="PERF_PC_BUSY_CYCLES"/> + <value value="1" name="PERF_PC_WORKING_CYCLES"/> + <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/> + <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/> + <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/> + <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/> + <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/> + <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/> + <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/> + <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/> + <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/> + <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> + <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> + <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/> + <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/> + <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/> + <value value="16" name="PERF_PC_INSTANCES"/> + <value value="17" name="PERF_PC_VPC_PRIMITIVES"/> + <value value="18" name="PERF_PC_DEAD_PRIM"/> + <value value="19" name="PERF_PC_LIVE_PRIM"/> + <value value="20" name="PERF_PC_VERTEX_HITS"/> + <value value="21" name="PERF_PC_IA_VERTICES"/> + <value value="22" name="PERF_PC_IA_PRIMITIVES"/> + <value value="23" name="PERF_PC_GS_PRIMITIVES"/> + <value value="24" name="PERF_PC_HS_INVOCATIONS"/> + <value value="25" name="PERF_PC_DS_INVOCATIONS"/> + <value value="26" name="PERF_PC_VS_INVOCATIONS"/> + <value value="27" name="PERF_PC_GS_INVOCATIONS"/> + <value value="28" name="PERF_PC_DS_PRIMITIVES"/> + <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/> + <value value="30" name="PERF_PC_3D_DRAWCALLS"/> + <value value="31" name="PERF_PC_2D_DRAWCALLS"/> + <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> + <value value="33" name="PERF_TESS_BUSY_CYCLES"/> + <value value="34" name="PERF_TESS_WORKING_CYCLES"/> + <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/> + <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/> + <value value="37" name="PERF_PC_TSE_TRANSACTION"/> + <value value="38" name="PERF_PC_TSE_VERTEX"/> + <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/> + <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/> + <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/> +</enum> + +<enum name="a6xx_vfd_perfcounter_select"> + <value value="0" name="PERF_VFD_BUSY_CYCLES"/> + <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/> + <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> + <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/> + <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/> + <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/> + <value value="6" name="PERF_VFD_RBUFFER_FULL"/> + <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/> + <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> + <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/> + <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/> + <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/> + <value value="12" name="PERF_VFD_MODE_0_FIBERS"/> + <value value="13" name="PERF_VFD_MODE_1_FIBERS"/> + <value value="14" name="PERF_VFD_MODE_2_FIBERS"/> + <value value="15" name="PERF_VFD_MODE_3_FIBERS"/> + <value value="16" name="PERF_VFD_MODE_4_FIBERS"/> + <value value="17" name="PERF_VFD_TOTAL_VERTICES"/> + <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/> + <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> + <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/> + <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/> + <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/> +</enum> + +<enum name="a6xx_hlsq_perfcounter_select"> + <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/> + <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/> + <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/> + <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> + <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/> + <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/> + <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/> + <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/> + <value value="8" name="PERF_HLSQ_QUADS"/> + <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/> + <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/> + <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> + <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> + <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> + <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> + <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> + <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> + <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> + <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/> + <value value="19" name="PERF_HLSQ_PIXELS"/> + <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> +</enum> + +<enum name="a6xx_vpc_perfcounter_select"> + <value value="0" name="PERF_VPC_BUSY_CYCLES"/> + <value value="1" name="PERF_VPC_WORKING_CYCLES"/> + <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/> + <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/> + <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> + <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/> + <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/> + <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/> + <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/> + <value value="9" name="PERF_VPC_PC_PRIMITIVES"/> + <value value="10" name="PERF_VPC_SP_COMPONENTS"/> + <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> + <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> + <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/> + <value value="14" name="PERF_VPC_LM_TRANSACTION"/> + <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/> + <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/> + <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/> + <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/> + <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/> + <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/> + <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/> + <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/> + <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/> + <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> + <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/> + <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/> + <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/> +</enum> + +<enum name="a6xx_tse_perfcounter_select"> + <value value="0" name="PERF_TSE_BUSY_CYCLES"/> + <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/> + <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/> + <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> + <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> + <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/> + <value value="6" name="PERF_TSE_INPUT_PRIM"/> + <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/> + <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/> + <value value="9" name="PERF_TSE_CLIPPED_PRIM"/> + <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/> + <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/> + <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/> + <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/> + <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/> + <value value="15" name="PERF_TSE_CINVOCATION"/> + <value value="16" name="PERF_TSE_CPRIMITIVES"/> + <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/> + <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/> + <value value="19" name="PERF_TSE_CLIP_PLANES"/> +</enum> + +<enum name="a6xx_ras_perfcounter_select"> + <value value="0" name="PERF_RAS_BUSY_CYCLES"/> + <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> + <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/> + <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/> + <value value="4" name="PERF_RAS_SUPER_TILES"/> + <value value="5" name="PERF_RAS_8X4_TILES"/> + <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/> + <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/> + <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/> + <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/> + <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> + <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> + <value value="12" name="PERF_RAS_BLOCKS"/> +</enum> + +<enum name="a6xx_uche_perfcounter_select"> + <value value="0" name="PERF_UCHE_BUSY_CYCLES"/> + <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/> + <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/> + <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/> + <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/> + <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/> + <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> + <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/> + <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/> + <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/> + <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/> + <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/> + <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/> + <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/> + <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/> + <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/> + <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/> + <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/> + <value value="18" name="PERF_UCHE_EVICTS"/> + <value value="19" name="PERF_UCHE_BANK_REQ0"/> + <value value="20" name="PERF_UCHE_BANK_REQ1"/> + <value value="21" name="PERF_UCHE_BANK_REQ2"/> + <value value="22" name="PERF_UCHE_BANK_REQ3"/> + <value value="23" name="PERF_UCHE_BANK_REQ4"/> + <value value="24" name="PERF_UCHE_BANK_REQ5"/> + <value value="25" name="PERF_UCHE_BANK_REQ6"/> + <value value="26" name="PERF_UCHE_BANK_REQ7"/> + <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/> + <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/> + <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/> + <value value="30" name="PERF_UCHE_TPH_REF_FULL"/> + <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/> + <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/> + <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/> + <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/> + <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/> + <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/> + <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/> + <value value="38" name="PERF_UCHE_RAM_READ_REQ"/> + <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/> +</enum> + +<enum name="a6xx_tp_perfcounter_select"> + <value value="0" name="PERF_TP_BUSY_CYCLES"/> + <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/> + <value value="2" name="PERF_TP_LATENCY_CYCLES"/> + <value value="3" name="PERF_TP_LATENCY_TRANS"/> + <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/> + <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/> + <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/> + <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/> + <value value="8" name="PERF_TP_SP_TP_TRANS"/> + <value value="9" name="PERF_TP_TP_SP_TRANS"/> + <value value="10" name="PERF_TP_OUTPUT_PIXELS"/> + <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/> + <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/> + <value value="13" name="PERF_TP_QUADS_RECEIVED"/> + <value value="14" name="PERF_TP_QUADS_OFFSET"/> + <value value="15" name="PERF_TP_QUADS_SHADOW"/> + <value value="16" name="PERF_TP_QUADS_ARRAY"/> + <value value="17" name="PERF_TP_QUADS_GRADIENT"/> + <value value="18" name="PERF_TP_QUADS_1D"/> + <value value="19" name="PERF_TP_QUADS_2D"/> + <value value="20" name="PERF_TP_QUADS_BUFFER"/> + <value value="21" name="PERF_TP_QUADS_3D"/> + <value value="22" name="PERF_TP_QUADS_CUBE"/> + <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/> + <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/> + <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/> + <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/> + <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/> + <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/> + <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> + <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/> + <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/> + <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/> + <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/> + <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/> + <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> + <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> + <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> + <value value="38" name="PERF_TP_TPA2TPC_TRANS"/> + <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/> + <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/> + <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/> + <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/> + <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/> + <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/> + <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> + <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/> + <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> + <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/> + <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/> + <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> + <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> + <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/> + <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/> + <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> + <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/> + <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/> +</enum> + +<enum name="a6xx_sp_perfcounter_select"> + <value value="0" name="PERF_SP_BUSY_CYCLES"/> + <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/> + <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/> + <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/> + <value value="4" name="PERF_SP_STALL_CYCLES_TP"/> + <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/> + <value value="6" name="PERF_SP_STALL_CYCLES_RB"/> + <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/> + <value value="8" name="PERF_SP_WAVE_CONTEXTS"/> + <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/> + <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/> + <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/> + <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/> + <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/> + <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/> + <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/> + <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/> + <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/> + <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/> + <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/> + <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/> + <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/> + <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/> + <value value="23" name="PERF_SP_WAVE_END_CYCLES"/> + <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/> + <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> + <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/> + <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/> + <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/> + <value value="29" name="PERF_SP_LM_ATOMICS"/> + <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/> + <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/> + <value value="32" name="PERF_SP_GM_ATOMICS"/> + <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> + <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> + <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> + <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> + <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> + <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> + <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> + <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> + <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> + <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> + <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/> + <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/> + <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/> + <value value="46" name="PERF_SP_UCHE_READ_TRANS"/> + <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/> + <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/> + <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/> + <value value="50" name="PERF_SP_PIXELS_KILLED"/> + <value value="51" name="PERF_SP_ICL1_REQUESTS"/> + <value value="52" name="PERF_SP_ICL1_MISSES"/> + <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/> + <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/> + <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/> + <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/> + <value value="57" name="PERF_SP_GPR_READ"/> + <value value="58" name="PERF_SP_GPR_WRITE"/> + <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> + <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> + <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/> + <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> + <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> + <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> + <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/> + <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/> + <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/> + <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> + <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/> + <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/> + <value value="71" name="PERF_SP_WORKING_EU"/> + <value value="72" name="PERF_SP_ANY_EU_WORKING"/> + <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/> + <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/> + <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/> + <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/> + <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/> + <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/> + <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/> + <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/> + <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/> + <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/> + <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> + <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/> +</enum> + +<enum name="a6xx_rb_perfcounter_select"> + <value value="0" name="PERF_RB_BUSY_CYCLES"/> + <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/> + <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/> + <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/> + <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/> + <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/> + <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/> + <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/> + <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/> + <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/> + <value value="10" name="PERF_RB_Z_WORKLOAD"/> + <value value="11" name="PERF_RB_HLSQ_ACTIVE"/> + <value value="12" name="PERF_RB_Z_READ"/> + <value value="13" name="PERF_RB_Z_WRITE"/> + <value value="14" name="PERF_RB_C_READ"/> + <value value="15" name="PERF_RB_C_WRITE"/> + <value value="16" name="PERF_RB_TOTAL_PASS"/> + <value value="17" name="PERF_RB_Z_PASS"/> + <value value="18" name="PERF_RB_Z_FAIL"/> + <value value="19" name="PERF_RB_S_FAIL"/> + <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/> + <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/> + <value value="22" name="PERF_RB_PS_INVOCATIONS"/> + <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/> + <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/> + <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/> + <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/> + <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/> + <value value="28" name="PERF_RB_2D_VALID_PIXELS"/> + <value value="29" name="PERF_RB_3D_PIXELS"/> + <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/> + <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/> + <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/> + <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/> + <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> + <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> + <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> + <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> + <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/> + <value value="39" name="PERF_RB_2D_INPUT_TRANS"/> + <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> + <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> + <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/> + <value value="43" name="PERF_RB_COLOR_PIX_TILES"/> + <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/> + <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/> + <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/> + <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/> +</enum> + +<enum name="a6xx_vsc_perfcounter_select"> + <value value="0" name="PERF_VSC_BUSY_CYCLES"/> + <value value="1" name="PERF_VSC_WORKING_CYCLES"/> + <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/> + <value value="3" name="PERF_VSC_EOT_NUM"/> + <value value="4" name="PERF_VSC_INPUT_TILES"/> +</enum> + +<enum name="a6xx_ccu_perfcounter_select"> + <value value="0" name="PERF_CCU_BUSY_CYCLES"/> + <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> + <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> + <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/> + <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/> + <value value="5" name="PERF_CCU_COLOR_BLOCKS"/> + <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/> + <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/> + <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/> + <value value="9" name="PERF_CCU_GMEM_READ"/> + <value value="10" name="PERF_CCU_GMEM_WRITE"/> + <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/> + <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/> + <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/> + <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/> + <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/> + <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/> + <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/> + <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/> + <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/> + <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/> + <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/> + <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/> + <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/> + <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/> + <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/> + <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/> + <value value="27" name="PERF_CCU_2D_RD_REQ"/> + <value value="28" name="PERF_CCU_2D_WR_REQ"/> +</enum> + +<enum name="a6xx_lrz_perfcounter_select"> + <value value="0" name="PERF_LRZ_BUSY_CYCLES"/> + <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/> + <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/> + <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/> + <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/> + <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> + <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/> + <value value="7" name="PERF_LRZ_LRZ_READ"/> + <value value="8" name="PERF_LRZ_LRZ_WRITE"/> + <value value="9" name="PERF_LRZ_READ_LATENCY"/> + <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/> + <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> + <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/> + <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> + <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/> + <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/> + <value value="16" name="PERF_LRZ_TILE_KILLED"/> + <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/> + <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> + <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/> + <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/> + <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/> + <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/> + <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/> + <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> + <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> + <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/> + <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/> +</enum> + +<enum name="a6xx_cmp_perfcounter_select"> + <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/> + <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> + <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> + <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> + <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> + <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/> + <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> + <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/> + <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/> + <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/> + <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/> + <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> + <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> + <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> + <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> + <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> + <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> + <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> + <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> + <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> + <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> + <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> + <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> + <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> + <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> + <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/> + <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/> + <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/> + <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/> + <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/> + <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> + <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> + <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/> + <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> + <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> + <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> + <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> + <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/> + <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/> + <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/> +</enum> + +<!-- +Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the +component type/size, so I think it relates to internal format used for +blending? The one exception is that 16b unorm and 32b float use the +same value... maybe 16b unorm is uncommon enough that it was just easier +to upconvert to 32b float internally? + + 8b unorm: 10 +16b unorm: 4 + +32b int: 7 +16b int: 6 + 8b int: 5 + +32b float: 4 +16b float: 3 + --> +<enum name="a6xx_2d_ifmt"> + <value value="0x10" name="R2D_UNORM8"/> + <value value="0x7" name="R2D_INT32"/> + <value value="0x6" name="R2D_INT16"/> + <value value="0x5" name="R2D_INT8"/> + <value value="0x4" name="R2D_FLOAT32"/> + <value value="0x3" name="R2D_FLOAT16"/> +</enum> + +<domain name="A6XX" width="32"> + <bitset name="A6XX_RBBM_INT_0_MASK"> + <bitfield name="RBBM_GPU_IDLE" pos="0"/> + <bitfield name="CP_AHB_ERROR" pos="1"/> + <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/> + <bitfield name="RBBM_GPC_ERROR" pos="7"/> + <bitfield name="CP_SW" pos="8"/> + <bitfield name="CP_HW_ERROR" pos="9"/> + <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/> + <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/> + <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/> + <bitfield name="CP_IB2" pos="13"/> + <bitfield name="CP_IB1" pos="14"/> + <bitfield name="CP_RB" pos="15"/> + <bitfield name="CP_RB_DONE_TS" pos="17"/> + <bitfield name="CP_WT_DONE_TS" pos="18"/> + <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/> + <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/> + <bitfield name="RBBM_HANG_DETECT" pos="23"/> + <bitfield name="UCHE_OOB_ACCESS" pos="24"/> + <bitfield name="UCHE_TRAP_INTR" pos="25"/> + <bitfield name="DEBBUS_INTR_0" pos="26"/> + <bitfield name="DEBBUS_INTR_1" pos="27"/> + <bitfield name="ISDB_CPU_IRQ" pos="30"/> + <bitfield name="ISDB_UNDER_DEBUG" pos="31"/> + </bitset> + + <bitset name="A6XX_CP_INT"> + <bitfield name="CP_OPCODE_ERROR" pos="0"/> + <bitfield name="CP_UCODE_ERROR" pos="1"/> + <bitfield name="CP_HW_FAULT_ERROR" pos="2"/> + <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/> + <bitfield name="CP_AHB_ERROR" pos="5"/> + <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/> + <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/> + </bitset> + + <reg32 offset="0x0800" name="CP_RB_BASE"/> + <reg32 offset="0x0801" name="CP_RB_BASE_HI"/> + <reg32 offset="0x0802" name="CP_RB_CNTL"/> + <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/> + <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/> + <reg32 offset="0x0806" name="CP_RB_RPTR"/> + <reg32 offset="0x0807" name="CP_RB_WPTR"/> + <reg32 offset="0x0808" name="CP_SQE_CNTL"/> + <reg32 offset="0x0821" name="CP_HW_FAULT"/> + <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/> + <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/> + <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/> + <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/> + <reg32 offset="0x0840" name="CP_MISC_CNTL"/> + <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1"/> + <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2"/> + <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/> + <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/> + <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/> + <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/> + <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/> + + <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8"> + <reg32 offset="0x0" name="REG" type="uint"/> + </array> + <array offset="0x0850" name="CP_PROTECT" stride="1" length="32"> + <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> + </array> + + <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/> + <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/> + <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/> + <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/> + <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/> + <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/> + <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/> + <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/> + <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/> + <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/> + <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/> + <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/> + <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/> + <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/> + <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/> + <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/> + <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/> + <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/> + <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/> + <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/> + <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/> + <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/> + <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/> + <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/> + <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/> + <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/> + <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/> + <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/> + <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/> + <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/> + <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/> + <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/> + <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/> + <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/> + <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/> + <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/> + <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/> + <reg32 offset="0x0928" name="CP_IB1_BASE"/> + <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/> + <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/> + <reg32 offset="0x092B" name="CP_IB2_BASE"/> + <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/> + <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/> + <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/> + <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/> + <reg32 offset="0x098D" name="CP_AHB_CNTL"/> + <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/> + <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/> + <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/> + <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/> + <reg32 offset="0x0210" name="RBBM_STATUS"> + <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" /> + <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" /> + <bitfield high="21" low="21" name="HLSQ_BUSY" /> + <bitfield high="20" low="20" name="VSC_BUSY" /> + <bitfield high="19" low="19" name="TPL1_BUSY" /> + <bitfield high="18" low="18" name="SP_BUSY" /> + <bitfield high="17" low="17" name="UCHE_BUSY" /> + <bitfield high="16" low="16" name="VPC_BUSY" /> + <bitfield high="15" low="15" name="VFD_BUSY" /> + <bitfield high="14" low="14" name="TESS_BUSY" /> + <bitfield high="13" low="13" name="PC_VSD_BUSY" /> + <bitfield high="12" low="12" name="PC_DCALL_BUSY" /> + <bitfield high="11" low="11" name="COM_DCOM_BUSY" /> + <bitfield high="10" low="10" name="LRZ_BUSY" /> + <bitfield high="9" low="9" name="A2D_BUSY" /> + <bitfield high="8" low="8" name="CCU_BUSY" /> + <bitfield high="7" low="7" name="RB_BUSY" /> + <bitfield high="6" low="6" name="RAS_BUSY" /> + <bitfield high="5" low="5" name="TSE_BUSY" /> + <bitfield high="4" low="4" name="VBIF_BUSY" /> + <bitfield high="3" low="3" name="GFX_DBGC_BUSY" /> + <bitfield high="2" low="2" name="CP_BUSY" /> + <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" /> + <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/> + </reg32> + <reg32 offset="0x0213" name="RBBM_STATUS3"/> + <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/> + <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/> + <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/> + <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/> + <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/> + <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/> + <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/> + <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/> + <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/> + <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/> + <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/> + <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/> + <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/> + <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/> + <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/> + <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/> + <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/> + <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/> + <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/> + <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/> + <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/> + <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/> + <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/> + <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/> + <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/> + <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/> + <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/> + <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/> + <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/> + <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/> + <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/> + <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/> + <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/> + <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/> + <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/> + <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/> + <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/> + <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/> + <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/> + <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/> + <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/> + <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/> + <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/> + <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/> + <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/> + <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/> + <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/> + <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/> + <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/> + <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/> + <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/> + <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/> + <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/> + <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/> + <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/> + <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/> + <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/> + <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/> + <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/> + <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/> + <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/> + <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/> + <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/> + <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/> + <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/> + <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/> + <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/> + <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/> + <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/> + <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/> + <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/> + <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/> + <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/> + <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/> + <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/> + <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/> + <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/> + <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/> + <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/> + <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/> + <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/> + <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/> + <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/> + <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/> + <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/> + <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/> + <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/> + <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/> + <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/> + <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/> + <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/> + <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/> + <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/> + <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/> + <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/> + <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/> + <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/> + <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/> + <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/> + <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/> + <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/> + <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/> + <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/> + <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/> + <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/> + <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/> + <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/> + <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/> + <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/> + <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/> + <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/> + <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/> + <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/> + <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/> + <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/> + <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/> + <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/> + <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/> + <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/> + <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/> + <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/> + <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/> + <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/> + <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/> + <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/> + <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/> + <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/> + <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/> + <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/> + <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/> + <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/> + <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/> + <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/> + <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/> + <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/> + <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/> + <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/> + <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/> + <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/> + <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/> + <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/> + <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/> + <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/> + <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/> + <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/> + <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/> + <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/> + <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/> + <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/> + <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/> + <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/> + <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/> + <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/> + <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/> + <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/> + <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/> + <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/> + <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/> + <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/> + <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/> + <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/> + <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/> + <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/> + <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/> + <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/> + <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/> + <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/> + <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/> + <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/> + <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/> + <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/> + <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/> + <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/> + <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/> + <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/> + <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/> + <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/> + <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/> + <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/> + <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/> + <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/> + <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/> + <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/> + <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/> + <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/> + <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/> + <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/> + <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/> + <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/> + <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/> + <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/> + <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/> + <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/> + <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/> + <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/> + <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/> + <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/> + <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/> + <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/> + <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/> + <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/> + <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/> + <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/> + <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/> + <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/> + <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/> + <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/> + <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/> + <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/> + <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/> + <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/> + <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/> + <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/> + <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/> + <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/> + <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/> + <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/> + <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/> + <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/> + <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/> + <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/> + <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/> + <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/> + <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/> + <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/> + <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/> + <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/> + <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/> + <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/> + <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/> + <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/> + <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/> + <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/> + <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/> + <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/> + <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/> + <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/> + <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/> + <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/> + <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/> + <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/> + <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/> + <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/> + <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/> + <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/> + <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/> + <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/> + <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/> + <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/> + <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/> + <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/> + <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/> + <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/> + <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/> + <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/> + <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/> + <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/> + <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/> + <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/> + <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/> + <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/> + <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/> + <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/> + <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/> + <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> + <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/> + <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/> + <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/> + <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/> + <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/> + <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/> + <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> + <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/> + <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/> + <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/> + <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/> + <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/> + <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/> + <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/> + <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/> + <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/> + <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/> + <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/> + <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/> + <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/> + <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/> + <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/> + <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/> + <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/> + <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/> + <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/> + <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/> + <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/> + <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/> + <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/> + <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/> + <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/> + <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/> + <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/> + <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/> + <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/> + <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/> + <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/> + <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/> + <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/> + <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/> + <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/> + <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/> + <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/> + <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/> + <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/> + <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/> + <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/> + <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/> + <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/> + <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/> + <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/> + <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/> + <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/> + <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/> + <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/> + <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/> + <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/> + <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/> + <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/> + <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/> + <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/> + <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/> + <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/> + <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/> + <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/> + <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/> + <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/> + <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/> + <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/> + <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/> + <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/> + <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/> + <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/> + <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/> + <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/> + <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/> + <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/> + <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/> + <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/> + <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/> + <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/> + <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/> + <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/> + <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/> + <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/> + <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/> + <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/> + <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/> + <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/> + <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/> + <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/> + <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/> + <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/> + <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/> + <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/> + <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/> + <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/> + <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/> + <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/> + <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/> + <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/> + <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/> + <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/> + <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/> + <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/> + <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/> + <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/> + <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/> + <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/> + <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/> + <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/> + <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/> + <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/> + <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/> + <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/> + <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/> + <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/> + <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/> + <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/> + <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/> + <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/> + <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/> + <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D"> + <bitfield high="7" low="0" name="PING_INDEX"/> + <bitfield high="15" low="8" name="PING_BLK_SEL"/> + </reg32> + <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT"> + <bitfield high="5" low="0" name="TRACEEN"/> + <bitfield high="14" low="12" name="GRANU"/> + <bitfield high="31" low="28" name="SEGT"/> + </reg32> + <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM"> + <bitfield high="27" low="24" name="ENABLE"/> + </reg32> + <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/> + <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/> + <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/> + <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/> + <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/> + <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/> + <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/> + <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/> + <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0"> + <bitfield high="3" low="0" name="BYTEL0"/> + <bitfield high="7" low="4" name="BYTEL1"/> + <bitfield high="11" low="8" name="BYTEL2"/> + <bitfield high="15" low="12" name="BYTEL3"/> + <bitfield high="19" low="16" name="BYTEL4"/> + <bitfield high="23" low="20" name="BYTEL5"/> + <bitfield high="27" low="24" name="BYTEL6"/> + <bitfield high="31" low="28" name="BYTEL7"/> + </reg32> + <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1"> + <bitfield high="3" low="0" name="BYTEL8"/> + <bitfield high="7" low="4" name="BYTEL9"/> + <bitfield high="11" low="8" name="BYTEL10"/> + <bitfield high="15" low="12" name="BYTEL11"/> + <bitfield high="19" low="16" name="BYTEL12"/> + <bitfield high="23" low="20" name="BYTEL13"/> + <bitfield high="27" low="24" name="BYTEL14"/> + <bitfield high="31" low="28" name="BYTEL15"/> + </reg32> + <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/> + <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/> + <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/> + <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/> + <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/> + <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/> + <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/> + <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/> + <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/> + <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/> + <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/> + <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/> + <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/> + <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/> + <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/> + <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/> + <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/> + <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/> + <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/> + <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/> + <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/> + <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/> + <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/> + <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/> + <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/> + <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/> + <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/> + <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/> + <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/> + <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/> + <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/> + <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/> + <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/> + <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/> + <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/> + <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/> + <reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/> + <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/> + <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/> + <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/> + <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/> + <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/> + <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/> + <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/> + <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/> + <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/> + <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/> + <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/> + <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/> + <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/> + <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/> + <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/> + <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/> + <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/> + <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/> + <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/> + <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/> + <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/> + <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/> + <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/> + <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/> + <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/> + <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/> + <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/> + <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/> + <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/> + <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/> + <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/> + <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/> + <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/> + <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/> + <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/> + <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/> + <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/> + <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/> + <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/> + <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/> + <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/> + <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/> + <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/> + <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/> + <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/> + <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/> + <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/> + <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/> + <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/> + <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/> + <reg32 offset="0x0E19" name="UCHE_CLIENT_PF"> + <bitfield high="7" low="0" name="PERFSEL"/> + </reg32> + <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/> + <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/> + <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/> + <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/> + <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/> + <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/> + <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/> + <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/> + <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/> + <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/> + <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/> + <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/> + <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/> + <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/> + <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/> + <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/> + <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/> + <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/> + <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/> + <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/> + <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/> + <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/> + <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/> + <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/> + <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/> + <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/> + <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/> + <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/> + <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/> + <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/> + <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/> + <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/> + <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/> + <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/> + <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/> + <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/> + <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/> + <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/> + <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/> + <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/> + <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/> + <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/> + <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/> + <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/> + <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/> + <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/> + <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/> + <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/> + <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/> + <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/> + <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/> + <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/> + <reg32 offset="0x3000" name="VBIF_VERSION"/> + <reg32 offset="0x3001" name="VBIF_CLKON"> + <bitfield pos="1" name="FORCE_ON_TESTBUS"/> + </reg32> + <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/> + <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/> + <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/> + <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/> + <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/> + <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"> + <bitfield low="0" high="3" name="DATA_SEL"/> + </reg32> + <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/> + <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"> + <bitfield low="0" high="8" name="DATA_SEL"/> + </reg32> + <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/> + <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/> + <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/> + <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/> + <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/> + <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/> + <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/> + <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/> + <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/> + <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/> + <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/> + <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/> + <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/> + <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/> + <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/> + <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/> + <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/> + <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/> + <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/> + <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/> + <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/> + <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/> + + <!-- move/rename these.. --> + + <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/> + <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/> + <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/> + + <!-- same as RB_BIN_CONTROL --> + <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL"> + <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/> + <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/> + <bitfield name="BINNING_PASS" pos="18" type="boolean"/> + <bitfield name="USE_VIZ" pos="21" type="boolean"/> + </reg32> + + <!-- + from offset it seems it should be RB, but weird to duplicate + other regs from same block?? + --> + <reg32 offset="0x88d3" name="RB_BIN_CONTROL2"> + <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/> + <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/> + </reg32> + + <reg32 offset="0x0c02" name="VSC_BIN_SIZE"> + <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/> + <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/> + </reg32> + <reg32 offset="0x0c03" name="VSC_SIZE_ADDRESS_LO"/> + <reg32 offset="0x0c04" name="VSC_SIZE_ADDRESS_HI"/> + <reg32 offset="0x0c06" name="VSC_BIN_COUNT"> + <bitfield name="NX" low="1" high="10" type="uint"/> + <bitfield name="NY" low="11" high="20" type="uint"/> + </reg32> + <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32"> + <reg32 offset="0x0" name="REG"> + <doc> + Configures the mapping between VSC_PIPE buffer and + bin, X/Y specify the bin index in the horiz/vert + direction (0,0 is upper left, 0,1 is leftmost bin + on second row, and so on). W/H specify the number + of bins assigned to this VSC_PIPE in the horiz/vert + dimension. + </doc> + <bitfield name="X" low="0" high="9" type="uint"/> + <bitfield name="Y" low="10" high="19" type="uint"/> + <bitfield name="W" low="20" high="25" type="uint"/> + <bitfield name="H" low="26" high="31" type="uint"/> + </reg32> + </array> + <!-- + compared to a5xx and earlier, we just program the address of the first + visibility stream and hw adds (pipe_num * VSC_PIPE_DATA_PITCH) + + TODO now there seem to be two buffers of VSC data (both referenced by + CP_SET_BIN_DATA packet. Not sure what this new DATA2 one is, but seems + to have the larger pitch. + --> + <reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/> + <reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/> + <reg32 offset="0x0c32" name="VSC_PIPE_DATA2_PITCH"/> + <reg32 offset="0x0c33" name="VSC_PIPE_DATA2_ARRAY_PITCH" shr="4" type="uint"/> + <reg32 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS_LO"/> + <reg32 offset="0x0c35" name="VSC_PIPE_DATA_ADDRESS_HI"/> + <reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/> + <reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/> + + <!-- + note, also a range starting at 0x0c58, one or the other probably + corresponds to the new "VSC_XXX" thing, whatever it is.. + --> + <array offset="0x0c78" name="VSC_SIZE" stride="1" length="32"> + <doc> + Has the size of data written to corresponding VSC pipe, ie. + same thing that is written out to VSC_SIZE_ADDRESS_LO/HI + </doc> + <reg32 offset="0x0" name="REG"/> + </array> + + <!-- always 0x03200000 ? --> + <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/> + + <reg32 offset="0x8000" name="GRAS_UNKNOWN_8000"/> + <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/> + + <!-- always 0x0 ? --> + <reg32 offset="0x8004" name="GRAS_UNKNOWN_8004"/> + + <reg32 offset="0x8005" name="GRAS_CNTL"> + <!-- see also RB_RENDER_CONTROL0 --> + <bitfield name="VARYING" pos="0" type="boolean"/> + <!-- b1 set for interpolateAtCentroid() --> + <bitfield name="CENTROID" pos="1" type="boolean"/> + <!-- b2 set instead of b0 when running in per-sample mode --> + <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/> + <!-- + b3 set for interpolateAt{Offset,Sample}() if not in per-sample + mode, and frag_face + --> + <bitfield name="SIZE" pos="3" type="boolean"/> + <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode --> + <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/> + <bitfield name="XCOORD" pos="6" type="boolean"/> + <bitfield name="YCOORD" pos="7" type="boolean"/> + <bitfield name="ZCOORD" pos="8" type="boolean"/> + <bitfield name="WCOORD" pos="9" type="boolean"/> + </reg32> + <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ"> + <bitfield name="HORZ" low="0" high="9" type="uint"/> + <bitfield name="VERT" low="10" high="19" type="uint"/> + </reg32> + <reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/> + <reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/> + <reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/> + <reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/> + <reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/> + <reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/> + + <reg32 offset="0x8090" name="GRAS_SU_CNTL"> + <bitfield name="CULL_FRONT" pos="0" type="boolean"/> + <bitfield name="CULL_BACK" pos="1" type="boolean"/> + <bitfield name="FRONT_CW" pos="2" type="boolean"/> + <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/> + <bitfield name="POLY_OFFSET" pos="11" type="boolean"/> + <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/> + <!-- probably LINEHALFWIDTH is the same as a4xx.. --> + </reg32> + <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX"> + <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> + <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> + </reg32> + <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/> + + <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL"> + <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/> + <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/> + <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/> + <!-- duplicates RB_DEPTH_BUFFER_INFO: --> + <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO"> + <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> + </reg32> + + <!-- always 0x0 --> + <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/> + + <!-- always 0x0 ? --> + <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/> + + <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/> + + <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + </reg32> + <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> + </reg32> + + <!-- always 0x0 --> + <reg32 offset="0x80a4" name="GRAS_UNKNOWN_80A4"/> + <!-- always 0x0 --> + <reg32 offset="0x80a5" name="GRAS_UNKNOWN_80A5"/> + <!-- always 0x0 --> + <reg32 offset="0x80a6" name="GRAS_UNKNOWN_80A6"/> + <!-- always 0x0 --> + <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/> + + <reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/> + <reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/> + <reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/> + <reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/> + <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/> + <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/> + + <reg32 offset="0x8100" name="GRAS_LRZ_CNTL"> + <!-- + These bits seems to mostly fit.. but wouldn't hurt to have a 2nd + look when we get around to enabling lrz + --> + <bitfield name="ENABLE" pos="0" type="boolean"/> + <doc>LRZ write also disabled for blend/etc.</doc> + <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> + <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc> + <bitfield name="GREATER" pos="2" type="boolean"/> + <!-- set at end of batch that had LRZ enabled (to flush/disable it?) --> + <bitfield name="UNK3" pos="3" type="boolean"/> + <!-- set when depth-test + depth-write enabled --> + <bitfield name="UNK4" pos="4" type="boolean"/> + </reg32> + <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/> + <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/> + </reg32> + <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/> + <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/> + <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH"> + <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/> + <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? --> + </reg32> + <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/> + <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/> + + <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL"> + <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> + </reg32> + + <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/> + + <enum name="a6xx_rotation"> + <value value="0x0" name="ROTATE_0"/> + <value value="0x1" name="ROTATE_90"/> + <value value="0x2" name="ROTATE_180"/> + <value value="0x3" name="ROTATE_270"/> + </enum> + + <bitset name="a6xx_2d_blit_cntl" inline="yes"> + <bitfield name="ROTATE" low="0" high="1" type="a6xx_rotation"/> + <bitfield name="HORIZONTAL_FLIP" low="2" high="2" type="boolean"/> + <bitfield name="SOLID_COLOR" low="4" high="4" type="boolean"/> + <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_color_fmt"/> + <bitfield name="SCISSOR" pos="16" type="boolean"/> + <!-- double check these: + <bitfield name="FLAGS" pos="18" type="boolean"/> + <bitfield name="TILE_MODE" low="20" high="21" type="a6xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="22" high="23" type="a3xx_color_swap"/> + --> + <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/> + </bitset> + + <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/> + + <!-- could be the src coords are fixed point? --> + <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X"> + <bitfield name="X" low="8" high="31" type="int"/> + </reg32> + <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X"> + <bitfield name="X" low="8" high="31" type="int"/> + </reg32> + <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y"> + <bitfield name="Y" low="8" high="31" type="int"/> + </reg32> + <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y"> + <bitfield name="Y" low="8" high="31" type="int"/> + </reg32> + + <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/> + <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/> + + <reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/> + <reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/> + + <!-- always 0x880 ? --> + <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/> + + <!-- same as GRAS_BIN_CONTROL: --> + <reg32 offset="0x8800" name="RB_BIN_CONTROL"> + <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/> + <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/> + <bitfield name="BINNING_PASS" pos="18" type="boolean"/> + <bitfield name="USE_VIZ" pos="21" type="boolean"/> + </reg32> + <reg32 offset="0x8801" name="RB_RENDER_CNTL"> + <!-- always set: ?? --> + <bitfield name="UNK4" pos="4" type="boolean"/> + <!-- set during binning pass: --> + <bitfield name="BINNING" pos="7" type="boolean"/> + <!-- bit seems to be set whenever depth buffer enabled: --> + <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/> + <!-- bitmask of MRTs using UBWC flag buffer: --> + <bitfield name="FLAG_MRTS" low="16" high="23"/> + </reg32> + <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + </reg32> + <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> + </reg32> + + <!-- always 0x0 ? --> + <reg32 offset="0x8804" name="RB_UNKNOWN_8804"/> + <!-- always 0x0 ? --> + <reg32 offset="0x8805" name="RB_UNKNOWN_8805"/> + <!-- always 0x0 ? --> + <reg32 offset="0x8806" name="RB_UNKNOWN_8806"/> + + <!-- + note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL + name comes from kernel and is probably right) + --> + <reg32 offset="0x8809" name="RB_RENDER_CONTROL0"> + <!-- see also GRAS_CNTL --> + <bitfield name="VARYING" pos="0" type="boolean"/> + <!-- b1 set for interpolateAtCentroid() --> + <bitfield name="CENTROID" pos="1" type="boolean"/> + <!-- b2 set instead of b0 when running in per-sample mode --> + <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/> + <!-- + b3 set for interpolateAt{Offset,Sample}() if not in per-sample + mode, and frag_face + --> + <bitfield name="SIZE" pos="3" type="boolean"/> + <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode --> + <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/> + <bitfield name="XCOORD" pos="6" type="boolean"/> + <bitfield name="YCOORD" pos="7" type="boolean"/> + <bitfield name="ZCOORD" pos="8" type="boolean"/> + <bitfield name="WCOORD" pos="9" type="boolean"/> + <bitfield name="UNK10" pos="10" type="boolean"/> + </reg32> + <reg32 offset="0x880a" name="RB_RENDER_CONTROL1"> + <!-- enable bits for various FS sysvalue regs: --> + <bitfield name="SAMPLEMASK" pos="0" type="boolean"/> + <bitfield name="FACENESS" pos="2" type="boolean"/> + <bitfield name="SAMPLEID" pos="3" type="boolean"/> + <!-- b4 and b5 set in per-sample mode: --> + <bitfield name="UNK4" pos="4" type="boolean"/> + <bitfield name="UNK5" pos="5" type="boolean"/> + <bitfield name="SIZE" pos="6" type="boolean"/> + </reg32> + + <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0"> + <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/> + <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/> + </reg32> + <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1"> + <bitfield name="MRT" low="0" high="3" type="uint"/> + </reg32> + <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS"> + <bitfield name="RT0" low="0" high="3"/> + <bitfield name="RT1" low="4" high="7"/> + <bitfield name="RT2" low="8" high="11"/> + <bitfield name="RT3" low="12" high="15"/> + <bitfield name="RT4" low="16" high="19"/> + <bitfield name="RT5" low="20" high="23"/> + <bitfield name="RT6" low="24" high="27"/> + <bitfield name="RT7" low="28" high="31"/> + </reg32> + <reg32 offset="0x880e" name="RB_DITHER_CNTL"> + <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> + <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> + <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> + <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> + <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> + <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> + <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/> + <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> + </reg32> + <reg32 offset="0x880f" name="RB_SRGB_CNTL"> + <!-- Same as SP_SRGB_CNTL --> + <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> + <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> + <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> + <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> + <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> + <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> + <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> + <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> + </reg32> + + <reg32 offset="0x8810" name="RB_SAMPLE_CNTL"> + <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x8811" name="RB_UNKNOWN_8811"/> + + <!-- always 0x0 ? --> + <reg32 offset="0x8818" name="RB_UNKNOWN_8818"/> + <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/> + <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/> + <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/> + <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/> + <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/> + <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/> + + <array offset="0x8820" name="RB_MRT" stride="8" length="8"> + <reg32 offset="0x0" name="CONTROL"> + <bitfield name="BLEND" pos="0" type="boolean"/> + <bitfield name="BLEND2" pos="1" type="boolean"/> + <bitfield name="ROP_ENABLE" pos="2" type="boolean"/> + <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/> + <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/> + </reg32> + <reg32 offset="0x1" name="BLEND_CONTROL"> + <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/> + <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/> + <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/> + <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/> + <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/> + </reg32> + <reg32 offset="0x2" name="BUF_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/> + <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> + </reg32> + <!-- + at least in gmem, things seem to be aligned to pitch of 64.. + maybe an artifact of tiled format used in gmem? + --> + <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/> + <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/> + <!-- + Compared to a5xx and before, we configure both a GMEM base and + external base. Not sure if this is to facilitate GMEM save/ + restore for context switch, or just to simplify state setup to + not have to care about GMEM vs BYPASS mode. + --> + <reg32 offset="0x5" name="BASE_LO"/> + <reg32 offset="0x6" name="BASE_HI"/> + <reg32 offset="0x7" name="BASE_GMEM"/> + </array> + + <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/> + <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/> + <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/> + <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/> + <reg32 offset="0x8864" name="RB_ALPHA_CONTROL"> + <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> + <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> + <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> + </reg32> + <reg32 offset="0x8865" name="RB_BLEND_CNTL"> + <!-- per-mrt enable bit --> + <bitfield name="ENABLE_BLEND" low="0" high="7"/> + <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> + <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> + <bitfield name="SAMPLE_MASK" low="16" high="31"/> + </reg32> + <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL"> + <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/> + </reg32> + + <reg32 offset="0x8871" name="RB_DEPTH_CNTL"> + <bitfield name="Z_ENABLE" pos="0" type="boolean"/> + <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/> + <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/> + <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc> + <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/> + </reg32> + <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: --> + <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO"> + <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> + </reg32> +<!-- probably: --> + <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint"> + <doc>stride of depth/stencil buffer</doc> + </reg32> + <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint"> + <doc>size of layer</doc> + </reg32> + <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/> + <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/> + <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/> + + <!-- always 0x0 ? --> + <reg32 offset="0x8878" name="RB_UNKNOWN_8878"/> + <!-- always 0x0 ? --> + <reg32 offset="0x8879" name="RB_UNKNOWN_8879"/> + + <reg32 offset="0x8880" name="RB_STENCIL_CONTROL"> + <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> + <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> + <!-- + set for stencil operations that require read from stencil + buffer, but not for example for stencil clear (which does + not require read).. so guessing this is analogous to + READ_DEST_ENABLE for color buffer.. + --> + <bitfield name="STENCIL_READ" pos="2" type="boolean"/> + <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/> + <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/> + <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/> + <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/> + <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/> + <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/> + <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> + <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> + </reg32> + <reg32 offset="0x8881" name="RB_STENCIL_INFO"> + <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint"> + <doc>stride of stencil buffer</doc> + </reg32> + <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint"> + <doc>size of layer</doc> + </reg32> + <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/> + <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/> + <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/> + <reg32 offset="0x8887" name="RB_STENCILREF"> + <bitfield name="REF" low="0" high="7"/> + <bitfield name="BFREF" low="8" high="15"/> + </reg32> + <reg32 offset="0x8888" name="RB_STENCILMASK"> + <bitfield name="MASK" low="0" high="7"/> + <bitfield name="BFMASK" low="8" high="15"/> + </reg32> + <reg32 offset="0x8889" name="RB_STENCILWRMASK"> + <bitfield name="WRMASK" low="0" high="7"/> + <bitfield name="BFWRMASK" low="8" high="15"/> + </reg32> + <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/> + <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL"> + <bitfield name="COPY" pos="1" type="boolean"/> + </reg32> + + <reg32 offset="0x8898" name="RB_LRZ_CNTL"> + <bitfield name="ENABLE" pos="0" type="boolean"/> + </reg32> + + <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/> + <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/> + <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/> + + <reg32 offset="0x88d5" name="RB_MSAA_CNTL"> + <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> + </reg32> + <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/> + <!-- s/DST_FORMAT/DST_INFO/ probably: --> + <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO"> + <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> + <bitfield name="FLAGS" pos="2" type="boolean"/> + <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> + <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_color_fmt"/> + <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/> + </reg32> + <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/> + <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/> + <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/> + <!-- array-pitch is size of layer --> + <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/> + <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/> + <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/> + <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH"> + <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> + <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> + </reg32> + + <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/> + <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/> + <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/> + <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/> + + <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: --> + <reg32 offset="0x88e3" name="RB_BLIT_INFO"> + <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? --> + <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? --> + <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably --> + <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? --> + <doc> + For clearing depth/stencil + 1 - depth + 2 - stencil + 3 - depth+stencil + For clearing color buffer: + then probably a component mask, I always see 0xf + </doc> + <bitfield name="CLEAR_MASK" low="4" high="7"/> + </reg32> + + <!-- always 0x0 ? --> + <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/> + + <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/> + <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/> + <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH"> + <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> + <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> + </reg32> + <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8"> + <reg32 offset="0" name="ADDR_LO"/> + <reg32 offset="1" name="ADDR_HI"/> + <reg32 offset="2" name="PITCH"> + <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> + <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? --> + </reg32> + </array> + <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/> + <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/> + + <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/> + <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/> + + <reg32 offset="0x8c17" name="RB_2D_DST_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/> + <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> + <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled --> + <bitfield name="FLAGS" pos="12" type="boolean"/> + </reg32> + <reg32 offset="0x8c18" name="RB_2D_DST_LO"/> + <reg32 offset="0x8c19" name="RB_2D_DST_HI"/> + <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE"> + <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/> + </reg32> + + <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/> + <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/> + <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH"> + <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> + <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> + </reg32> + + <!-- unlike a5xx, these are per channel values rather than packed --> + <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/> + <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/> + <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/> + <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/> + + <!-- always 0x1 ? --> + <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/> + + <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/> + + <reg32 offset="0x8e07" name="RB_CCU_CNTL"/> <!-- always 7c400004 or 10000000 --> + + <!-- always 0x00ffff00 ? */ --> + <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/> + + <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/> + + <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/> + <reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/> + + <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8"> + <reg32 offset="0x0" name="MODE"/> + </array> + <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8"> + <reg32 offset="0x0" name="MODE"/> + </array> + + <!-- always 0x0 --> + <reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/> + <reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/> + + <array offset="0x9212" name="VPC_VAR" stride="1" length="4"> + <!-- one bit per varying component: --> + <reg32 offset="0" name="DISABLE"/> + </array> + + <reg32 offset="0x9216" name="VPC_SO_CNTL"> + <!-- always 0x10000 when SO enabled.. --> + <bitfield name="ENABLE" pos="16" type="boolean"/> + </reg32> + <reg32 offset="0x9217" name="VPC_SO_PROG"> + <bitfield name="A_BUF" low="0" high="1" type="uint"/> + <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> + <bitfield name="A_EN" pos="11" type="boolean"/> + <bitfield name="B_BUF" low="12" high="13" type="uint"/> + <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> + <bitfield name="B_EN" pos="23" type="boolean"/> + </reg32> + <array offset="0x921a" name="VPC_SO" stride="7" length="4"> + <reg32 offset="0" name="BUFFER_BASE_LO"/> + <reg32 offset="1" name="BUFFER_BASE_HI"/> + <reg32 offset="2" name="BUFFER_SIZE"/> + <reg32 offset="3" name="NCOMP"/> <!-- component count --> + <reg32 offset="4" name="BUFFER_OFFSET"/> + <reg32 offset="5" name="FLUSH_BASE_LO"/> + <reg32 offset="6" name="FLUSH_BASE_HI"/> + </array> + + <!-- always 0x0 ? --> + <reg32 offset="0x9236" name="VPC_UNKNOWN_9236"> + <bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/> + </reg32> + + <!-- always 0x0 ? --> + <reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/> + + <reg32 offset="0x9301" name="VPC_PACK"> + <doc> + num of varyings plus four for gl_Position (plus one if gl_PointSize) + plus # of transform-feedback (streamout) varyings if using the + hw streamout (rather than stg instructions in shader) + </doc> + <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> + <bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/> + <!-- + This seems to be the OUTLOC for the psize output. It could possibly + be the max-OUTLOC position, but it is only set when VS writes psize + (and blob always puts psize at highest OUTLOC) + --> + <bitfield name="PSIZELOC" low="16" high="23" type="uint"/> + </reg32> + + <reg32 offset="0x9303" name="VPC_PACK_3"> + <doc> + domain shader version + + num of varyings plus four for gl_Position (plus one if gl_PointSize) + plus # of transform-feedback (streamout) varyings if using the + hw streamout (rather than stg instructions in shader) + </doc> + <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> + <bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/> + <!-- + This seems to be the OUTLOC for the psize output. It could possibly + be the max-OUTLOC position, but it is only set when VS writes psize + (and blob always puts psize at highest OUTLOC) + --> + <bitfield name="PSIZELOC" low="16" high="23" type="uint"/> + </reg32> + + <reg32 offset="0x9304" name="VPC_CNTL_0"> + <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> + <bitfield name="VARYING" pos="16" type="boolean"/> + </reg32> + + <reg32 offset="0x9305" name="VPC_SO_BUF_CNTL"> + <bitfield name="BUF0" pos="0" type="boolean"/> + <bitfield name="BUF1" pos="3" type="boolean"/> + <bitfield name="BUF2" pos="6" type="boolean"/> + <bitfield name="BUF3" pos="9" type="boolean"/> + <bitfield name="ENABLE" pos="15" type="boolean"/> + </reg32> + <reg32 offset="0x9306" name="VPC_SO_OVERRIDE"> + <bitfield name="SO_DISABLE" pos="0" type="boolean"/> + </reg32> + + <!-- always 0x0 ? --> + <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/> + <!-- always 0x0 ? --> + <reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/> + + <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/> + + <!-- always 0x0 ? --> + <reg32 offset="0x9801" name="PC_UNKNOWN_9801"/> + + <enum name="a6xx_tess_spacing"> + <value value="0x0" name="TESS_EQUAL"/> + <value value="0x2" name="TESS_FRACTIONAL_ODD"/> + <value value="0x3" name="TESS_FRACTIONAL_EVEN"/> + </enum> + + <reg32 offset="0x9802" name="PC_TESS_CNTL"> + <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> + <bitfield name="CCW" pos="2" type="boolean"/> + <bitfield name="PRIMITIVES" pos="3" type="boolean"/> + </reg32> + + <!-- probably: --> + <reg32 offset="0x9803" name="PC_RESTART_INDEX"/> + <reg32 offset="0x9804" name="PC_MODE_CNTL"/> + + <!-- always 0x1 ? --> + <reg32 offset="0x9805" name="PC_UNKNOWN_9805"/> + <reg32 offset="0x9806" name="PC_UNKNOWN_9806"/> + + <reg32 offset="0x9980" name="PC_UNKNOWN_9980"/> + <reg32 offset="0x9981" name="PC_UNKNOWN_9981"/> + + <reg32 offset="0x9990" name="PC_UNKNOWN_9990"/> + + <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0"> + <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> + <!-- maybe? b1 seems always set, so just assume it is for now: --> + <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> + </reg32> + <reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1"> + <doc> + vertex shader + + num of varyings plus four for gl_Position (plus one if gl_PointSize) + plus # of transform-feedback (streamout) varyings if using the + hw streamout (rather than stg instructions in shader) + </doc> + <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/> + <bitfield name="PSIZE" pos="8" type="boolean"/> + </reg32> + + <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3"> + <doc> + hull shader? + + num of varyings plus four for gl_Position (plus one if gl_PointSize) + plus # of transform-feedback (streamout) varyings if using the + hw streamout (rather than stg instructions in shader) + </doc> + <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/> + <bitfield name="PSIZE" pos="8" type="boolean"/> + </reg32> + <reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4"> + <doc> + domain shader + num of varyings plus four for gl_Position (plus one if gl_PointSize) + plus # of transform-feedback (streamout) varyings if using the + hw streamout (rather than stg instructions in shader) + </doc> + <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/> + <bitfield name="PSIZE" pos="8" type="boolean"/> + </reg32> + + <!-- always 0x0 ? --> + <reg32 offset="0x9b06" name="PC_UNKNOWN_9B06"/> + <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/> + + <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/> + <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/> + + <!-- always 0x0 --> + <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/> + + <reg32 offset="0xa000" name="VFD_CONTROL_0"> + <bitfield name="VTXCNT" low="0" high="5" type="uint"/> + </reg32> + <reg32 offset="0xa001" name="VFD_CONTROL_1"> + <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/> + <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/> + <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xa002" name="VFD_CONTROL_2"> + <bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xa003" name="VFD_CONTROL_3"> + <bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/> + <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> + <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xa004" name="VFD_CONTROL_4"> + </reg32> + <reg32 offset="0xa005" name="VFD_CONTROL_5"> + </reg32> + <reg32 offset="0xa006" name="VFD_CONTROL_6"> + </reg32> + + <reg32 offset="0xa007" name="VFD_MODE_CNTL"> + <bitfield name="BINNING_PASS" pos="0" type="boolean"/> + </reg32> + + <!-- always 0x0 ? --> + <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/> + <reg32 offset="0xa009" name="VFD_UNKNOWN_A009"/> + + <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/> + <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/> + <array offset="0xa010" name="VFD_FETCH" stride="4" length="32"> + <reg32 offset="0x0" name="BASE_LO"/> + <reg32 offset="0x1" name="BASE_HI"/> + <reg32 offset="0x2" name="SIZE" type="uint"/> + <reg32 offset="0x3" name="STRIDE" type="uint"/> + </array> + <array offset="0xa090" name="VFD_DECODE" stride="2" length="32"> + <reg32 offset="0x0" name="INSTR"> + <!-- IDX appears to index into VFD_FETCH[] --> + <bitfield name="IDX" low="0" high="4" type="uint"/> + <bitfield name="INSTANCED" pos="17" type="boolean"/> + <bitfield name="FORMAT" low="20" high="27" type="a6xx_vtx_fmt"/> + <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/> + <bitfield name="UNK30" pos="30" type="boolean"/> + <bitfield name="FLOAT" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x1" name="STEP_RATE"/> + </array> + <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32"> + <reg32 offset="0x0" name="INSTR"> + <bitfield name="WRITEMASK" low="0" high="3" type="hex"/> + <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/> + </reg32> + </array> + + <!-- always 0x1 ? --> + <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/> + + <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL"> + <!-- # of VS outputs including pos/psize --> + <bitfield name="VSOUT" low="0" high="4" type="uint"/> + </reg32> + <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16"> + <reg32 offset="0x0" name="REG"> + <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> + <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> + <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> + </reg32> + </array> + <!-- + Starting with a5xx, position/psize outputs from shader end up in the + SP_VS_OUT map, with highest OUTLOCn position. (Generally they are + the last entries too, except when gl_PointCoord is used, blob inserts + an extra varying after, but with a lower OUTLOC position. If present, + psize is last, preceded by position. + --> + <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> + <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> + <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> + <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> + </reg32> + </array> + + <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes"> + <!-- + When b31 set we just see FULLREGFOOTPRINT set. The pattern of + used registers is a bit odd too: + - used (half): 0-15 68-179 (cnt=128, max=179) + - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127> + whereas we usually see a (mostly) contiguous range of regs used. But if + I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)), + then: + - used (merged): 0-191 (cnt=192, max=191) + So I think if b31 is set, then the half precision registers overlap + the full precision registers. (Which seems like a pretty sensible + feature, actually I'm not sure when you *wouldn't* want to use that, + since it gives register allocation more flexibility) + --> + <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/> + <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/> + <!-- seems to be nesting level for flow control:.. --> + <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/> + <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/> + <bitfield name="VARYING" pos="22" type="boolean"/> + <bitfield name="PIXLODENABLE" pos="26" type="boolean"/> + <bitfield name="MERGEDREGS" pos="31" type="boolean"/> + </bitset> + + <bitset name="a6xx_sp_xs_config" inline="yes"> + <bitfield name="ENABLED" pos="8" type="boolean"/> + <!-- + number of textures and samplers.. these might be swapped, with GL I + always see the same value for both. + --> + <bitfield name="NTEX" low="9" high="16" type="uint"/> + <bitfield name="NSAMP" low="17" high="21" type="uint"/> + <bitfield name="NIBO" low="22" high="29" type="uint"/> + </bitset> + + <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/> + <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/> + <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/> + <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/> + <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/> + <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/> + + <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/> + <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/> + <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/> + <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/> + <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/> + <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/> + <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/> + + <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL"> + <!-- # of DS outputs including pos/psize --> + <bitfield name="DSOUT" low="0" high="4" type="uint"/> + </reg32> + <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16"> + <reg32 offset="0x0" name="REG"> + <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> + <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> + <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> + </reg32> + </array> + <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> + <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> + <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> + <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> + </reg32> + </array> + + <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/> + <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/> + <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/> + <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/> + <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/> + <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/> + + <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/> + <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/> + <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/> + <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/> + <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/> + <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/> + + <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/> + <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/> + <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/> + <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/> + <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/> + <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/> + <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/> + <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/> + <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/> + <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/> + <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/> + <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/> + <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/> + <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/> + <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/> + <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/> + + <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/> + <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/> + <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/> + + <reg32 offset="0xa989" name="SP_BLEND_CNTL"> + <bitfield name="ENABLED" pos="0" type="boolean"/> + <bitfield name="UNK8" pos="8" type="boolean"/> + <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> + </reg32> + <reg32 offset="0xa98a" name="SP_SRGB_CNTL"> + <!-- Same as RB_SRGB_CNTL --> + <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> + <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> + <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> + <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> + <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> + <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> + <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> + <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> + </reg32> + <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS"> + <bitfield name="RT0" low="0" high="3"/> + <bitfield name="RT1" low="4" high="7"/> + <bitfield name="RT2" low="8" high="11"/> + <bitfield name="RT3" low="12" high="15"/> + <bitfield name="RT4" low="16" high="19"/> + <bitfield name="RT5" low="20" high="23"/> + <bitfield name="RT6" low="24" high="27"/> + <bitfield name="RT7" low="28" high="31"/> + </reg32> + <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0"> + <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> + <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1"> + <bitfield name="MRT" low="0" high="3" type="uint"/> + </reg32> + + <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8"> + <reg32 offset="0" name="REG"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/> + <bitfield name="COLOR_SINT" pos="8" type="boolean"/> + <bitfield name="COLOR_UINT" pos="9" type="boolean"/> + </reg32> + </array> + + <reg32 offset="0xa99e" name="SP_UNKNOWN_A99E"/> + + <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/> + + <!-- always 0x0 ? --> + <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/> + + <!-- set for compute shaders, always 0x41 --> + <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/> + + <!-- set for compute shaders, always 0x0 --> + <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/> + + <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/> + + <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/> + <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/> + <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/> + <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/> + <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/> + <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/> + <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/> + <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/> + + <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8"> + <doc>per MRT</doc> + <reg32 offset="0x0" name="REG"> + <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="HALF_PRECISION" pos="8" type="boolean"/> + </reg32> + </array> + + <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> + <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/> + <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/> + <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/> + <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/> + + <!-- + IBO state for compute shader: + --> + <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/> + <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/> + <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/> + + <!-- always 0x5 ? --> + <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/> + + <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/> + <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/> + + <!-- + Combined IBO state for 3d pipe, used for Image and SSBO write/atomic + instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders. + --> + <reg32 offset="0xab1a" name="SP_IBO_LO"/> + <reg32 offset="0xab1b" name="SP_IBO_HI"/> + <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/> + + <!-- + I believe this describes the src format, but haven't seen traces with + src_format != dst_format + --> + <reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT"> + <bitfield name="NORM" pos="0" type="boolean"/> + <bitfield name="SINT" pos="1" type="boolean"/> + <bitfield name="UINT" pos="2" type="boolean"/> + <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_color_fmt"/> + </reg32> + + <!-- always 0x0 --> + <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/> + + <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/> + <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/> + + <!-- always 0x3f ? --> + <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/> + + <!-- always 0x0 ? --> + <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/> + <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/> + + <!-- could be all the stuff below here is actually TPL1?? --> + + <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + </reg32> + <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL"> + <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> + <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> + </reg32> + + <!-- looks to work in the same way as a5xx: --> + <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/> + <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/> + <!-- always 0x0 ? --> + <reg32 offset="0xb304" name="SP_TP_UNKNOWN_B304"/> + + <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/> + + <!-- + Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either + badly named or the functionality moved in a6xx. But downstream kernel + calls this "a6xx_sp_ps_tp_2d_cluster" + --> + <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/> + <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> + <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled --> + <bitfield name="FLAGS" pos="12" type="boolean"/> + <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> + <bitfield name="FILTER" pos="16" type="boolean"/> + </reg32> + <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE"> + <bitfield name="WIDTH" low="0" high="14" type="uint"/> + <bitfield name="HEIGHT" low="15" high="29" type="uint"/> + </reg32> + <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/> + <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/> + <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH"> + <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/> + </reg32> + + <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/> + <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/> + <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH"> + <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> + <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> + </reg32> + + <!-- always 0x00100000 ? --> + <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/> + + <!-- always 0x44 ? --> + <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/> + + <bitset name="a6xx_hlsq_xs_cntl" inline="yes"> + <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/> + <bitfield name="ENABLED" pos="8" type="boolean"/> + </bitset> + + <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/> + <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/> + <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/> + <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/> + + <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/> + + <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG"> + <!-- always 0x7 ? --> + </reg32> + <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG"> + <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> + <!-- SAMPLEID is loaded into a half-precision register: --> + <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> + <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> + <!-- + SIZE is the "size" of the primitive, ie. what the i/j coords need + to be divided by to scale to a single fragment. It is probably + the longer of the two lines that form the tri (ie v0v1 and v0v2)? + --> + <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG"> + <!-- register loaded with position (bary.f) --> + <bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/> + <bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG"> + <bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/> + <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/> + <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG"> + <!-- unknown regid in low 8b --> + </reg32> + <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/> + + <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0"> + <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> + <!-- localsize is value minus one: --> + <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> + <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> + <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> + </reg32> + <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1"> + <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2"> + <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3"> + <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4"> + <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5"> + <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6"> + <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0"> + <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/> + <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/> + <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> + </reg32> + <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc --> + <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/> + <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/> + <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/> + + <!-- probably: --> + <reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/> + + <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/> + + <!-- always 0x0 ? --> + <reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/> + + <!-- always 0x80 ? --> + <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/> + <!-- always 0x0 ? --> + <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/> + <!-- always 0x0 ? --> + <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/> + +</domain> + +<!-- Seems basically the same as a5xx, maybe move to common.xml.. --> +<domain name="A6XX_TEX_SAMP" width="32"> + <doc>Texture sampler dwords</doc> + <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> + <value name="A6XX_TEX_NEAREST" value="0"/> + <value name="A6XX_TEX_LINEAR" value="1"/> + <value name="A6XX_TEX_ANISO" value="2"/> + </enum> + <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> + <value name="A6XX_TEX_REPEAT" value="0"/> + <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> + <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> + <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> + <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> + </enum> + <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> + <value name="A6XX_TEX_ANISO_1" value="0"/> + <value name="A6XX_TEX_ANISO_2" value="1"/> + <value name="A6XX_TEX_ANISO_4" value="2"/> + <value name="A6XX_TEX_ANISO_8" value="3"/> + <value name="A6XX_TEX_ANISO_16" value="4"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> + <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/> + <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/> + <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/> + <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/> + <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/> + <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/> + <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real --> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/> + <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/> + <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/> + <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/> + <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/> + <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="BCOLOR_OFFSET" low="0" high="31"/> + </reg32> + <reg32 offset="3" name="3"/> +</domain> + +<domain name="A6XX_TEX_CONST" width="32"> + <doc>Texture constant dwords</doc> + <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> + <value name="A6XX_TEX_X" value="0"/> + <value name="A6XX_TEX_Y" value="1"/> + <value name="A6XX_TEX_Z" value="2"/> + <value name="A6XX_TEX_W" value="3"/> + <value name="A6XX_TEX_ZERO" value="4"/> + <value name="A6XX_TEX_ONE" value="5"/> + </enum> + <enum name="a6xx_tex_type"> <!-- same as a4xx? --> + <value name="A6XX_TEX_1D" value="0"/> + <value name="A6XX_TEX_2D" value="1"/> + <value name="A6XX_TEX_CUBE" value="2"/> + <value name="A6XX_TEX_3D" value="3"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> + <bitfield name="SRGB" pos="2" type="boolean"/> + <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/> + <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/> + <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/> + <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/> + <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> + <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/> + <bitfield name="FMT" low="22" high="29" type="a6xx_tex_fmt"/> + <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="WIDTH" low="0" high="14" type="uint"/> + <bitfield name="HEIGHT" low="15" high="29" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <!-- + b4 and b31 set for buffer/ssbo case, in which case low 15 bits + of size encoded in WIDTH, and high 15 bits encoded in HEIGHT + + b31 is probably the 'BUFFER' bit.. it is the one that changes + behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071 + --> + <bitfield name="UNK4" pos="4" type="boolean"/> + <bitfield name="FETCHSIZE" low="0" high="3" type="a6xx_tex_fetchsize"/> + <doc>Pitch in bytes (so actually stride)</doc> + <bitfield name="PITCH" low="7" high="28" type="uint"/> + <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/> + <bitfield name="UNK31" pos="31" type="boolean"/> + </reg32> + <reg32 offset="3" name="3"> + <!-- + ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and + for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the + layer size at the point that it stops being reduced moving to + higher (smaller) mipmap levels + --> + <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/> + <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/> + <bitfield name="UNK27" pos="27" type="boolean"/> + <bitfield name="FLAG" pos="28" type="boolean"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="BASE_LO" low="5" high="31" shr="5"/> + </reg32> + <reg32 offset="5" name="5"> + <bitfield name="BASE_HI" low="0" high="16"/> + <bitfield name="DEPTH" low="17" high="29" type="uint"/> + </reg32> + <reg32 offset="6" name="6"/> + <reg32 offset="7" name="7"> + <bitfield name="FLAG_LO" low="5" high="31" shr="5"/> + </reg32> + <reg32 offset="8" name="8"> + <bitfield name="FLAG_HI" low="0" high="16"/> + </reg32> + <reg32 offset="9" name="9"> + <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> + </reg32> + <reg32 offset="10" name="10"> + <!-- + I see some other bits set by blob above FLAG_BUFFER_PITCH, but they + don't seem to be particularly sensible... or needed for UBWC to work + --> + <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> + </reg32> + <reg32 offset="11" name="11"/> + <reg32 offset="12" name="12"/> + <reg32 offset="13" name="13"/> + <reg32 offset="14" name="14"/> + <reg32 offset="15" name="15"/> +</domain> + +<!-- +Note the "SSBO" state blocks are actually used for both images and SSBOs, +naming is just because I r/e'd SSBOs first. I should probably come up +with a better name. +--> +<domain name="A6XX_IBO" width="32"> + <reg32 offset="0" name="0"> + <!-- + NOTE: same position as in TEX_CONST state.. I don't see other bits + used but if they are good chance position is same as TEX_CONST + --> + <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> + <bitfield name="FMT" low="22" high="29" type="a6xx_tex_fmt"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="WIDTH" low="0" high="14" type="uint"/> + <bitfield name="HEIGHT" low="15" high="29" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <!-- + b4 and b31 set for buffer/ssbo case, in which case low 15 bits + of size encoded in WIDTH, and high 15 bits encoded in HEIGHT + --> + <bitfield name="UNK4" pos="4" type="boolean"/> + <doc>Pitch in bytes (so actually stride)</doc> + <bitfield name="PITCH" low="7" high="28" type="uint"/> + <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/> + <bitfield name="UNK31" pos="31" type="boolean"/> + </reg32> + <reg32 offset="3" name="3"> + <!-- + ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and + for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the + layer size at the point that it stops being reduced moving to + higher (smaller) mipmap levels + --> + <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/> + <bitfield name="UNK27" pos="27" type="boolean"/> + <bitfield name="FLAG" pos="28" type="boolean"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="BASE_LO" low="0" high="31"/> + </reg32> + <reg32 offset="5" name="5"> + <bitfield name="BASE_HI" low="0" high="16"/> + <bitfield name="DEPTH" low="17" high="29" type="uint"/> + </reg32> + <reg32 offset="6" name="6"> + </reg32> + <reg32 offset="7" name="7"> + </reg32> + <reg32 offset="8" name="8"> + </reg32> + <reg32 offset="9" name="9"> + <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> + </reg32> + <reg32 offset="10" name="10"> + <!-- + I see some other bits set by blob above FLAG_BUFFER_PITCH, but they + don't seem to be particularly sensible... or needed for UBWC to work + --> + <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> + </reg32> +</domain> + +<domain name="A6XX_UBO" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="BASE_LO" low="0" high="31"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="BASE_HI" low="0" high="16"/> + <!-- size probably in high bits --> + </reg32> +</domain> + +<domain name="CP_UNK_A6XX_55" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="BASE_LO" low="0" high="31"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="BASE_HI" low="0" high="16"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="SIZE" low="0" high="15"/> + </reg32> +</domain> + +<domain name="A6XX_PDC" width="32"> + <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/> + <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/> + <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/> + <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/> + <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/> + <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/> + <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/> + <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/> + <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/> + <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/> + <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/> + <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/> + <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/> + <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/> + <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/> + <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/> + <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/> + <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/> + <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/> + <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/> + <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/> + <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/> + <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/> + <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/> + <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/> + <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/> +</domain> + +<domain name="A6XX_PDC_GPU_SEQ" width="32"> + <reg32 offset="0x0" name="MEM_0"/> +</domain> + +<domain name="A6XX_CX_DBGC" width="32"> + <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A"> + <bitfield high="7" low="0" name="PING_INDEX"/> + <bitfield high="15" low="8" name="PING_BLK_SEL"/> + </reg32> + <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/> + <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/> + <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/> + <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT"> + <bitfield high="5" low="0" name="TRACEEN"/> + <bitfield high="14" low="12" name="GRANU"/> + <bitfield high="31" low="28" name="SEGT"/> + </reg32> + <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM"> + <bitfield high="27" low="24" name="ENABLE"/> + </reg32> + <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/> + <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/> + <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/> + <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/> + <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/> + <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/> + <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/> + <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/> + <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0"> + <bitfield high="3" low="0" name="BYTEL0"/> + <bitfield high="7" low="4" name="BYTEL1"/> + <bitfield high="11" low="8" name="BYTEL2"/> + <bitfield high="15" low="12" name="BYTEL3"/> + <bitfield high="19" low="16" name="BYTEL4"/> + <bitfield high="23" low="20" name="BYTEL5"/> + <bitfield high="27" low="24" name="BYTEL6"/> + <bitfield high="31" low="28" name="BYTEL7"/> + </reg32> + <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1"> + <bitfield high="3" low="0" name="BYTEL8"/> + <bitfield high="7" low="4" name="BYTEL9"/> + <bitfield high="11" low="8" name="BYTEL10"/> + <bitfield high="15" low="12" name="BYTEL11"/> + <bitfield high="19" low="16" name="BYTEL12"/> + <bitfield high="23" low="20" name="BYTEL13"/> + <bitfield high="27" low="24" name="BYTEL14"/> + <bitfield high="31" low="28" name="BYTEL15"/> + </reg32> + + <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/> + <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> +</domain> + +<domain name="A6XX_CX_MISC" width="32"> + <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/> + <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/> +</domain> + +</database> diff --git a/src/freedreno/registers/a6xx.xml.h b/src/freedreno/registers/a6xx.xml.h deleted file mode 100644 index 43fcd2ba8ae..00000000000 --- a/src/freedreno/registers/a6xx.xml.h +++ /dev/null @@ -1,5994 +0,0 @@ -#ifndef A6XX_XML -#define A6XX_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2019 by the following authors: -- Rob Clark <[email protected]> (robclark) -- Ilia Mirkin <[email protected]> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum a6xx_color_fmt { - RB6_A8_UNORM = 2, - RB6_R8_UNORM = 3, - RB6_R8_SNORM = 4, - RB6_R8_UINT = 5, - RB6_R8_SINT = 6, - RB6_R4G4B4A4_UNORM = 8, - RB6_R5G5B5A1_UNORM = 10, - RB6_R5G6B5_UNORM = 14, - RB6_R8G8_UNORM = 15, - RB6_R8G8_SNORM = 16, - RB6_R8G8_UINT = 17, - RB6_R8G8_SINT = 18, - RB6_R16_UNORM = 21, - RB6_R16_SNORM = 22, - RB6_R16_FLOAT = 23, - RB6_R16_UINT = 24, - RB6_R16_SINT = 25, - RB6_R8G8B8A8_UNORM = 48, - RB6_R8G8B8_UNORM = 49, - RB6_R8G8B8A8_SNORM = 50, - RB6_R8G8B8A8_UINT = 51, - RB6_R8G8B8A8_SINT = 52, - RB6_R10G10B10A2_UNORM = 55, - RB6_R10G10B10A2_UINT = 58, - RB6_R11G11B10_FLOAT = 66, - RB6_R16G16_UNORM = 67, - RB6_R16G16_SNORM = 68, - RB6_R16G16_FLOAT = 69, - RB6_R16G16_UINT = 70, - RB6_R16G16_SINT = 71, - RB6_R32_FLOAT = 74, - RB6_R32_UINT = 75, - RB6_R32_SINT = 76, - RB6_R16G16B16A16_UNORM = 96, - RB6_R16G16B16A16_SNORM = 97, - RB6_R16G16B16A16_FLOAT = 98, - RB6_R16G16B16A16_UINT = 99, - RB6_R16G16B16A16_SINT = 100, - RB6_R32G32_FLOAT = 103, - RB6_R32G32_UINT = 104, - RB6_R32G32_SINT = 105, - RB6_R32G32B32A32_FLOAT = 130, - RB6_R32G32B32A32_UINT = 131, - RB6_R32G32B32A32_SINT = 132, - RB6_Z24_UNORM_S8_UINT = 145, - RB6_X8Z24_UNORM = 160, -}; - -enum a6xx_tile_mode { - TILE6_LINEAR = 0, - TILE6_2 = 2, - TILE6_3 = 3, -}; - -enum a6xx_vtx_fmt { - VFMT6_8_UNORM = 3, - VFMT6_8_SNORM = 4, - VFMT6_8_UINT = 5, - VFMT6_8_SINT = 6, - VFMT6_8_8_UNORM = 15, - VFMT6_8_8_SNORM = 16, - VFMT6_8_8_UINT = 17, - VFMT6_8_8_SINT = 18, - VFMT6_16_UNORM = 21, - VFMT6_16_SNORM = 22, - VFMT6_16_FLOAT = 23, - VFMT6_16_UINT = 24, - VFMT6_16_SINT = 25, - VFMT6_8_8_8_UNORM = 33, - VFMT6_8_8_8_SNORM = 34, - VFMT6_8_8_8_UINT = 35, - VFMT6_8_8_8_SINT = 36, - VFMT6_8_8_8_8_UNORM = 48, - VFMT6_8_8_8_8_SNORM = 50, - VFMT6_8_8_8_8_UINT = 51, - VFMT6_8_8_8_8_SINT = 52, - VFMT6_10_10_10_2_UNORM = 54, - VFMT6_10_10_10_2_SNORM = 57, - VFMT6_10_10_10_2_UINT = 58, - VFMT6_10_10_10_2_SINT = 59, - VFMT6_11_11_10_FLOAT = 66, - VFMT6_16_16_UNORM = 67, - VFMT6_16_16_SNORM = 68, - VFMT6_16_16_FLOAT = 69, - VFMT6_16_16_UINT = 70, - VFMT6_16_16_SINT = 71, - VFMT6_32_UNORM = 72, - VFMT6_32_SNORM = 73, - VFMT6_32_FLOAT = 74, - VFMT6_32_UINT = 75, - VFMT6_32_SINT = 76, - VFMT6_32_FIXED = 77, - VFMT6_16_16_16_UNORM = 88, - VFMT6_16_16_16_SNORM = 89, - VFMT6_16_16_16_FLOAT = 90, - VFMT6_16_16_16_UINT = 91, - VFMT6_16_16_16_SINT = 92, - VFMT6_16_16_16_16_UNORM = 96, - VFMT6_16_16_16_16_SNORM = 97, - VFMT6_16_16_16_16_FLOAT = 98, - VFMT6_16_16_16_16_UINT = 99, - VFMT6_16_16_16_16_SINT = 100, - VFMT6_32_32_UNORM = 101, - VFMT6_32_32_SNORM = 102, - VFMT6_32_32_FLOAT = 103, - VFMT6_32_32_UINT = 104, - VFMT6_32_32_SINT = 105, - VFMT6_32_32_FIXED = 106, - VFMT6_32_32_32_UNORM = 112, - VFMT6_32_32_32_SNORM = 113, - VFMT6_32_32_32_UINT = 114, - VFMT6_32_32_32_SINT = 115, - VFMT6_32_32_32_FLOAT = 116, - VFMT6_32_32_32_FIXED = 117, - VFMT6_32_32_32_32_UNORM = 128, - VFMT6_32_32_32_32_SNORM = 129, - VFMT6_32_32_32_32_FLOAT = 130, - VFMT6_32_32_32_32_UINT = 131, - VFMT6_32_32_32_32_SINT = 132, - VFMT6_32_32_32_32_FIXED = 133, -}; - -enum a6xx_tex_fmt { - TFMT6_A8_UNORM = 2, - TFMT6_8_UNORM = 3, - TFMT6_8_SNORM = 4, - TFMT6_8_UINT = 5, - TFMT6_8_SINT = 6, - TFMT6_4_4_4_4_UNORM = 8, - TFMT6_5_5_5_1_UNORM = 10, - TFMT6_5_6_5_UNORM = 14, - TFMT6_8_8_UNORM = 15, - TFMT6_8_8_SNORM = 16, - TFMT6_8_8_UINT = 17, - TFMT6_8_8_SINT = 18, - TFMT6_L8_A8_UNORM = 19, - TFMT6_16_UNORM = 21, - TFMT6_16_SNORM = 22, - TFMT6_16_FLOAT = 23, - TFMT6_16_UINT = 24, - TFMT6_16_SINT = 25, - TFMT6_8_8_8_8_UNORM = 48, - TFMT6_8_8_8_UNORM = 49, - TFMT6_8_8_8_8_SNORM = 50, - TFMT6_8_8_8_8_UINT = 51, - TFMT6_8_8_8_8_SINT = 52, - TFMT6_9_9_9_E5_FLOAT = 53, - TFMT6_10_10_10_2_UNORM = 54, - TFMT6_10_10_10_2_UINT = 58, - TFMT6_11_11_10_FLOAT = 66, - TFMT6_16_16_UNORM = 67, - TFMT6_16_16_SNORM = 68, - TFMT6_16_16_FLOAT = 69, - TFMT6_16_16_UINT = 70, - TFMT6_16_16_SINT = 71, - TFMT6_32_FLOAT = 74, - TFMT6_32_UINT = 75, - TFMT6_32_SINT = 76, - TFMT6_16_16_16_16_UNORM = 96, - TFMT6_16_16_16_16_SNORM = 97, - TFMT6_16_16_16_16_FLOAT = 98, - TFMT6_16_16_16_16_UINT = 99, - TFMT6_16_16_16_16_SINT = 100, - TFMT6_32_32_FLOAT = 103, - TFMT6_32_32_UINT = 104, - TFMT6_32_32_SINT = 105, - TFMT6_32_32_32_UINT = 114, - TFMT6_32_32_32_SINT = 115, - TFMT6_32_32_32_FLOAT = 116, - TFMT6_32_32_32_32_FLOAT = 130, - TFMT6_32_32_32_32_UINT = 131, - TFMT6_32_32_32_32_SINT = 132, - TFMT6_Z24_UNORM_S8_UINT = 145, - TFMT6_X8Z24_UNORM = 160, - TFMT6_ETC2_RG11_UNORM = 171, - TFMT6_ETC2_RG11_SNORM = 172, - TFMT6_ETC2_R11_UNORM = 173, - TFMT6_ETC2_R11_SNORM = 174, - TFMT6_ETC1 = 175, - TFMT6_ETC2_RGB8 = 176, - TFMT6_ETC2_RGBA8 = 177, - TFMT6_ETC2_RGB8A1 = 178, - TFMT6_DXT1 = 179, - TFMT6_DXT3 = 180, - TFMT6_DXT5 = 181, - TFMT6_RGTC1_UNORM = 183, - TFMT6_RGTC1_SNORM = 184, - TFMT6_RGTC2_UNORM = 187, - TFMT6_RGTC2_SNORM = 188, - TFMT6_BPTC_UFLOAT = 190, - TFMT6_BPTC_FLOAT = 191, - TFMT6_BPTC = 192, - TFMT6_ASTC_4x4 = 193, - TFMT6_ASTC_5x4 = 194, - TFMT6_ASTC_5x5 = 195, - TFMT6_ASTC_6x5 = 196, - TFMT6_ASTC_6x6 = 197, - TFMT6_ASTC_8x5 = 198, - TFMT6_ASTC_8x6 = 199, - TFMT6_ASTC_8x8 = 200, - TFMT6_ASTC_10x5 = 201, - TFMT6_ASTC_10x6 = 202, - TFMT6_ASTC_10x8 = 203, - TFMT6_ASTC_10x10 = 204, - TFMT6_ASTC_12x10 = 205, - TFMT6_ASTC_12x12 = 206, -}; - -enum a6xx_tex_fetchsize { - TFETCH6_1_BYTE = 0, - TFETCH6_2_BYTE = 1, - TFETCH6_4_BYTE = 2, - TFETCH6_8_BYTE = 3, - TFETCH6_16_BYTE = 4, -}; - -enum a6xx_depth_format { - DEPTH6_NONE = 0, - DEPTH6_16 = 1, - DEPTH6_24_8 = 2, - DEPTH6_32 = 4, -}; - -enum a6xx_shader_id { - A6XX_TP0_TMO_DATA = 9, - A6XX_TP0_SMO_DATA = 10, - A6XX_TP0_MIPMAP_BASE_DATA = 11, - A6XX_TP1_TMO_DATA = 25, - A6XX_TP1_SMO_DATA = 26, - A6XX_TP1_MIPMAP_BASE_DATA = 27, - A6XX_SP_INST_DATA = 41, - A6XX_SP_LB_0_DATA = 42, - A6XX_SP_LB_1_DATA = 43, - A6XX_SP_LB_2_DATA = 44, - A6XX_SP_LB_3_DATA = 45, - A6XX_SP_LB_4_DATA = 46, - A6XX_SP_LB_5_DATA = 47, - A6XX_SP_CB_BINDLESS_DATA = 48, - A6XX_SP_CB_LEGACY_DATA = 49, - A6XX_SP_UAV_DATA = 50, - A6XX_SP_INST_TAG = 51, - A6XX_SP_CB_BINDLESS_TAG = 52, - A6XX_SP_TMO_UMO_TAG = 53, - A6XX_SP_SMO_TAG = 54, - A6XX_SP_STATE_DATA = 55, - A6XX_HLSQ_CHUNK_CVS_RAM = 73, - A6XX_HLSQ_CHUNK_CPS_RAM = 74, - A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, - A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, - A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, - A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, - A6XX_HLSQ_CVS_MISC_RAM = 80, - A6XX_HLSQ_CPS_MISC_RAM = 81, - A6XX_HLSQ_INST_RAM = 82, - A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, - A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, - A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, - A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, - A6XX_HLSQ_INST_RAM_TAG = 87, - A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, - A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, - A6XX_HLSQ_PWR_REST_RAM = 90, - A6XX_HLSQ_PWR_REST_TAG = 91, - A6XX_HLSQ_DATAPATH_META = 96, - A6XX_HLSQ_FRONTEND_META = 97, - A6XX_HLSQ_INDIRECT_META = 98, - A6XX_HLSQ_BACKEND_META = 99, -}; - -enum a6xx_debugbus_id { - A6XX_DBGBUS_CP = 1, - A6XX_DBGBUS_RBBM = 2, - A6XX_DBGBUS_VBIF = 3, - A6XX_DBGBUS_HLSQ = 4, - A6XX_DBGBUS_UCHE = 5, - A6XX_DBGBUS_DPM = 6, - A6XX_DBGBUS_TESS = 7, - A6XX_DBGBUS_PC = 8, - A6XX_DBGBUS_VFDP = 9, - A6XX_DBGBUS_VPC = 10, - A6XX_DBGBUS_TSE = 11, - A6XX_DBGBUS_RAS = 12, - A6XX_DBGBUS_VSC = 13, - A6XX_DBGBUS_COM = 14, - A6XX_DBGBUS_LRZ = 16, - A6XX_DBGBUS_A2D = 17, - A6XX_DBGBUS_CCUFCHE = 18, - A6XX_DBGBUS_GMU_CX = 19, - A6XX_DBGBUS_RBP = 20, - A6XX_DBGBUS_DCS = 21, - A6XX_DBGBUS_DBGC = 22, - A6XX_DBGBUS_CX = 23, - A6XX_DBGBUS_GMU_GX = 24, - A6XX_DBGBUS_TPFCHE = 25, - A6XX_DBGBUS_GBIF_GX = 26, - A6XX_DBGBUS_GPC = 29, - A6XX_DBGBUS_LARC = 30, - A6XX_DBGBUS_HLSQ_SPTP = 31, - A6XX_DBGBUS_RB_0 = 32, - A6XX_DBGBUS_RB_1 = 33, - A6XX_DBGBUS_UCHE_WRAPPER = 36, - A6XX_DBGBUS_CCU_0 = 40, - A6XX_DBGBUS_CCU_1 = 41, - A6XX_DBGBUS_VFD_0 = 56, - A6XX_DBGBUS_VFD_1 = 57, - A6XX_DBGBUS_VFD_2 = 58, - A6XX_DBGBUS_VFD_3 = 59, - A6XX_DBGBUS_SP_0 = 64, - A6XX_DBGBUS_SP_1 = 65, - A6XX_DBGBUS_TPL1_0 = 72, - A6XX_DBGBUS_TPL1_1 = 73, - A6XX_DBGBUS_TPL1_2 = 74, - A6XX_DBGBUS_TPL1_3 = 75, -}; - -enum a6xx_cp_perfcounter_select { - PERF_CP_ALWAYS_COUNT = 0, - PERF_CP_BUSY_GFX_CORE_IDLE = 1, - PERF_CP_BUSY_CYCLES = 2, - PERF_CP_NUM_PREEMPTIONS = 3, - PERF_CP_PREEMPTION_REACTION_DELAY = 4, - PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, - PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, - PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, - PERF_CP_PREDICATED_DRAWS_KILLED = 8, - PERF_CP_MODE_SWITCH = 9, - PERF_CP_ZPASS_DONE = 10, - PERF_CP_CONTEXT_DONE = 11, - PERF_CP_CACHE_FLUSH = 12, - PERF_CP_LONG_PREEMPTIONS = 13, - PERF_CP_SQE_I_CACHE_STARVE = 14, - PERF_CP_SQE_IDLE = 15, - PERF_CP_SQE_PM4_STARVE_RB_IB = 16, - PERF_CP_SQE_PM4_STARVE_SDS = 17, - PERF_CP_SQE_MRB_STARVE = 18, - PERF_CP_SQE_RRB_STARVE = 19, - PERF_CP_SQE_VSD_STARVE = 20, - PERF_CP_VSD_DECODE_STARVE = 21, - PERF_CP_SQE_PIPE_OUT_STALL = 22, - PERF_CP_SQE_SYNC_STALL = 23, - PERF_CP_SQE_PM4_WFI_STALL = 24, - PERF_CP_SQE_SYS_WFI_STALL = 25, - PERF_CP_SQE_T4_EXEC = 26, - PERF_CP_SQE_LOAD_STATE_EXEC = 27, - PERF_CP_SQE_SAVE_SDS_STATE = 28, - PERF_CP_SQE_DRAW_EXEC = 29, - PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, - PERF_CP_SQE_EXEC_PROFILED = 31, - PERF_CP_MEMORY_POOL_EMPTY = 32, - PERF_CP_MEMORY_POOL_SYNC_STALL = 33, - PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, - PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, - PERF_CP_AHB_STALL_SQE_GMU = 36, - PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, - PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, - PERF_CP_CLUSTER0_EMPTY = 39, - PERF_CP_CLUSTER1_EMPTY = 40, - PERF_CP_CLUSTER2_EMPTY = 41, - PERF_CP_CLUSTER3_EMPTY = 42, - PERF_CP_CLUSTER4_EMPTY = 43, - PERF_CP_CLUSTER5_EMPTY = 44, - PERF_CP_PM4_DATA = 45, - PERF_CP_PM4_HEADERS = 46, - PERF_CP_VBIF_READ_BEATS = 47, - PERF_CP_VBIF_WRITE_BEATS = 48, - PERF_CP_SQE_INSTR_COUNTER = 49, -}; - -enum a6xx_rbbm_perfcounter_select { - PERF_RBBM_ALWAYS_COUNT = 0, - PERF_RBBM_ALWAYS_ON = 1, - PERF_RBBM_TSE_BUSY = 2, - PERF_RBBM_RAS_BUSY = 3, - PERF_RBBM_PC_DCALL_BUSY = 4, - PERF_RBBM_PC_VSD_BUSY = 5, - PERF_RBBM_STATUS_MASKED = 6, - PERF_RBBM_COM_BUSY = 7, - PERF_RBBM_DCOM_BUSY = 8, - PERF_RBBM_VBIF_BUSY = 9, - PERF_RBBM_VSC_BUSY = 10, - PERF_RBBM_TESS_BUSY = 11, - PERF_RBBM_UCHE_BUSY = 12, - PERF_RBBM_HLSQ_BUSY = 13, -}; - -enum a6xx_pc_perfcounter_select { - PERF_PC_BUSY_CYCLES = 0, - PERF_PC_WORKING_CYCLES = 1, - PERF_PC_STALL_CYCLES_VFD = 2, - PERF_PC_STALL_CYCLES_TSE = 3, - PERF_PC_STALL_CYCLES_VPC = 4, - PERF_PC_STALL_CYCLES_UCHE = 5, - PERF_PC_STALL_CYCLES_TESS = 6, - PERF_PC_STALL_CYCLES_TSE_ONLY = 7, - PERF_PC_STALL_CYCLES_VPC_ONLY = 8, - PERF_PC_PASS1_TF_STALL_CYCLES = 9, - PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, - PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, - PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, - PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, - PERF_PC_STARVE_CYCLES_DI = 14, - PERF_PC_VIS_STREAMS_LOADED = 15, - PERF_PC_INSTANCES = 16, - PERF_PC_VPC_PRIMITIVES = 17, - PERF_PC_DEAD_PRIM = 18, - PERF_PC_LIVE_PRIM = 19, - PERF_PC_VERTEX_HITS = 20, - PERF_PC_IA_VERTICES = 21, - PERF_PC_IA_PRIMITIVES = 22, - PERF_PC_GS_PRIMITIVES = 23, - PERF_PC_HS_INVOCATIONS = 24, - PERF_PC_DS_INVOCATIONS = 25, - PERF_PC_VS_INVOCATIONS = 26, - PERF_PC_GS_INVOCATIONS = 27, - PERF_PC_DS_PRIMITIVES = 28, - PERF_PC_VPC_POS_DATA_TRANSACTION = 29, - PERF_PC_3D_DRAWCALLS = 30, - PERF_PC_2D_DRAWCALLS = 31, - PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, - PERF_TESS_BUSY_CYCLES = 33, - PERF_TESS_WORKING_CYCLES = 34, - PERF_TESS_STALL_CYCLES_PC = 35, - PERF_TESS_STARVE_CYCLES_PC = 36, - PERF_PC_TSE_TRANSACTION = 37, - PERF_PC_TSE_VERTEX = 38, - PERF_PC_TESS_PC_UV_TRANS = 39, - PERF_PC_TESS_PC_UV_PATCHES = 40, - PERF_PC_TESS_FACTOR_TRANS = 41, -}; - -enum a6xx_vfd_perfcounter_select { - PERF_VFD_BUSY_CYCLES = 0, - PERF_VFD_STALL_CYCLES_UCHE = 1, - PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, - PERF_VFD_STALL_CYCLES_SP_INFO = 3, - PERF_VFD_STALL_CYCLES_SP_ATTR = 4, - PERF_VFD_STARVE_CYCLES_UCHE = 5, - PERF_VFD_RBUFFER_FULL = 6, - PERF_VFD_ATTR_INFO_FIFO_FULL = 7, - PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, - PERF_VFD_NUM_ATTRIBUTES = 9, - PERF_VFD_UPPER_SHADER_FIBERS = 10, - PERF_VFD_LOWER_SHADER_FIBERS = 11, - PERF_VFD_MODE_0_FIBERS = 12, - PERF_VFD_MODE_1_FIBERS = 13, - PERF_VFD_MODE_2_FIBERS = 14, - PERF_VFD_MODE_3_FIBERS = 15, - PERF_VFD_MODE_4_FIBERS = 16, - PERF_VFD_TOTAL_VERTICES = 17, - PERF_VFDP_STALL_CYCLES_VFD = 18, - PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, - PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, - PERF_VFDP_STARVE_CYCLES_PC = 21, - PERF_VFDP_VS_STAGE_WAVES = 22, -}; - -enum a6xx_hlsq_perfcounter_select { - PERF_HLSQ_BUSY_CYCLES = 0, - PERF_HLSQ_STALL_CYCLES_UCHE = 1, - PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, - PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, - PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, - PERF_HLSQ_UCHE_LATENCY_COUNT = 5, - PERF_HLSQ_FS_STAGE_1X_WAVES = 6, - PERF_HLSQ_FS_STAGE_2X_WAVES = 7, - PERF_HLSQ_QUADS = 8, - PERF_HLSQ_CS_INVOCATIONS = 9, - PERF_HLSQ_COMPUTE_DRAWCALLS = 10, - PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, - PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, - PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, - PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, - PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, - PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, - PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, - PERF_HLSQ_STALL_CYCLES_VPC = 18, - PERF_HLSQ_PIXELS = 19, - PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, -}; - -enum a6xx_vpc_perfcounter_select { - PERF_VPC_BUSY_CYCLES = 0, - PERF_VPC_WORKING_CYCLES = 1, - PERF_VPC_STALL_CYCLES_UCHE = 2, - PERF_VPC_STALL_CYCLES_VFD_WACK = 3, - PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, - PERF_VPC_STALL_CYCLES_PC = 5, - PERF_VPC_STALL_CYCLES_SP_LM = 6, - PERF_VPC_STARVE_CYCLES_SP = 7, - PERF_VPC_STARVE_CYCLES_LRZ = 8, - PERF_VPC_PC_PRIMITIVES = 9, - PERF_VPC_SP_COMPONENTS = 10, - PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, - PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, - PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, - PERF_VPC_LM_TRANSACTION = 14, - PERF_VPC_STREAMOUT_TRANSACTION = 15, - PERF_VPC_VS_BUSY_CYCLES = 16, - PERF_VPC_PS_BUSY_CYCLES = 17, - PERF_VPC_VS_WORKING_CYCLES = 18, - PERF_VPC_PS_WORKING_CYCLES = 19, - PERF_VPC_STARVE_CYCLES_RB = 20, - PERF_VPC_NUM_VPCRAM_READ_POS = 21, - PERF_VPC_WIT_FULL_CYCLES = 22, - PERF_VPC_VPCRAM_FULL_CYCLES = 23, - PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, - PERF_VPC_NUM_VPCRAM_WRITE = 25, - PERF_VPC_NUM_VPCRAM_READ_SO = 26, - PERF_VPC_NUM_ATTR_REQ_LM = 27, -}; - -enum a6xx_tse_perfcounter_select { - PERF_TSE_BUSY_CYCLES = 0, - PERF_TSE_CLIPPING_CYCLES = 1, - PERF_TSE_STALL_CYCLES_RAS = 2, - PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, - PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, - PERF_TSE_STARVE_CYCLES_PC = 5, - PERF_TSE_INPUT_PRIM = 6, - PERF_TSE_INPUT_NULL_PRIM = 7, - PERF_TSE_TRIVAL_REJ_PRIM = 8, - PERF_TSE_CLIPPED_PRIM = 9, - PERF_TSE_ZERO_AREA_PRIM = 10, - PERF_TSE_FACENESS_CULLED_PRIM = 11, - PERF_TSE_ZERO_PIXEL_PRIM = 12, - PERF_TSE_OUTPUT_NULL_PRIM = 13, - PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, - PERF_TSE_CINVOCATION = 15, - PERF_TSE_CPRIMITIVES = 16, - PERF_TSE_2D_INPUT_PRIM = 17, - PERF_TSE_2D_ALIVE_CYCLES = 18, - PERF_TSE_CLIP_PLANES = 19, -}; - -enum a6xx_ras_perfcounter_select { - PERF_RAS_BUSY_CYCLES = 0, - PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, - PERF_RAS_STALL_CYCLES_LRZ = 2, - PERF_RAS_STARVE_CYCLES_TSE = 3, - PERF_RAS_SUPER_TILES = 4, - PERF_RAS_8X4_TILES = 5, - PERF_RAS_MASKGEN_ACTIVE = 6, - PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, - PERF_RAS_FULLY_COVERED_8X4_TILES = 8, - PERF_RAS_PRIM_KILLED_INVISILBE = 9, - PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, - PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, - PERF_RAS_BLOCKS = 12, -}; - -enum a6xx_uche_perfcounter_select { - PERF_UCHE_BUSY_CYCLES = 0, - PERF_UCHE_STALL_CYCLES_ARBITER = 1, - PERF_UCHE_VBIF_LATENCY_CYCLES = 2, - PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, - PERF_UCHE_VBIF_READ_BEATS_TP = 4, - PERF_UCHE_VBIF_READ_BEATS_VFD = 5, - PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, - PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, - PERF_UCHE_VBIF_READ_BEATS_SP = 8, - PERF_UCHE_READ_REQUESTS_TP = 9, - PERF_UCHE_READ_REQUESTS_VFD = 10, - PERF_UCHE_READ_REQUESTS_HLSQ = 11, - PERF_UCHE_READ_REQUESTS_LRZ = 12, - PERF_UCHE_READ_REQUESTS_SP = 13, - PERF_UCHE_WRITE_REQUESTS_LRZ = 14, - PERF_UCHE_WRITE_REQUESTS_SP = 15, - PERF_UCHE_WRITE_REQUESTS_VPC = 16, - PERF_UCHE_WRITE_REQUESTS_VSC = 17, - PERF_UCHE_EVICTS = 18, - PERF_UCHE_BANK_REQ0 = 19, - PERF_UCHE_BANK_REQ1 = 20, - PERF_UCHE_BANK_REQ2 = 21, - PERF_UCHE_BANK_REQ3 = 22, - PERF_UCHE_BANK_REQ4 = 23, - PERF_UCHE_BANK_REQ5 = 24, - PERF_UCHE_BANK_REQ6 = 25, - PERF_UCHE_BANK_REQ7 = 26, - PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, - PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, - PERF_UCHE_GMEM_READ_BEATS = 29, - PERF_UCHE_TPH_REF_FULL = 30, - PERF_UCHE_TPH_VICTIM_FULL = 31, - PERF_UCHE_TPH_EXT_FULL = 32, - PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, - PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, - PERF_UCHE_DCMP_LATENCY_CYCLES = 35, - PERF_UCHE_VBIF_READ_BEATS_PC = 36, - PERF_UCHE_READ_REQUESTS_PC = 37, - PERF_UCHE_RAM_READ_REQ = 38, - PERF_UCHE_RAM_WRITE_REQ = 39, -}; - -enum a6xx_tp_perfcounter_select { - PERF_TP_BUSY_CYCLES = 0, - PERF_TP_STALL_CYCLES_UCHE = 1, - PERF_TP_LATENCY_CYCLES = 2, - PERF_TP_LATENCY_TRANS = 3, - PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, - PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, - PERF_TP_L1_CACHELINE_REQUESTS = 6, - PERF_TP_L1_CACHELINE_MISSES = 7, - PERF_TP_SP_TP_TRANS = 8, - PERF_TP_TP_SP_TRANS = 9, - PERF_TP_OUTPUT_PIXELS = 10, - PERF_TP_FILTER_WORKLOAD_16BIT = 11, - PERF_TP_FILTER_WORKLOAD_32BIT = 12, - PERF_TP_QUADS_RECEIVED = 13, - PERF_TP_QUADS_OFFSET = 14, - PERF_TP_QUADS_SHADOW = 15, - PERF_TP_QUADS_ARRAY = 16, - PERF_TP_QUADS_GRADIENT = 17, - PERF_TP_QUADS_1D = 18, - PERF_TP_QUADS_2D = 19, - PERF_TP_QUADS_BUFFER = 20, - PERF_TP_QUADS_3D = 21, - PERF_TP_QUADS_CUBE = 22, - PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, - PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, - PERF_TP_OUTPUT_PIXELS_POINT = 25, - PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, - PERF_TP_OUTPUT_PIXELS_MIP = 27, - PERF_TP_OUTPUT_PIXELS_ANISO = 28, - PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, - PERF_TP_FLAG_CACHE_REQUESTS = 30, - PERF_TP_FLAG_CACHE_MISSES = 31, - PERF_TP_L1_5_L2_REQUESTS = 32, - PERF_TP_2D_OUTPUT_PIXELS = 33, - PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, - PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, - PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, - PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, - PERF_TP_TPA2TPC_TRANS = 38, - PERF_TP_L1_MISSES_ASTC_1TILE = 39, - PERF_TP_L1_MISSES_ASTC_2TILE = 40, - PERF_TP_L1_MISSES_ASTC_4TILE = 41, - PERF_TP_L1_5_L2_COMPRESS_REQS = 42, - PERF_TP_L1_5_L2_COMPRESS_MISS = 43, - PERF_TP_L1_BANK_CONFLICT = 44, - PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, - PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, - PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, - PERF_TP_FRONTEND_WORKING_CYCLES = 48, - PERF_TP_L1_TAG_WORKING_CYCLES = 49, - PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, - PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, - PERF_TP_BACKEND_WORKING_CYCLES = 52, - PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, - PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, - PERF_TP_STARVE_CYCLES_SP = 55, - PERF_TP_STARVE_CYCLES_UCHE = 56, -}; - -enum a6xx_sp_perfcounter_select { - PERF_SP_BUSY_CYCLES = 0, - PERF_SP_ALU_WORKING_CYCLES = 1, - PERF_SP_EFU_WORKING_CYCLES = 2, - PERF_SP_STALL_CYCLES_VPC = 3, - PERF_SP_STALL_CYCLES_TP = 4, - PERF_SP_STALL_CYCLES_UCHE = 5, - PERF_SP_STALL_CYCLES_RB = 6, - PERF_SP_NON_EXECUTION_CYCLES = 7, - PERF_SP_WAVE_CONTEXTS = 8, - PERF_SP_WAVE_CONTEXT_CYCLES = 9, - PERF_SP_FS_STAGE_WAVE_CYCLES = 10, - PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, - PERF_SP_VS_STAGE_WAVE_CYCLES = 12, - PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, - PERF_SP_FS_STAGE_DURATION_CYCLES = 14, - PERF_SP_VS_STAGE_DURATION_CYCLES = 15, - PERF_SP_WAVE_CTRL_CYCLES = 16, - PERF_SP_WAVE_LOAD_CYCLES = 17, - PERF_SP_WAVE_EMIT_CYCLES = 18, - PERF_SP_WAVE_NOP_CYCLES = 19, - PERF_SP_WAVE_WAIT_CYCLES = 20, - PERF_SP_WAVE_FETCH_CYCLES = 21, - PERF_SP_WAVE_IDLE_CYCLES = 22, - PERF_SP_WAVE_END_CYCLES = 23, - PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, - PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, - PERF_SP_WAVE_JOIN_CYCLES = 26, - PERF_SP_LM_LOAD_INSTRUCTIONS = 27, - PERF_SP_LM_STORE_INSTRUCTIONS = 28, - PERF_SP_LM_ATOMICS = 29, - PERF_SP_GM_LOAD_INSTRUCTIONS = 30, - PERF_SP_GM_STORE_INSTRUCTIONS = 31, - PERF_SP_GM_ATOMICS = 32, - PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, - PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, - PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, - PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, - PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, - PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, - PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, - PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, - PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, - PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, - PERF_SP_VS_INSTRUCTIONS = 43, - PERF_SP_FS_INSTRUCTIONS = 44, - PERF_SP_ADDR_LOCK_COUNT = 45, - PERF_SP_UCHE_READ_TRANS = 46, - PERF_SP_UCHE_WRITE_TRANS = 47, - PERF_SP_EXPORT_VPC_TRANS = 48, - PERF_SP_EXPORT_RB_TRANS = 49, - PERF_SP_PIXELS_KILLED = 50, - PERF_SP_ICL1_REQUESTS = 51, - PERF_SP_ICL1_MISSES = 52, - PERF_SP_HS_INSTRUCTIONS = 53, - PERF_SP_DS_INSTRUCTIONS = 54, - PERF_SP_GS_INSTRUCTIONS = 55, - PERF_SP_CS_INSTRUCTIONS = 56, - PERF_SP_GPR_READ = 57, - PERF_SP_GPR_WRITE = 58, - PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, - PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, - PERF_SP_LM_BANK_CONFLICTS = 61, - PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, - PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, - PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, - PERF_SP_LM_WORKING_CYCLES = 65, - PERF_SP_DISPATCHER_WORKING_CYCLES = 66, - PERF_SP_SEQUENCER_WORKING_CYCLES = 67, - PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, - PERF_SP_STARVE_CYCLES_HLSQ = 69, - PERF_SP_NON_EXECUTION_LS_CYCLES = 70, - PERF_SP_WORKING_EU = 71, - PERF_SP_ANY_EU_WORKING = 72, - PERF_SP_WORKING_EU_FS_STAGE = 73, - PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, - PERF_SP_WORKING_EU_VS_STAGE = 75, - PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, - PERF_SP_WORKING_EU_CS_STAGE = 77, - PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, - PERF_SP_GPR_READ_PREFETCH = 79, - PERF_SP_GPR_READ_CONFLICT = 80, - PERF_SP_GPR_WRITE_CONFLICT = 81, - PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, - PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, - PERF_SP_EXECUTABLE_WAVES = 84, -}; - -enum a6xx_rb_perfcounter_select { - PERF_RB_BUSY_CYCLES = 0, - PERF_RB_STALL_CYCLES_HLSQ = 1, - PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, - PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, - PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, - PERF_RB_STARVE_CYCLES_SP = 5, - PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, - PERF_RB_STARVE_CYCLES_CCU = 7, - PERF_RB_STARVE_CYCLES_Z_PLANE = 8, - PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, - PERF_RB_Z_WORKLOAD = 10, - PERF_RB_HLSQ_ACTIVE = 11, - PERF_RB_Z_READ = 12, - PERF_RB_Z_WRITE = 13, - PERF_RB_C_READ = 14, - PERF_RB_C_WRITE = 15, - PERF_RB_TOTAL_PASS = 16, - PERF_RB_Z_PASS = 17, - PERF_RB_Z_FAIL = 18, - PERF_RB_S_FAIL = 19, - PERF_RB_BLENDED_FXP_COMPONENTS = 20, - PERF_RB_BLENDED_FP16_COMPONENTS = 21, - PERF_RB_PS_INVOCATIONS = 22, - PERF_RB_2D_ALIVE_CYCLES = 23, - PERF_RB_2D_STALL_CYCLES_A2D = 24, - PERF_RB_2D_STARVE_CYCLES_SRC = 25, - PERF_RB_2D_STARVE_CYCLES_SP = 26, - PERF_RB_2D_STARVE_CYCLES_DST = 27, - PERF_RB_2D_VALID_PIXELS = 28, - PERF_RB_3D_PIXELS = 29, - PERF_RB_BLENDER_WORKING_CYCLES = 30, - PERF_RB_ZPROC_WORKING_CYCLES = 31, - PERF_RB_CPROC_WORKING_CYCLES = 32, - PERF_RB_SAMPLER_WORKING_CYCLES = 33, - PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, - PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, - PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, - PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, - PERF_RB_STALL_CYCLES_VPC = 38, - PERF_RB_2D_INPUT_TRANS = 39, - PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, - PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, - PERF_RB_BLENDED_FP32_COMPONENTS = 42, - PERF_RB_COLOR_PIX_TILES = 43, - PERF_RB_STALL_CYCLES_CCU = 44, - PERF_RB_EARLY_Z_ARB3_GRANT = 45, - PERF_RB_LATE_Z_ARB3_GRANT = 46, - PERF_RB_EARLY_Z_SKIP_GRANT = 47, -}; - -enum a6xx_vsc_perfcounter_select { - PERF_VSC_BUSY_CYCLES = 0, - PERF_VSC_WORKING_CYCLES = 1, - PERF_VSC_STALL_CYCLES_UCHE = 2, - PERF_VSC_EOT_NUM = 3, - PERF_VSC_INPUT_TILES = 4, -}; - -enum a6xx_ccu_perfcounter_select { - PERF_CCU_BUSY_CYCLES = 0, - PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, - PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, - PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, - PERF_CCU_DEPTH_BLOCKS = 4, - PERF_CCU_COLOR_BLOCKS = 5, - PERF_CCU_DEPTH_BLOCK_HIT = 6, - PERF_CCU_COLOR_BLOCK_HIT = 7, - PERF_CCU_PARTIAL_BLOCK_READ = 8, - PERF_CCU_GMEM_READ = 9, - PERF_CCU_GMEM_WRITE = 10, - PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, - PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, - PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, - PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, - PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, - PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, - PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, - PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, - PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, - PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, - PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, - PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, - PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, - PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, - PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, - PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, - PERF_CCU_2D_RD_REQ = 27, - PERF_CCU_2D_WR_REQ = 28, -}; - -enum a6xx_lrz_perfcounter_select { - PERF_LRZ_BUSY_CYCLES = 0, - PERF_LRZ_STARVE_CYCLES_RAS = 1, - PERF_LRZ_STALL_CYCLES_RB = 2, - PERF_LRZ_STALL_CYCLES_VSC = 3, - PERF_LRZ_STALL_CYCLES_VPC = 4, - PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, - PERF_LRZ_STALL_CYCLES_UCHE = 6, - PERF_LRZ_LRZ_READ = 7, - PERF_LRZ_LRZ_WRITE = 8, - PERF_LRZ_READ_LATENCY = 9, - PERF_LRZ_MERGE_CACHE_UPDATING = 10, - PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, - PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, - PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, - PERF_LRZ_FULL_8X8_TILES = 14, - PERF_LRZ_PARTIAL_8X8_TILES = 15, - PERF_LRZ_TILE_KILLED = 16, - PERF_LRZ_TOTAL_PIXEL = 17, - PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, - PERF_LRZ_FULLY_COVERED_TILES = 19, - PERF_LRZ_PARTIAL_COVERED_TILES = 20, - PERF_LRZ_FEEDBACK_ACCEPT = 21, - PERF_LRZ_FEEDBACK_DISCARD = 22, - PERF_LRZ_FEEDBACK_STALL = 23, - PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, - PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, - PERF_LRZ_STALL_CYCLES_VC = 26, - PERF_LRZ_RAS_MASK_TRANS = 27, -}; - -enum a6xx_cmp_perfcounter_select { - PERF_CMPDECMP_STALL_CYCLES_ARB = 0, - PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, - PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, - PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, - PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, - PERF_CMPDECMP_VBIF_READ_REQUEST = 5, - PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, - PERF_CMPDECMP_VBIF_READ_DATA = 7, - PERF_CMPDECMP_VBIF_WRITE_DATA = 8, - PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, - PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, - PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, - PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, - PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, - PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, - PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, - PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, - PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, - PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, - PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, - PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, - PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, - PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, - PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, - PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, - PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, - PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, - PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, - PERF_CMPDECMP_2D_RD_DATA = 28, - PERF_CMPDECMP_2D_WR_DATA = 29, - PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, - PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, - PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, - PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, - PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, - PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, - PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, - PERF_CMPDECMP_2D_BUSY_CYCLES = 37, - PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, - PERF_CMPDECMP_2D_PIXELS = 39, -}; - -enum a6xx_2d_ifmt { - R2D_UNORM8 = 16, - R2D_INT32 = 7, - R2D_INT16 = 6, - R2D_INT8 = 5, - R2D_FLOAT32 = 4, - R2D_FLOAT16 = 3, -}; - -enum a6xx_tess_spacing { - TESS_EQUAL = 0, - TESS_FRACTIONAL_ODD = 2, - TESS_FRACTIONAL_EVEN = 3, -}; - -enum a6xx_tex_filter { - A6XX_TEX_NEAREST = 0, - A6XX_TEX_LINEAR = 1, - A6XX_TEX_ANISO = 2, -}; - -enum a6xx_tex_clamp { - A6XX_TEX_REPEAT = 0, - A6XX_TEX_CLAMP_TO_EDGE = 1, - A6XX_TEX_MIRROR_REPEAT = 2, - A6XX_TEX_CLAMP_TO_BORDER = 3, - A6XX_TEX_MIRROR_CLAMP = 4, -}; - -enum a6xx_tex_aniso { - A6XX_TEX_ANISO_1 = 0, - A6XX_TEX_ANISO_2 = 1, - A6XX_TEX_ANISO_4 = 2, - A6XX_TEX_ANISO_8 = 3, - A6XX_TEX_ANISO_16 = 4, -}; - -enum a6xx_tex_swiz { - A6XX_TEX_X = 0, - A6XX_TEX_Y = 1, - A6XX_TEX_Z = 2, - A6XX_TEX_W = 3, - A6XX_TEX_ZERO = 4, - A6XX_TEX_ONE = 5, -}; - -enum a6xx_tex_type { - A6XX_TEX_1D = 0, - A6XX_TEX_2D = 1, - A6XX_TEX_CUBE = 2, - A6XX_TEX_3D = 3, -}; - -#define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 -#define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 -#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 -#define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 -#define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 -#define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 -#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 -#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 -#define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 -#define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 -#define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 -#define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 -#define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 -#define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 -#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 -#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 -#define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 -#define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 -#define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 -#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 -#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 -#define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 -#define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 -#define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 -#define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 -#define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 -#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 -#define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 -#define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 -#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 -#define REG_A6XX_CP_RB_BASE 0x00000800 - -#define REG_A6XX_CP_RB_BASE_HI 0x00000801 - -#define REG_A6XX_CP_RB_CNTL 0x00000802 - -#define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804 - -#define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805 - -#define REG_A6XX_CP_RB_RPTR 0x00000806 - -#define REG_A6XX_CP_RB_WPTR 0x00000807 - -#define REG_A6XX_CP_SQE_CNTL 0x00000808 - -#define REG_A6XX_CP_HW_FAULT 0x00000821 - -#define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 - -#define REG_A6XX_CP_PROTECT_STATUS 0x00000824 - -#define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830 - -#define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831 - -#define REG_A6XX_CP_MISC_CNTL 0x00000840 - -#define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 - -#define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 - -#define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 - -#define REG_A6XX_CP_CHICKEN_DBG 0x00000841 - -#define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 - -#define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 - -#define REG_A6XX_CP_PROTECT_CNTL 0x0000084f - -static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } - -static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } - -static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } - -static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } -#define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff -#define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 -static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) -{ - return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; -} -#define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 -#define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 -static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) -{ - return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; -} -#define A6XX_CP_PROTECT_REG_READ 0x80000000 - -#define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 - -#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1 - -#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2 - -#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3 - -#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4 - -#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5 - -#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6 - -#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7 - -#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da - -#define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db - -#define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc - -#define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd - -#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 - -#define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901 - -#define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 - -#define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 - -#define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 - -#define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 - -#define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a - -#define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b - -#define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c - -#define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d - -#define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e - -#define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f - -#define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 - -#define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 - -#define REG_A6XX_CP_IB1_BASE 0x00000928 - -#define REG_A6XX_CP_IB1_BASE_HI 0x00000929 - -#define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a - -#define REG_A6XX_CP_IB2_BASE 0x0000092b - -#define REG_A6XX_CP_IB2_BASE_HI 0x0000092c - -#define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d - -#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 - -#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 - -#define REG_A6XX_CP_AHB_CNTL 0x0000098d - -#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 - -#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 - -#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 - -#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 - -#define REG_A6XX_RBBM_STATUS 0x00000210 -#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 -#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 -#define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 -#define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 -#define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 -#define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 -#define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 -#define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 -#define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 -#define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 -#define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 -#define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 -#define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 -#define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 -#define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 -#define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 -#define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 -#define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 -#define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 -#define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 -#define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 -#define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 -#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 -#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 - -#define REG_A6XX_RBBM_STATUS3 0x00000213 - -#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 - -#define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400 - -#define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401 - -#define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402 - -#define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403 - -#define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404 - -#define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405 - -#define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406 - -#define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407 - -#define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408 - -#define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409 - -#define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a - -#define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b - -#define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c - -#define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d - -#define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e - -#define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f - -#define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410 - -#define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411 - -#define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412 - -#define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413 - -#define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414 - -#define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415 - -#define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416 - -#define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417 - -#define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418 - -#define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419 - -#define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a - -#define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b - -#define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c - -#define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d - -#define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e - -#define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f - -#define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423 - -#define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424 - -#define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425 - -#define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426 - -#define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427 - -#define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428 - -#define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429 - -#define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a - -#define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b - -#define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c - -#define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d - -#define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e - -#define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f - -#define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430 - -#define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431 - -#define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432 - -#define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433 - -#define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434 - -#define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435 - -#define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436 - -#define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437 - -#define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438 - -#define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439 - -#define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a - -#define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b - -#define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c - -#define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d - -#define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e - -#define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f - -#define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440 - -#define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441 - -#define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442 - -#define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f - -#define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450 - -#define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451 - -#define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452 - -#define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453 - -#define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454 - -#define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455 - -#define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456 - -#define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457 - -#define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458 - -#define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459 - -#define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a - -#define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b - -#define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c - -#define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d - -#define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e - -#define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f - -#define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460 - -#define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461 - -#define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462 - -#define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463 - -#define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464 - -#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465 - -#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466 - -#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467 - -#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468 - -#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469 - -#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a - -#define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b - -#define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c - -#define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d - -#define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e - -#define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f - -#define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470 - -#define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471 - -#define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472 - -#define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473 - -#define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474 - -#define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a - -#define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b - -#define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c - -#define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d - -#define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e - -#define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f - -#define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a - -#define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b - -#define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c - -#define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d - -#define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e - -#define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f - -#define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490 - -#define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491 - -#define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492 - -#define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493 - -#define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494 - -#define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495 - -#define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496 - -#define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497 - -#define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498 - -#define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499 - -#define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a - -#define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b - -#define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c - -#define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d - -#define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e - -#define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f - -#define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0 - -#define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1 - -#define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2 - -#define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3 - -#define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4 - -#define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5 - -#define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6 - -#define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7 - -#define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8 - -#define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9 - -#define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa - -#define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab - -#define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac - -#define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad - -#define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae - -#define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af - -#define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0 - -#define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1 - -#define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2 - -#define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3 - -#define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4 - -#define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5 - -#define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6 - -#define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7 - -#define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8 - -#define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9 - -#define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba - -#define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb - -#define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc - -#define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd - -#define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be - -#define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf - -#define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0 - -#define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1 - -#define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2 - -#define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3 - -#define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4 - -#define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5 - -#define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6 - -#define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7 - -#define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8 - -#define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9 - -#define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca - -#define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb - -#define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc - -#define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd - -#define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce - -#define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf - -#define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0 - -#define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1 - -#define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2 - -#define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3 - -#define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4 - -#define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5 - -#define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6 - -#define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7 - -#define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8 - -#define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9 - -#define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da - -#define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db - -#define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc - -#define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd - -#define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de - -#define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df - -#define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0 - -#define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1 - -#define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2 - -#define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3 - -#define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4 - -#define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5 - -#define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6 - -#define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7 - -#define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8 - -#define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9 - -#define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea - -#define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb - -#define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec - -#define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed - -#define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee - -#define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef - -#define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0 - -#define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1 - -#define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2 - -#define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3 - -#define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4 - -#define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5 - -#define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6 - -#define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7 - -#define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8 - -#define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9 - -#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a - -#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b - -#define REG_A6XX_RBBM_ISDB_CNT 0x00000533 - -#define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 - -#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 - -#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 - -#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 - -#define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 - -#define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 - -#define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 - -#define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f - -#define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 - -#define REG_A6XX_RBBM_INT_0_MASK 0x00000038 - -#define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 - -#define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 - -#define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 - -#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 - -#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 - -#define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae - -#define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 - -#define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 - -#define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 - -#define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 - -#define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 - -#define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 - -#define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba - -#define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb - -#define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc - -#define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd - -#define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be - -#define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf - -#define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 - -#define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 - -#define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 - -#define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 - -#define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 - -#define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 - -#define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca - -#define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb - -#define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc - -#define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd - -#define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce - -#define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf - -#define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 - -#define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 - -#define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 - -#define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 - -#define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 - -#define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 - -#define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 - -#define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 - -#define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 - -#define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 - -#define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da - -#define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db - -#define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc - -#define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd - -#define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de - -#define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df - -#define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 - -#define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 - -#define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 - -#define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 - -#define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 - -#define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 - -#define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 - -#define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 - -#define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 - -#define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 - -#define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea - -#define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb - -#define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec - -#define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed - -#define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee - -#define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef - -#define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 - -#define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 - -#define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 - -#define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 - -#define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 - -#define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 - -#define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa - -#define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb - -#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 - -#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 - -#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 - -#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 - -#define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 - -#define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 - -#define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 - -#define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 - -#define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 - -#define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a - -#define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b - -#define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c - -#define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d - -#define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e - -#define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f - -#define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 - -#define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 - -#define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 - -#define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 - -#define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 - -#define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 - -#define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 - -#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 - -#define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 - -#define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 - -#define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a - -#define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b - -#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c - -#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 - -#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 - -#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 - -#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 -#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff -#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 -#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 -#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 -#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 - -#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 - -#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a - -#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b - -#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c - -#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d - -#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e - -#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f - -#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 -static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f - -#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 - -#define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8 - -#define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9 - -#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 - -#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610 - -#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611 - -#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612 - -#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613 - -#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614 - -#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615 - -#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616 - -#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617 - -#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618 - -#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619 - -#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a - -#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b - -#define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 - -#define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17 - -#define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18 - -#define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19 - -#define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a - -#define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b - -#define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c - -#define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c - -#define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d - -#define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e - -#define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f - -#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d - -#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 - -#define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 - -#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a - -#define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b - -#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15 - -#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 - -#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 - -#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617 - -#define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609 - -#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 - -#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 - -#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05 - -#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06 - -#define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07 - -#define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08 - -#define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09 - -#define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a - -#define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b - -#define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c - -#define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d - -#define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e - -#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 - -#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 - -#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 -#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff -#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 -static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) -{ - return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; -} - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27 - -#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 - -#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a - -#define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b - -#define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c - -#define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d - -#define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e - -#define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f - -#define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27 - -#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 - -#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b - -#define REG_A6XX_VBIF_VERSION 0x00003000 - -#define REG_A6XX_VBIF_CLKON 0x00003001 -#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 - -#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a - -#define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 - -#define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 - -#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 - -#define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 - -#define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 -#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f -#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 -static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) -{ - return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; -} - -#define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 - -#define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 -#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff -#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 -static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) -{ - return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; -} - -#define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c - -#define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 - -#define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 - -#define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 - -#define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 - -#define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 - -#define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 - -#define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da - -#define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db - -#define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 - -#define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 - -#define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 - -#define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a - -#define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 -#define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00007fff -#define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 -static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) -{ - return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; -} -#define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x7fff0000 -#define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 -static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) -{ - return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; -} - -#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 -#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff -#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 -static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) -{ - return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; -} -#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000 -#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 -static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) -{ - return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 -#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff -#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 -static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) -{ - return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; -} -#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000 -#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 -static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) -{ - return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 -#define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x000000ff -#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 -static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; -} -#define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x0001ff00 -#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 -static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) -{ - assert(!(val & 0xf)); - return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; -} -#define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000 -#define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000 - -#define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 -#define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x000000ff -#define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 -static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; -} -#define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x0001ff00 -#define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 -static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) -{ - assert(!(val & 0xf)); - return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; -} - -#define REG_A6XX_VSC_BIN_SIZE 0x00000c02 -#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff -#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 -static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; -} -#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 -#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 -static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) -{ - assert(!(val & 0xf)); - return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; -} - -#define REG_A6XX_VSC_SIZE_ADDRESS_LO 0x00000c03 - -#define REG_A6XX_VSC_SIZE_ADDRESS_HI 0x00000c04 - -#define REG_A6XX_VSC_BIN_COUNT 0x00000c06 -#define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe -#define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 -static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) -{ - return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; -} -#define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 -#define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 -static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) -{ - return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; -} - -static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } - -static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } -#define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff -#define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 -static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) -{ - return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; -} -#define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 -#define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 -static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) -{ - return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; -} -#define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 -#define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 -static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) -{ - return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; -} -#define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 -#define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 -static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) -{ - return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; -} - -#define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO 0x00000c30 - -#define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI 0x00000c31 - -#define REG_A6XX_VSC_PIPE_DATA2_PITCH 0x00000c32 - -#define REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH 0x00000c33 -#define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK 0xffffffff -#define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0xf)); - return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO 0x00000c34 - -#define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI 0x00000c35 - -#define REG_A6XX_VSC_PIPE_DATA_PITCH 0x00000c36 - -#define REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH 0x00000c37 -#define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK 0xffffffff -#define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0xf)); - return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK; -} - -static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } - -static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } - -#define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 - -#define REG_A6XX_GRAS_UNKNOWN_8000 0x00008000 - -#define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001 - -#define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004 - -#define REG_A6XX_GRAS_CNTL 0x00008005 -#define A6XX_GRAS_CNTL_VARYING 0x00000001 -#define A6XX_GRAS_CNTL_CENTROID 0x00000002 -#define A6XX_GRAS_CNTL_PERSAMP_VARYING 0x00000004 -#define A6XX_GRAS_CNTL_SIZE 0x00000008 -#define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020 -#define A6XX_GRAS_CNTL_XCOORD 0x00000040 -#define A6XX_GRAS_CNTL_YCOORD 0x00000080 -#define A6XX_GRAS_CNTL_ZCOORD 0x00000100 -#define A6XX_GRAS_CNTL_WCOORD 0x00000200 - -#define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 -#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff -#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 -static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) -{ - return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; -} -#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 -#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 -static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) -{ - return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; -} - -#define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0 0x00008010 -#define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 -static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK; -} - -#define REG_A6XX_GRAS_CL_VPORT_XSCALE_0 0x00008011 -#define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 -static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK; -} - -#define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0 0x00008012 -#define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 -static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK; -} - -#define REG_A6XX_GRAS_CL_VPORT_YSCALE_0 0x00008013 -#define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 -static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK; -} - -#define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0 0x00008014 -#define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 -static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; -} - -#define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0 0x00008015 -#define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 -static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK; -} - -#define REG_A6XX_GRAS_SU_CNTL 0x00008090 -#define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 -#define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 -#define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 -#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 -#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 -static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) -{ - return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; -} -#define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 -#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 - -#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 -#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff -#define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 -static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) -{ - return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; -} -#define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 -#define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 -static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) -{ - return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; -} - -#define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 -#define A6XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff -#define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 -static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) -{ - return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; -} - -#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 -#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 - -#define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 -#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff -#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 -static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) -{ - return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; -} - -#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 -#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff -#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 -static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) -{ - return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; -} - -#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 -#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff -#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 -static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) -{ - return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; -} - -#define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 -#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 -#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 -static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) -{ - return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; -} - -#define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099 - -#define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b - -#define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0 - -#define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 -#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; -} - -#define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 -#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; -} -#define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 - -#define REG_A6XX_GRAS_UNKNOWN_80A4 0x000080a4 - -#define REG_A6XX_GRAS_UNKNOWN_80A5 0x000080a5 - -#define REG_A6XX_GRAS_UNKNOWN_80A6 0x000080a6 - -#define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af - -#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x000080b0 -#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff -#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; -} -#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 -#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; -} - -#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x000080b1 -#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff -#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; -} -#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 -#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; -} - -#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x000080d0 -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; -} -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; -} - -#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x000080d1 -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; -} -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; -} - -#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff -#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; -} -#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; -} - -#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff -#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; -} -#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; -} - -#define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 -#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 -#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 -#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 -#define A6XX_GRAS_LRZ_CNTL_UNK3 0x00000008 -#define A6XX_GRAS_LRZ_CNTL_UNK4 0x00000010 - -#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101 - -#define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102 -#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK; -} - -#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103 - -#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104 - -#define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 -#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000007ff -#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 -static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; -} -#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800 -#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 -static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106 - -#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107 - -#define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 -#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 - -#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 - -#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 -#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000003 -#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 -static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(uint32_t val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; -} -#define A6XX_GRAS_2D_BLIT_CNTL_HORIZONTAL_FLIP 0x00000004 -#define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000010 -#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 -#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 -static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; -} -#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 -#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 -#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 -static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; -} - -#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 -#define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0xffffff00 -#define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT 8 -static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(int32_t val) -{ - return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK; -} - -#define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 -#define A6XX_GRAS_2D_SRC_BR_X_X__MASK 0xffffff00 -#define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT 8 -static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(int32_t val) -{ - return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK; -} - -#define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 -#define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK 0xffffff00 -#define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT 8 -static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(int32_t val) -{ - return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK; -} - -#define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 -#define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK 0xffffff00 -#define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT 8 -static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(int32_t val) -{ - return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK; -} - -#define REG_A6XX_GRAS_2D_DST_TL 0x00008405 -#define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_2D_DST_TL_X__MASK 0x00007fff -#define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; -} -#define A6XX_GRAS_2D_DST_TL_Y__MASK 0x7fff0000 -#define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; -} - -#define REG_A6XX_GRAS_2D_DST_BR 0x00008406 -#define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_2D_DST_BR_X__MASK 0x00007fff -#define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; -} -#define A6XX_GRAS_2D_DST_BR_Y__MASK 0x7fff0000 -#define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; -} - -#define REG_A6XX_GRAS_RESOLVE_CNTL_1 0x0000840a -#define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK 0x00007fff -#define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK; -} -#define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 -#define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK; -} - -#define REG_A6XX_GRAS_RESOLVE_CNTL_2 0x0000840b -#define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK 0x00007fff -#define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT 0 -static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val) -{ - return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK; -} -#define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 -#define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT 16 -static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val) -{ - return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK; -} - -#define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600 - -#define REG_A6XX_RB_BIN_CONTROL 0x00008800 -#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x000000ff -#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 -static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; -} -#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x0001ff00 -#define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 -static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) -{ - assert(!(val & 0xf)); - return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; -} -#define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000 -#define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000 - -#define REG_A6XX_RB_RENDER_CNTL 0x00008801 -#define A6XX_RB_RENDER_CNTL_UNK4 0x00000010 -#define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 -#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 -#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 -#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 -static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) -{ - return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; -} - -#define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 -#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; -} - -#define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 -#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; -} -#define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 - -#define REG_A6XX_RB_UNKNOWN_8804 0x00008804 - -#define REG_A6XX_RB_UNKNOWN_8805 0x00008805 - -#define REG_A6XX_RB_UNKNOWN_8806 0x00008806 - -#define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 -#define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001 -#define A6XX_RB_RENDER_CONTROL0_CENTROID 0x00000002 -#define A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING 0x00000004 -#define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008 -#define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020 -#define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 -#define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 -#define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 -#define A6XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 -#define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 - -#define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a -#define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 -#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 -#define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 -#define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010 -#define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020 -#define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040 - -#define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b -#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 -#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 - -#define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c -#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f -#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 -static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) -{ - return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; -} - -#define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d -#define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f -#define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 -static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 -#define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 -static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 -#define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 -static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 -#define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 -static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 -#define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 -static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 -#define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 -static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 -#define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 -static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 -#define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 -static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; -} - -#define REG_A6XX_RB_DITHER_CNTL 0x0000880e -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 -static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 -static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 -static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 -static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 -static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 -static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 -static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 -static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; -} - -#define REG_A6XX_RB_SRGB_CNTL 0x0000880f -#define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 - -#define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 -#define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 - -#define REG_A6XX_RB_UNKNOWN_8811 0x00008811 - -#define REG_A6XX_RB_UNKNOWN_8818 0x00008818 - -#define REG_A6XX_RB_UNKNOWN_8819 0x00008819 - -#define REG_A6XX_RB_UNKNOWN_881A 0x0000881a - -#define REG_A6XX_RB_UNKNOWN_881B 0x0000881b - -#define REG_A6XX_RB_UNKNOWN_881C 0x0000881c - -#define REG_A6XX_RB_UNKNOWN_881D 0x0000881d - -#define REG_A6XX_RB_UNKNOWN_881E 0x0000881e - -static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } - -static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } -#define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 -#define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 -#define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 -#define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 -#define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 -static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) -{ - return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; -} -#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 -#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 -static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) -{ - return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; -} - -static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 -static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 -static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 -static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 -static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 -static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 -static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; -} - -static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } -#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) -{ - return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; -} -#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 -#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 -static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; -} -#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 -#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 -static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; -} - -static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } -#define A6XX_RB_MRT_PITCH__MASK 0xffffffff -#define A6XX_RB_MRT_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; -} - -static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } -#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff -#define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; -} - -static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; } - -static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; } - -static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } - -#define REG_A6XX_RB_BLEND_RED_F32 0x00008860 -#define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff -#define A6XX_RB_BLEND_RED_F32__SHIFT 0 -static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) -{ - return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; -} - -#define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 -#define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff -#define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 -static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) -{ - return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; -} - -#define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 -#define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff -#define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 -static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) -{ - return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; -} - -#define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 -#define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff -#define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 -static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) -{ - return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; -} - -#define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 -#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff -#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 -static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) -{ - return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; -} -#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 -#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 -#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 -static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) -{ - return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; -} - -#define REG_A6XX_RB_BLEND_CNTL 0x00008865 -#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff -#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 -static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) -{ - return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; -} -#define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 -#define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 -#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 -#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 -static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) -{ - return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; -} - -#define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 -#define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 - -#define REG_A6XX_RB_DEPTH_CNTL 0x00008871 -#define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 -#define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 -#define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c -#define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 -static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) -{ - return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; -} -#define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 - -#define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 -#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 -#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 -static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) -{ - return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; -} - -#define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 -#define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff -#define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; -} - -#define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 -#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff -#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875 - -#define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876 - -#define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 - -#define REG_A6XX_RB_UNKNOWN_8878 0x00008878 - -#define REG_A6XX_RB_UNKNOWN_8879 0x00008879 - -#define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 -#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 -#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 -#define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 -#define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 -#define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 -static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 -#define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 -static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 -#define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 -static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 -#define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 -static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 -#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 -static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 -#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 -static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 -#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 -static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 -#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 -static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; -} - -#define REG_A6XX_RB_STENCIL_INFO 0x00008881 -#define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 - -#define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 -#define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0xffffffff -#define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; -} - -#define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 -#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0xffffffff -#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884 - -#define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885 - -#define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 - -#define REG_A6XX_RB_STENCILREF 0x00008887 -#define A6XX_RB_STENCILREF_REF__MASK 0x000000ff -#define A6XX_RB_STENCILREF_REF__SHIFT 0 -static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) -{ - return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; -} -#define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 -#define A6XX_RB_STENCILREF_BFREF__SHIFT 8 -static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) -{ - return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; -} - -#define REG_A6XX_RB_STENCILMASK 0x00008888 -#define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff -#define A6XX_RB_STENCILMASK_MASK__SHIFT 0 -static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) -{ - return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; -} -#define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 -#define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 -static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) -{ - return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; -} - -#define REG_A6XX_RB_STENCILWRMASK 0x00008889 -#define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff -#define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 -static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) -{ - return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; -} -#define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 -#define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 -static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) -{ - return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; -} - -#define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 -#define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff -#define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 -static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) -{ - return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; -} -#define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 -#define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 -static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) -{ - return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 -#define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 - -#define REG_A6XX_RB_LRZ_CNTL 0x00008898 -#define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 - -#define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 - -#define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 -#define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00007fff -#define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) -{ - return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; -} -#define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x7fff0000 -#define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 -static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) -{ - return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; -} - -#define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 -#define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00007fff -#define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) -{ - return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; -} -#define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x7fff0000 -#define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 -static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) -{ - return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; -} - -#define REG_A6XX_RB_MSAA_CNTL 0x000088d5 -#define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018 -#define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3 -static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK; -} - -#define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 - -#define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 -#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 -#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; -} -#define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 -#define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 -#define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 -static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; -} -#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 -#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 -static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) -{ - return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; -} -#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 -#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 -static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; -} - -#define REG_A6XX_RB_BLIT_DST_LO 0x000088d8 - -#define REG_A6XX_RB_BLIT_DST_HI 0x000088d9 - -#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da -#define A6XX_RB_BLIT_DST_PITCH__MASK 0xffffffff -#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; -} - -#define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db -#define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff -#define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc - -#define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd - -#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de -#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff -#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; -} -#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x003ff800 -#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 -static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x7f)); - return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df - -#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 - -#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 - -#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 - -#define REG_A6XX_RB_BLIT_INFO 0x000088e3 -#define A6XX_RB_BLIT_INFO_UNK0 0x00000001 -#define A6XX_RB_BLIT_INFO_GMEM 0x00000002 -#define A6XX_RB_BLIT_INFO_INTEGER 0x00000004 -#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 -#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 -#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 -static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) -{ - return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; -} - -#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 - -#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900 - -#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901 - -#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; -} -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800 -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 -static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x7f)); - return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; -} - -static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } - -static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; } - -static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; } - -static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } -#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff -#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; -} -#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800 -#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 -static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x7f)); - return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927 - -#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928 - -#define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 -#define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000003 -#define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 -static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(uint32_t val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; -} -#define A6XX_RB_2D_BLIT_CNTL_HORIZONTAL_FLIP 0x00000004 -#define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000010 -#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 -#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 -static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; -} -#define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 -#define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 -#define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 -static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; -} - -#define REG_A6XX_RB_UNKNOWN_8C01 0x00008c01 - -#define REG_A6XX_RB_2D_DST_INFO 0x00008c17 -#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) -{ - return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; -} -#define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 -#define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 -static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; -} -#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 -static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; -} -#define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 - -#define REG_A6XX_RB_2D_DST_LO 0x00008c18 - -#define REG_A6XX_RB_2D_DST_HI 0x00008c19 - -#define REG_A6XX_RB_2D_DST_SIZE 0x00008c1a -#define A6XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff -#define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK; -} - -#define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20 - -#define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21 - -#define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 -#define A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__MASK 0x000007ff -#define A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__MASK; -} -#define A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800 -#define A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11 -static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x7f)); - return ((val >> 7) << A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c - -#define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d - -#define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e - -#define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f - -#define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 - -#define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04 - -#define REG_A6XX_RB_CCU_CNTL 0x00008e07 - -#define REG_A6XX_VPC_UNKNOWN_9101 0x00009101 - -#define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104 - -#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 - -#define REG_A6XX_VPC_UNKNOWN_9108 0x00009108 - -static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } - -static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } - -static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } - -static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } - -#define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 - -#define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 - -static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } - -static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } - -#define REG_A6XX_VPC_SO_CNTL 0x00009216 -#define A6XX_VPC_SO_CNTL_ENABLE 0x00010000 - -#define REG_A6XX_VPC_SO_PROG 0x00009217 -#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 -#define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) -{ - return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; -} -#define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc -#define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 -static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; -} -#define A6XX_VPC_SO_PROG_A_EN 0x00000800 -#define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 -#define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 -static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) -{ - return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; -} -#define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 -#define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 -static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; -} -#define A6XX_VPC_SO_PROG_B_EN 0x00800000 - -static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } - -static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; } - -static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; } - -static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } - -static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } - -static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } - -static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; } - -static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; } - -#define REG_A6XX_VPC_UNKNOWN_9236 0x00009236 -#define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK 0x00000001 -#define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT 0 -static inline uint32_t A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(uint32_t val) -{ - return ((val) << A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT) & A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK; -} - -#define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 - -#define REG_A6XX_VPC_PACK 0x00009301 -#define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK 0x000000ff -#define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT 0 -static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val) -{ - return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK; -} -#define A6XX_VPC_PACK_NUMNONPOSVAR__MASK 0x0000ff00 -#define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT 8 -static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) -{ - return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK; -} -#define A6XX_VPC_PACK_PSIZELOC__MASK 0x00ff0000 -#define A6XX_VPC_PACK_PSIZELOC__SHIFT 16 -static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val) -{ - return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK; -} - -#define REG_A6XX_VPC_PACK_3 0x00009303 -#define A6XX_VPC_PACK_3_STRIDE_IN_VPC__MASK 0x000000ff -#define A6XX_VPC_PACK_3_STRIDE_IN_VPC__SHIFT 0 -static inline uint32_t A6XX_VPC_PACK_3_STRIDE_IN_VPC(uint32_t val) -{ - return ((val) << A6XX_VPC_PACK_3_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_3_STRIDE_IN_VPC__MASK; -} -#define A6XX_VPC_PACK_3_NUMNONPOSVAR__MASK 0x0000ff00 -#define A6XX_VPC_PACK_3_NUMNONPOSVAR__SHIFT 8 -static inline uint32_t A6XX_VPC_PACK_3_NUMNONPOSVAR(uint32_t val) -{ - return ((val) << A6XX_VPC_PACK_3_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_3_NUMNONPOSVAR__MASK; -} -#define A6XX_VPC_PACK_3_PSIZELOC__MASK 0x00ff0000 -#define A6XX_VPC_PACK_3_PSIZELOC__SHIFT 16 -static inline uint32_t A6XX_VPC_PACK_3_PSIZELOC(uint32_t val) -{ - return ((val) << A6XX_VPC_PACK_3_PSIZELOC__SHIFT) & A6XX_VPC_PACK_3_PSIZELOC__MASK; -} - -#define REG_A6XX_VPC_CNTL_0 0x00009304 -#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff -#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 -static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) -{ - return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; -} -#define A6XX_VPC_CNTL_0_VARYING 0x00010000 - -#define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305 -#define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 -#define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 -#define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 -#define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 -#define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 - -#define REG_A6XX_VPC_SO_OVERRIDE 0x00009306 -#define A6XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001 - -#define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 - -#define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 - -#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 - -#define REG_A6XX_PC_UNKNOWN_9801 0x00009801 - -#define REG_A6XX_PC_TESS_CNTL 0x00009802 -#define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 -#define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 -static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) -{ - return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; -} -#define A6XX_PC_TESS_CNTL_CCW 0x00000004 -#define A6XX_PC_TESS_CNTL_PRIMITIVES 0x00000008 - -#define REG_A6XX_PC_RESTART_INDEX 0x00009803 - -#define REG_A6XX_PC_MODE_CNTL 0x00009804 - -#define REG_A6XX_PC_UNKNOWN_9805 0x00009805 - -#define REG_A6XX_PC_UNKNOWN_9806 0x00009806 - -#define REG_A6XX_PC_UNKNOWN_9980 0x00009980 - -#define REG_A6XX_PC_UNKNOWN_9981 0x00009981 - -#define REG_A6XX_PC_UNKNOWN_9990 0x00009990 - -#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 -#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 -#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 - -#define REG_A6XX_PC_PRIMITIVE_CNTL_1 0x00009b01 -#define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK 0x0000007f -#define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT 0 -static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val) -{ - return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK; -} -#define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE 0x00000100 - -#define REG_A6XX_PC_PRIMITIVE_CNTL_3 0x00009b03 -#define A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__MASK 0x0000007f -#define A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__SHIFT 0 -static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC(uint32_t val) -{ - return ((val) << A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__MASK; -} -#define A6XX_PC_PRIMITIVE_CNTL_3_PSIZE 0x00000100 - -#define REG_A6XX_PC_PRIMITIVE_CNTL_4 0x00009b04 -#define A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__MASK 0x0000007f -#define A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__SHIFT 0 -static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(uint32_t val) -{ - return ((val) << A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__MASK; -} -#define A6XX_PC_PRIMITIVE_CNTL_4_PSIZE 0x00000100 - -#define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06 - -#define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07 - -#define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08 - -#define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09 - -#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 - -#define REG_A6XX_VFD_CONTROL_0 0x0000a000 -#define A6XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f -#define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 -static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val) -{ - return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK; -} - -#define REG_A6XX_VFD_CONTROL_1 0x0000a001 -#define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff -#define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 -static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) -{ - return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; -} -#define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 -#define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 -static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) -{ - return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; -} -#define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 -#define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 -static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) -{ - return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; -} - -#define REG_A6XX_VFD_CONTROL_2 0x0000a002 -#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff -#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0 -static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val) -{ - return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK; -} -#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 -#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 -static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) -{ - return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; -} - -#define REG_A6XX_VFD_CONTROL_3 0x0000a003 -#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00 -#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8 -static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val) -{ - return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK; -} -#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 -#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 -static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) -{ - return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; -} -#define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 -#define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 -static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) -{ - return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; -} - -#define REG_A6XX_VFD_CONTROL_4 0x0000a004 - -#define REG_A6XX_VFD_CONTROL_5 0x0000a005 - -#define REG_A6XX_VFD_CONTROL_6 0x0000a006 - -#define REG_A6XX_VFD_MODE_CNTL 0x0000a007 -#define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001 - -#define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008 - -#define REG_A6XX_VFD_UNKNOWN_A009 0x0000a009 - -#define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e - -#define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f - -static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } - -static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; } - -static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; } - -static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } - -static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } - -static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } - -static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } -#define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f -#define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 -static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) -{ - return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; -} -#define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 -#define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 -#define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 -static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val) -{ - return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; -} -#define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 -#define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 -static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; -} -#define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 -#define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 - -static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } - -static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } - -static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } -#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f -#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 -static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) -{ - return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; -} -#define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 -#define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 -static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) -{ - return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; -} - -#define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8 - -#define REG_A6XX_SP_PRIMITIVE_CNTL 0x0000a802 -#define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f -#define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0 -static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) -{ - return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; -} - -static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } - -static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } -#define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff -#define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 -static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) -{ - return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; -} -#define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 -#define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 -static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) -{ - return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; -} -#define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 -#define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 -static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) -{ - return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; -} -#define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 -#define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 -static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) -{ - return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; -} - -static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } - -static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) -{ - return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) -{ - return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) -{ - return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) -{ - return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 -#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000 - -#define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b - -#define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c - -#define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d - -#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 - -#define REG_A6XX_SP_VS_CONFIG 0x0000a823 -#define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 -static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) -{ - return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 -static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) -{ - return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000 -#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 -static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) -{ - return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 - -#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 -#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000 - -#define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831 - -#define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833 - -#define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834 - -#define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835 - -#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a - -#define REG_A6XX_SP_HS_CONFIG 0x0000a83b -#define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 -static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) -{ - return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 -static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) -{ - return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000 -#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 -static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) -{ - return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c - -#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 -#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000 - -#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 -#define A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__MASK 0x0000001f -#define A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__SHIFT 0 -static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(uint32_t val) -{ - return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__MASK; -} - -static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } - -static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } -#define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff -#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 -static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) -{ - return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; -} -#define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 -#define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 -static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) -{ - return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; -} -#define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 -#define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 -static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) -{ - return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; -} -#define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 -#define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 -static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) -{ - return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; -} - -static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } - -static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) -{ - return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) -{ - return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) -{ - return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) -{ - return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b - -#define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c - -#define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d - -#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 - -#define REG_A6XX_SP_DS_CONFIG 0x0000a863 -#define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 -static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) -{ - return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 -static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) -{ - return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000 -#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 -static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) -{ - return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 - -#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 -#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000 - -#define REG_A6XX_SP_GS_UNKNOWN_A871 0x0000a871 - -#define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d - -#define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e - -#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 - -#define REG_A6XX_SP_GS_CONFIG 0x0000a894 -#define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 -static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) -{ - return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 -static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) -{ - return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000 -#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 -static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) -{ - return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 - -#define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0 - -#define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1 - -#define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2 - -#define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3 - -#define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4 - -#define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5 - -#define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6 - -#define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7 - -#define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8 - -#define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9 - -#define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa - -#define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab - -#define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac - -#define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad - -#define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae - -#define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af - -#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 -#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 - -#define REG_A6XX_SP_UNKNOWN_A982 0x0000a982 - -#define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983 - -#define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984 - -#define REG_A6XX_SP_BLEND_CNTL 0x0000a989 -#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001 -#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 -#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 - -#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a -#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 - -#define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b -#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f -#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 -static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 -static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 -static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 -static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 -static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 -static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 -static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 -static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; -} - -#define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c -#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 -#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 -static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) -{ - return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; -} -#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 -#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 -static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) -{ - return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; -} - -#define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d -#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f -#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 -static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) -{ - return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; -} - -static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } - -static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } -#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val) -{ - return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; -} -#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 -#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 - -#define REG_A6XX_SP_UNKNOWN_A99E 0x0000a99e - -#define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 - -#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 - -#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 - -#define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3 - -#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba - -#define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0 - -#define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1 - -#define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2 - -#define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3 - -#define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4 - -#define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5 - -#define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6 - -#define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7 - -static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } - -static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } -#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff -#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 -static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) -{ - return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; -} -#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 - -#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 -#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 - -#define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4 - -#define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5 - -#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb -#define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 -static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) -{ - return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 -static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) -{ - return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000 -#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 -static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) -{ - return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc - -#define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2 - -#define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3 - -#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 - -#define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00 - -#define REG_A6XX_SP_FS_CONFIG 0x0000ab04 -#define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 -static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) -{ - return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 -static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) -{ - return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000 -#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 -static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) -{ - return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 - -#define REG_A6XX_SP_IBO_LO 0x0000ab1a - -#define REG_A6XX_SP_IBO_HI 0x0000ab1b - -#define REG_A6XX_SP_IBO_COUNT 0x0000ab20 - -#define REG_A6XX_SP_2D_SRC_FORMAT 0x0000acc0 -#define A6XX_SP_2D_SRC_FORMAT_NORM 0x00000001 -#define A6XX_SP_2D_SRC_FORMAT_SINT 0x00000002 -#define A6XX_SP_2D_SRC_FORMAT_UINT 0x00000004 -#define A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__MASK 0x000007f8 -#define A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__SHIFT 3 -static inline uint32_t A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(enum a6xx_color_fmt val) -{ - return ((val) << A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__MASK; -} - -#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 - -#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03 - -#define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04 - -#define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f - -#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 - -#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 - -#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 -#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; -} - -#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 -#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; -} -#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 - -#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302 - -#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303 - -#define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304 - -#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309 - -#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 -#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; -} -#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 -#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 -static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; -} -#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 -static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; -} -#define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 -#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 -#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 -static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; -} -#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 - -#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 -#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff -#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; -} -#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 -#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 -static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; -} - -#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2 - -#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3 - -#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 -#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00 -#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 -static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; -} - -#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca - -#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb - -#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK; -} -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800 -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11 -static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0x7f)); - return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_SP_UNKNOWN_B600 0x0000b600 - -#define REG_A6XX_SP_UNKNOWN_B605 0x0000b605 - -#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 -#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 -static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 - -#define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 -#define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 -static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 - -#define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 -#define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 -static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 - -#define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 -#define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 -static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 - -#define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980 - -#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 - -#define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 -#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff -#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; -} -#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 -#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 -static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; -} -#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 -#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 -static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; -} -#define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000 -#define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24 -static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK; -} - -#define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 -#define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__MASK 0x000000ff -#define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__MASK; -} -#define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__MASK 0x00ff0000 -#define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__SHIFT 16 -static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__MASK; -} - -#define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 -#define A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__MASK 0x000000ff -#define A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__MASK; -} -#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 -#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 -static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; -} -#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 -#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 -static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; -} - -#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 - -#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 -#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 - -#define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 -#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 -#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; -} -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; -} -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; -} -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 -#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 -#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 -#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 -#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 -#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 -#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; -} - -#define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 -#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff -#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; -} -#define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 -#define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 -static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK; -} -#define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 -#define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 -static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK; -} -#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 -#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 -static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; -} - -#define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998 - -#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 - -#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a - -#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b - -#define REG_A6XX_HLSQ_UPDATE_CNTL 0x0000bb08 - -#define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 -#define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 -static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 - -#define REG_A6XX_HLSQ_UNKNOWN_BB11 0x0000bb11 - -#define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 - -#define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 - -#define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 - -#define REG_A6XX_TEX_SAMP_0 0x00000000 -#define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 -#define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 -#define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 -static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) -{ - return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; -} -#define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 -#define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 -static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) -{ - return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; -} -#define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 -#define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 -static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) -{ - return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; -} -#define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 -#define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 -static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) -{ - return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; -} -#define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 -#define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 -static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) -{ - return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; -} -#define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 -#define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 -static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) -{ - return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; -} -#define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 -#define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 -static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) -{ - return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; -} - -#define REG_A6XX_TEX_SAMP_1 0x00000001 -#define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e -#define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 -static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) -{ - return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; -} -#define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 -#define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 -#define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 -#define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 -#define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 -static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) -{ - return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; -} -#define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 -#define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 -static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) -{ - return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; -} - -#define REG_A6XX_TEX_SAMP_2 0x00000002 -#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffffff -#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 0 -static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) -{ - return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; -} - -#define REG_A6XX_TEX_SAMP_3 0x00000003 - -#define REG_A6XX_TEX_CONST_0 0x00000000 -#define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 -#define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 -static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; -} -#define A6XX_TEX_CONST_0_SRGB 0x00000004 -#define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 -#define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 -static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) -{ - return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; -} -#define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 -#define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 -static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) -{ - return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; -} -#define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 -#define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 -static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) -{ - return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; -} -#define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 -#define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 -static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) -{ - return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; -} -#define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 -#define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 -static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) -{ - return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; -} -#define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 -#define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 -static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; -} -#define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 -#define A6XX_TEX_CONST_0_FMT__SHIFT 22 -static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val) -{ - return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; -} -#define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 -#define A6XX_TEX_CONST_0_SWAP__SHIFT 30 -static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; -} - -#define REG_A6XX_TEX_CONST_1 0x00000001 -#define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff -#define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 -static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) -{ - return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; -} -#define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 -#define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 -static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) -{ - return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; -} - -#define REG_A6XX_TEX_CONST_2 0x00000002 -#define A6XX_TEX_CONST_2_UNK4 0x00000010 -#define A6XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f -#define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 -static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val) -{ - return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK; -} -#define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 -#define A6XX_TEX_CONST_2_PITCH__SHIFT 7 -static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) -{ - return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; -} -#define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000 -#define A6XX_TEX_CONST_2_TYPE__SHIFT 29 -static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) -{ - return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; -} -#define A6XX_TEX_CONST_2_UNK31 0x80000000 - -#define REG_A6XX_TEX_CONST_3 0x00000003 -#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff -#define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; -} -#define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 -#define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 -static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; -} -#define A6XX_TEX_CONST_3_UNK27 0x08000000 -#define A6XX_TEX_CONST_3_FLAG 0x10000000 - -#define REG_A6XX_TEX_CONST_4 0x00000004 -#define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 -#define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 -static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; -} - -#define REG_A6XX_TEX_CONST_5 0x00000005 -#define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff -#define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 -static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) -{ - return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; -} -#define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 -#define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 -static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) -{ - return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; -} - -#define REG_A6XX_TEX_CONST_6 0x00000006 - -#define REG_A6XX_TEX_CONST_7 0x00000007 -#define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 -#define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 -static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) -{ - assert(!(val & 0x1f)); - return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; -} - -#define REG_A6XX_TEX_CONST_8 0x00000008 -#define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff -#define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 -static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) -{ - return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; -} - -#define REG_A6XX_TEX_CONST_9 0x00000009 -#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff -#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0xf)); - return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_TEX_CONST_10 0x0000000a -#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f -#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 -static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; -} - -#define REG_A6XX_TEX_CONST_11 0x0000000b - -#define REG_A6XX_TEX_CONST_12 0x0000000c - -#define REG_A6XX_TEX_CONST_13 0x0000000d - -#define REG_A6XX_TEX_CONST_14 0x0000000e - -#define REG_A6XX_TEX_CONST_15 0x0000000f - -#define REG_A6XX_IBO_0 0x00000000 -#define A6XX_IBO_0_TILE_MODE__MASK 0x00000003 -#define A6XX_IBO_0_TILE_MODE__SHIFT 0 -static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK; -} -#define A6XX_IBO_0_FMT__MASK 0x3fc00000 -#define A6XX_IBO_0_FMT__SHIFT 22 -static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_tex_fmt val) -{ - return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK; -} - -#define REG_A6XX_IBO_1 0x00000001 -#define A6XX_IBO_1_WIDTH__MASK 0x00007fff -#define A6XX_IBO_1_WIDTH__SHIFT 0 -static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val) -{ - return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK; -} -#define A6XX_IBO_1_HEIGHT__MASK 0x3fff8000 -#define A6XX_IBO_1_HEIGHT__SHIFT 15 -static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val) -{ - return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK; -} - -#define REG_A6XX_IBO_2 0x00000002 -#define A6XX_IBO_2_UNK4 0x00000010 -#define A6XX_IBO_2_PITCH__MASK 0x1fffff80 -#define A6XX_IBO_2_PITCH__SHIFT 7 -static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val) -{ - return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK; -} -#define A6XX_IBO_2_TYPE__MASK 0x60000000 -#define A6XX_IBO_2_TYPE__SHIFT 29 -static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val) -{ - return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK; -} -#define A6XX_IBO_2_UNK31 0x80000000 - -#define REG_A6XX_IBO_3 0x00000003 -#define A6XX_IBO_3_ARRAY_PITCH__MASK 0x00003fff -#define A6XX_IBO_3_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0xfff)); - return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK; -} -#define A6XX_IBO_3_UNK27 0x08000000 -#define A6XX_IBO_3_FLAG 0x10000000 - -#define REG_A6XX_IBO_4 0x00000004 -#define A6XX_IBO_4_BASE_LO__MASK 0xffffffff -#define A6XX_IBO_4_BASE_LO__SHIFT 0 -static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val) -{ - return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK; -} - -#define REG_A6XX_IBO_5 0x00000005 -#define A6XX_IBO_5_BASE_HI__MASK 0x0001ffff -#define A6XX_IBO_5_BASE_HI__SHIFT 0 -static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val) -{ - return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK; -} -#define A6XX_IBO_5_DEPTH__MASK 0x3ffe0000 -#define A6XX_IBO_5_DEPTH__SHIFT 17 -static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val) -{ - return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK; -} - -#define REG_A6XX_IBO_6 0x00000006 - -#define REG_A6XX_IBO_7 0x00000007 - -#define REG_A6XX_IBO_8 0x00000008 - -#define REG_A6XX_IBO_9 0x00000009 -#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff -#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 -static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) -{ - assert(!(val & 0xf)); - return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_IBO_10 0x0000000a -#define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f -#define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0 -static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val) -{ - assert(!(val & 0x3f)); - return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK; -} - -#define REG_A6XX_UBO_0 0x00000000 -#define A6XX_UBO_0_BASE_LO__MASK 0xffffffff -#define A6XX_UBO_0_BASE_LO__SHIFT 0 -static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) -{ - return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; -} - -#define REG_A6XX_UBO_1 0x00000001 -#define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff -#define A6XX_UBO_1_BASE_HI__SHIFT 0 -static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) -{ - return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; -} - -#define REG_CP_UNK_A6XX_55_0 0x00000000 -#define CP_UNK_A6XX_55_0_BASE_LO__MASK 0xffffffff -#define CP_UNK_A6XX_55_0_BASE_LO__SHIFT 0 -static inline uint32_t CP_UNK_A6XX_55_0_BASE_LO(uint32_t val) -{ - return ((val) << CP_UNK_A6XX_55_0_BASE_LO__SHIFT) & CP_UNK_A6XX_55_0_BASE_LO__MASK; -} - -#define REG_CP_UNK_A6XX_55_1 0x00000001 -#define CP_UNK_A6XX_55_1_BASE_HI__MASK 0x0001ffff -#define CP_UNK_A6XX_55_1_BASE_HI__SHIFT 0 -static inline uint32_t CP_UNK_A6XX_55_1_BASE_HI(uint32_t val) -{ - return ((val) << CP_UNK_A6XX_55_1_BASE_HI__SHIFT) & CP_UNK_A6XX_55_1_BASE_HI__MASK; -} - -#define REG_CP_UNK_A6XX_55_2 0x00000002 -#define CP_UNK_A6XX_55_2_SIZE__MASK 0x0000ffff -#define CP_UNK_A6XX_55_2_SIZE__SHIFT 0 -static inline uint32_t CP_UNK_A6XX_55_2_SIZE(uint32_t val) -{ - return ((val) << CP_UNK_A6XX_55_2_SIZE__SHIFT) & CP_UNK_A6XX_55_2_SIZE__MASK; -} - -#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 - -#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 - -#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 - -#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 - -#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 - -#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 - -#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 - -#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 - -#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 - -#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 - -#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 - -#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 - -#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 - -#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 - -#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 - -#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 - -#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 - -#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 - -#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 - -#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 - -#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 - -#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 - -#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 - -#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 - -#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da - -#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db - -#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 -static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 - -#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 - -#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 - - -#endif /* A6XX_XML */ diff --git a/src/freedreno/registers/adreno_common.xml b/src/freedreno/registers/adreno_common.xml new file mode 100644 index 00000000000..7c078a091cd --- /dev/null +++ b/src/freedreno/registers/adreno_common.xml @@ -0,0 +1,368 @@ +<?xml version="1.0" encoding="UTF-8"?> +<database xmlns="http://nouveau.freedesktop.org/" +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" +xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> + +<enum name="chip" bare="yes"> + <value name="A2XX"/> + <value name="A3XX"/> + <value name="A4XX"/> + <value name="A5XX"/> + <value name="A6XX"/> +</enum> + +<enum name="adreno_pa_su_sc_draw"> + <value name="PC_DRAW_POINTS" value="0"/> + <value name="PC_DRAW_LINES" value="1"/> + <value name="PC_DRAW_TRIANGLES" value="2"/> +</enum> + +<enum name="adreno_compare_func"> + <value name="FUNC_NEVER" value="0"/> + <value name="FUNC_LESS" value="1"/> + <value name="FUNC_EQUAL" value="2"/> + <value name="FUNC_LEQUAL" value="3"/> + <value name="FUNC_GREATER" value="4"/> + <value name="FUNC_NOTEQUAL" value="5"/> + <value name="FUNC_GEQUAL" value="6"/> + <value name="FUNC_ALWAYS" value="7"/> +</enum> + +<enum name="adreno_stencil_op"> + <value name="STENCIL_KEEP" value="0"/> + <value name="STENCIL_ZERO" value="1"/> + <value name="STENCIL_REPLACE" value="2"/> + <value name="STENCIL_INCR_CLAMP" value="3"/> + <value name="STENCIL_DECR_CLAMP" value="4"/> + <value name="STENCIL_INVERT" value="5"/> + <value name="STENCIL_INCR_WRAP" value="6"/> + <value name="STENCIL_DECR_WRAP" value="7"/> +</enum> + +<enum name="adreno_rb_blend_factor"> + <value name="FACTOR_ZERO" value="0"/> + <value name="FACTOR_ONE" value="1"/> + <value name="FACTOR_SRC_COLOR" value="4"/> + <value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/> + <value name="FACTOR_SRC_ALPHA" value="6"/> + <value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/> + <value name="FACTOR_DST_COLOR" value="8"/> + <value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/> + <value name="FACTOR_DST_ALPHA" value="10"/> + <value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/> + <value name="FACTOR_CONSTANT_COLOR" value="12"/> + <value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/> + <value name="FACTOR_CONSTANT_ALPHA" value="14"/> + <value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/> + <value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/> + <value name="FACTOR_SRC1_COLOR" value="20"/> + <value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/> + <value name="FACTOR_SRC1_ALPHA" value="22"/> + <value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/> +</enum> + +<bitset name="adreno_rb_stencilrefmask" inline="yes"> + <bitfield name="STENCILREF" low="0" high="7" type="hex"/> + <bitfield name="STENCILMASK" low="8" high="15" type="hex"/> + <bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/> +</bitset> + +<enum name="adreno_rb_surface_endian"> + <value name="ENDIAN_NONE" value="0"/> + <value name="ENDIAN_8IN16" value="1"/> + <value name="ENDIAN_8IN32" value="2"/> + <value name="ENDIAN_16IN32" value="3"/> + <value name="ENDIAN_8IN64" value="4"/> + <value name="ENDIAN_8IN128" value="5"/> +</enum> + +<enum name="adreno_rb_dither_mode"> + <value name="DITHER_DISABLE" value="0"/> + <value name="DITHER_ALWAYS" value="1"/> + <value name="DITHER_IF_ALPHA_OFF" value="2"/> +</enum> + +<enum name="adreno_rb_depth_format"> + <value name="DEPTHX_16" value="0"/> + <value name="DEPTHX_24_8" value="1"/> + <value name="DEPTHX_32" value="2"/> +</enum> + +<enum name="adreno_rb_copy_control_mode"> + <value name="RB_COPY_RESOLVE" value="1"/> + <value name="RB_COPY_CLEAR" value="2"/> + <value name="RB_COPY_DEPTH_STENCIL" value="5"/> <!-- not sure if this is part of MODE or another bitfield?? --> +</enum> + +<bitset name="adreno_reg_xy" inline="yes"> + <bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/> + <bitfield name="X" low="0" high="14" type="uint"/> + <bitfield name="Y" low="16" high="30" type="uint"/> +</bitset> + +<bitset name="adreno_cp_protect" inline="yes"> + <bitfield name="BASE_ADDR" low="0" high="16"/> + <bitfield name="MASK_LEN" low="24" high="28"/> + <bitfield name="TRAP_WRITE" pos="29"/> + <bitfield name="TRAP_READ" pos="30"/> +</bitset> + +<domain name="AXXX" width="32"> + <brief>Registers in common between a2xx and a3xx</brief> + + <reg32 offset="0x01c0" name="CP_RB_BASE"/> + <reg32 offset="0x01c1" name="CP_RB_CNTL"> + <bitfield name="BUFSZ" low="0" high="5"/> + <bitfield name="BLKSZ" low="8" high="13"/> + <bitfield name="BUF_SWAP" low="16" high="17"/> + <bitfield name="POLL_EN" pos="20" type="boolean"/> + <bitfield name="NO_UPDATE" pos="27" type="boolean"/> + <bitfield name="RPTR_WR_EN" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR"> + <bitfield name="SWAP" low="0" high="1" type="uint"/> + <bitfield name="ADDR" low="2" high="31" shr="2"/> + </reg32> + <reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/> + <reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/> + <reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/> + <reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/> + <reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/> + <reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS"> + <bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/> + <bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/> + <bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/> + </reg32> + <reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS"> + <bitfield name="MEQ_END" low="16" high="20" type="uint"/> + <bitfield name="ROQ_END" low="24" high="28" type="uint"/> + </reg32> + <reg32 offset="0x01d7" name="CP_CSQ_AVAIL"> + <bitfield name="RING" low="0" high="6" type="uint"/> + <bitfield name="IB1" low="8" high="14" type="uint"/> + <bitfield name="IB2" low="16" high="22" type="uint"/> + </reg32> + <reg32 offset="0x01d8" name="CP_STQ_AVAIL"> + <bitfield name="ST" low="0" high="6" type="uint"/> + </reg32> + <reg32 offset="0x01d9" name="CP_MEQ_AVAIL"> + <bitfield name="MEQ" low="0" high="4" type="uint"/> + </reg32> + <reg32 offset="0x01dc" name="SCRATCH_UMSK"> + <bitfield name="UMSK" low="0" high="7" type="uint"/> + <bitfield name="SWAP" low="16" high="17" type="uint"/> + </reg32> + <reg32 offset="0x01dd" name="SCRATCH_ADDR"/> + <reg32 offset="0x01ea" name="CP_ME_RDADDR"/> + + <reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/> + <reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/> + <reg32 offset="0x01f2" name="CP_INT_CNTL"> + <bitfield name="SW_INT_MASK" pos="19" type="boolean"/> + <bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/> + <bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/> + <bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/> + <bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/> + <bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/> + <bitfield name="IB2_INT_MASK" pos="29" type="boolean"/> + <bitfield name="IB1_INT_MASK" pos="30" type="boolean"/> + <bitfield name="RB_INT_MASK" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x01f3" name="CP_INT_STATUS"/> + <reg32 offset="0x01f4" name="CP_INT_ACK"/> + <reg32 offset="0x01f6" name="CP_ME_CNTL"> + <bitfield name="BUSY" pos="29" type="boolean"/> + <bitfield name="HALT" pos="28" type="boolean"/> + </reg32> + <reg32 offset="0x01f7" name="CP_ME_STATUS"/> + <reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/> + <reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/> + <reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/> + <reg32 offset="0x01fc" name="CP_DEBUG"> + <bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/> + <bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/> + <bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/> + <bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/> + <bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/> + <bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/> + <bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/> + <bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="0x01fd" name="CP_CSQ_RB_STAT"> + <bitfield name="RPTR" low="0" high="6" type="uint"/> + <bitfield name="WPTR" low="16" high="22" type="uint"/> + </reg32> + <reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT"> + <bitfield name="RPTR" low="0" high="6" type="uint"/> + <bitfield name="WPTR" low="16" high="22" type="uint"/> + </reg32> + <reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT"> + <bitfield name="RPTR" low="0" high="6" type="uint"/> + <bitfield name="WPTR" low="16" high="22" type="uint"/> + </reg32> + + <reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/> + <reg32 offset="0x0443" name="CP_STQ_ST_STAT"/> + <reg32 offset="0x044d" name="CP_ST_BASE"/> + <reg32 offset="0x044e" name="CP_ST_BUFSZ"/> + <reg32 offset="0x044f" name="CP_MEQ_STAT"/> + <reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/> + <reg32 offset="0x0454" name="CP_BIN_MASK_LO"/> + <reg32 offset="0x0455" name="CP_BIN_MASK_HI"/> + <reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/> + <reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/> + <reg32 offset="0x0458" name="CP_IB1_BASE"/> + <reg32 offset="0x0459" name="CP_IB1_BUFSZ"/> + <reg32 offset="0x045a" name="CP_IB2_BASE"/> + <reg32 offset="0x045b" name="CP_IB2_BUFSZ"/> + <reg32 offset="0x047f" name="CP_STAT"> + <bitfield pos="31" name="CP_BUSY"/> + <bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/> + <bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/> + <bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/> + <bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/> + <bitfield pos="26" name="ME_BUSY"/> + <bitfield pos="25" name="MIU_WR_C_BUSY"/> + <bitfield pos="23" name="CP_3D_BUSY"/> + <bitfield pos="22" name="CP_NRT_BUSY"/> + <bitfield pos="21" name="RBIU_SCRATCH_BUSY"/> + <bitfield pos="20" name="RCIU_ME_BUSY"/> + <bitfield pos="19" name="RCIU_PFP_BUSY"/> + <bitfield pos="18" name="MEQ_RING_BUSY"/> + <bitfield pos="17" name="PFP_BUSY"/> + <bitfield pos="16" name="ST_QUEUE_BUSY"/> + <bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/> + <bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/> + <bitfield pos="11" name="RING_QUEUE_BUSY"/> + <bitfield pos="10" name="CSF_BUSY"/> + <bitfield pos="9" name="CSF_ST_BUSY"/> + <bitfield pos="8" name="EVENT_BUSY"/> + <bitfield pos="7" name="CSF_INDIRECT2_BUSY"/> + <bitfield pos="6" name="CSF_INDIRECTS_BUSY"/> + <bitfield pos="5" name="CSF_RING_BUSY"/> + <bitfield pos="4" name="RCIU_BUSY"/> + <bitfield pos="3" name="RBIU_BUSY"/> + <bitfield pos="2" name="MIU_RD_RETURN_BUSY"/> + <bitfield pos="1" name="MIU_RD_REQ_BUSY"/> + <bitfield pos="0" name="MIU_WR_BUSY"/> + </reg32> + <reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/> + <reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/> + <reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/> + <reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/> + <reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/> + <reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/> + <reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/> + <reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/> + + <reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/> + <reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/> + <reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/> + <reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/> + <reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/> + <reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/> + <reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/> + <reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/> + <reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/> + <reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/> + <reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/> + <reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/> + <reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/> + <reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/> + <reg32 offset="0x060e" name="CP_ME_NRT_DATA"/> + <reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/> + <reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/> + <reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/> + +</domain> + +<!-- + Common between A3xx and A4xx: + --> + +<enum name="a3xx_regid"> + <value name="REGID_UNUSED" value="0xfc"/> +</enum> + +<enum name="a3xx_rop_code"> + <value name="ROP_CLEAR" value="0"/> + <value name="ROP_NOR" value="1"/> + <value name="ROP_AND_INVERTED" value="2"/> + <value name="ROP_COPY_INVERTED" value="3"/> + <value name="ROP_AND_REVERSE" value="4"/> + <value name="ROP_INVERT" value="5"/> + <value name="ROP_XOR" value="6"/> + <value name="ROP_NAND" value="7"/> + <value name="ROP_AND" value="8"/> + <value name="ROP_EQUIV" value="9"/> + <value name="ROP_NOOP" value="10"/> + <value name="ROP_OR_INVERTED" value="11"/> + <value name="ROP_COPY" value="12"/> + <value name="ROP_OR_REVERSE" value="13"/> + <value name="ROP_OR" value="14"/> + <value name="ROP_SET" value="15"/> +</enum> + +<enum name="a3xx_render_mode"> + <value name="RB_RENDERING_PASS" value="0"/> + <value name="RB_TILING_PASS" value="1"/> + <value name="RB_RESOLVE_PASS" value="2"/> + <value name="RB_COMPUTE_PASS" value="3"/> +</enum> + +<enum name="a3xx_msaa_samples"> + <value name="MSAA_ONE" value="0"/> + <value name="MSAA_TWO" value="1"/> + <value name="MSAA_FOUR" value="2"/> + <value name="MSAA_EIGHT" value="3"/> +</enum> + +<enum name="a3xx_threadmode"> + <value value="0" name="MULTI"/> + <value value="1" name="SINGLE"/> +</enum> + +<enum name="a3xx_instrbuffermode"> + <!-- + When shader size goes above ~128 or so, blob switches to '0' + and doesn't emit shader in cmdstream. When either is '0' it + doesn't get emitted via CP_LOAD_STATE. When only one is + '0' the other gets size 256-others_size. So I think that: + BUFFER => execute out of state memory + CACHE => use available state memory as local cache + NOTE that when CACHE mode, also set CACHEINVALID flag! + + TODO check if that 256 size is same for all a3xx + --> + <value value="0" name="CACHE"/> + <value value="1" name="BUFFER"/> +</enum> + +<enum name="a3xx_threadsize"> + <value value="0" name="TWO_QUADS"/> + <value value="1" name="FOUR_QUADS"/> +</enum> + +<enum name="a3xx_color_swap"> + <value name="WZYX" value="0"/> + <value name="WXYZ" value="1"/> + <value name="ZYXW" value="2"/> + <value name="XYZW" value="3"/> +</enum> + +<enum name="a3xx_rb_blend_opcode"> + <value name="BLEND_DST_PLUS_SRC" value="0"/> + <value name="BLEND_SRC_MINUS_DST" value="1"/> + <value name="BLEND_DST_MINUS_SRC" value="2"/> + <value name="BLEND_MIN_DST_SRC" value="3"/> + <value name="BLEND_MAX_DST_SRC" value="4"/> +</enum> + +<enum name="a4xx_tess_spacing"> + <value name="EQUAL_SPACING" value="0"/> + <value name="ODD_SPACING" value="2"/> + <value name="EVEN_SPACING" value="3"/> +</enum> + +</database> + diff --git a/src/freedreno/registers/adreno_common.xml.h b/src/freedreno/registers/adreno_common.xml.h deleted file mode 100644 index 53a67a195b0..00000000000 --- a/src/freedreno/registers/adreno_common.xml.h +++ /dev/null @@ -1,536 +0,0 @@ -#ifndef ADRENO_COMMON_XML -#define ADRENO_COMMON_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2018 by the following authors: -- Rob Clark <[email protected]> (robclark) -- Ilia Mirkin <[email protected]> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum chip { - A2XX = 0, - A3XX = 0, - A4XX = 0, - A5XX = 0, - A6XX = 0, -}; - -enum adreno_pa_su_sc_draw { - PC_DRAW_POINTS = 0, - PC_DRAW_LINES = 1, - PC_DRAW_TRIANGLES = 2, -}; - -enum adreno_compare_func { - FUNC_NEVER = 0, - FUNC_LESS = 1, - FUNC_EQUAL = 2, - FUNC_LEQUAL = 3, - FUNC_GREATER = 4, - FUNC_NOTEQUAL = 5, - FUNC_GEQUAL = 6, - FUNC_ALWAYS = 7, -}; - -enum adreno_stencil_op { - STENCIL_KEEP = 0, - STENCIL_ZERO = 1, - STENCIL_REPLACE = 2, - STENCIL_INCR_CLAMP = 3, - STENCIL_DECR_CLAMP = 4, - STENCIL_INVERT = 5, - STENCIL_INCR_WRAP = 6, - STENCIL_DECR_WRAP = 7, -}; - -enum adreno_rb_blend_factor { - FACTOR_ZERO = 0, - FACTOR_ONE = 1, - FACTOR_SRC_COLOR = 4, - FACTOR_ONE_MINUS_SRC_COLOR = 5, - FACTOR_SRC_ALPHA = 6, - FACTOR_ONE_MINUS_SRC_ALPHA = 7, - FACTOR_DST_COLOR = 8, - FACTOR_ONE_MINUS_DST_COLOR = 9, - FACTOR_DST_ALPHA = 10, - FACTOR_ONE_MINUS_DST_ALPHA = 11, - FACTOR_CONSTANT_COLOR = 12, - FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, - FACTOR_CONSTANT_ALPHA = 14, - FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, - FACTOR_SRC_ALPHA_SATURATE = 16, - FACTOR_SRC1_COLOR = 20, - FACTOR_ONE_MINUS_SRC1_COLOR = 21, - FACTOR_SRC1_ALPHA = 22, - FACTOR_ONE_MINUS_SRC1_ALPHA = 23, -}; - -enum adreno_rb_surface_endian { - ENDIAN_NONE = 0, - ENDIAN_8IN16 = 1, - ENDIAN_8IN32 = 2, - ENDIAN_16IN32 = 3, - ENDIAN_8IN64 = 4, - ENDIAN_8IN128 = 5, -}; - -enum adreno_rb_dither_mode { - DITHER_DISABLE = 0, - DITHER_ALWAYS = 1, - DITHER_IF_ALPHA_OFF = 2, -}; - -enum adreno_rb_depth_format { - DEPTHX_16 = 0, - DEPTHX_24_8 = 1, - DEPTHX_32 = 2, -}; - -enum adreno_rb_copy_control_mode { - RB_COPY_RESOLVE = 1, - RB_COPY_CLEAR = 2, - RB_COPY_DEPTH_STENCIL = 5, -}; - -enum a3xx_rop_code { - ROP_CLEAR = 0, - ROP_NOR = 1, - ROP_AND_INVERTED = 2, - ROP_COPY_INVERTED = 3, - ROP_AND_REVERSE = 4, - ROP_INVERT = 5, - ROP_XOR = 6, - ROP_NAND = 7, - ROP_AND = 8, - ROP_EQUIV = 9, - ROP_NOOP = 10, - ROP_OR_INVERTED = 11, - ROP_COPY = 12, - ROP_OR_REVERSE = 13, - ROP_OR = 14, - ROP_SET = 15, -}; - -enum a3xx_render_mode { - RB_RENDERING_PASS = 0, - RB_TILING_PASS = 1, - RB_RESOLVE_PASS = 2, - RB_COMPUTE_PASS = 3, -}; - -enum a3xx_msaa_samples { - MSAA_ONE = 0, - MSAA_TWO = 1, - MSAA_FOUR = 2, - MSAA_EIGHT = 3, -}; - -enum a3xx_threadmode { - MULTI = 0, - SINGLE = 1, -}; - -enum a3xx_instrbuffermode { - CACHE = 0, - BUFFER = 1, -}; - -enum a3xx_threadsize { - TWO_QUADS = 0, - FOUR_QUADS = 1, -}; - -enum a3xx_color_swap { - WZYX = 0, - WXYZ = 1, - ZYXW = 2, - XYZW = 3, -}; - -enum a3xx_rb_blend_opcode { - BLEND_DST_PLUS_SRC = 0, - BLEND_SRC_MINUS_DST = 1, - BLEND_DST_MINUS_SRC = 2, - BLEND_MIN_DST_SRC = 3, - BLEND_MAX_DST_SRC = 4, -}; - -enum a4xx_tess_spacing { - EQUAL_SPACING = 0, - ODD_SPACING = 2, - EVEN_SPACING = 3, -}; - -#define REG_AXXX_CP_RB_BASE 0x000001c0 - -#define REG_AXXX_CP_RB_CNTL 0x000001c1 -#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f -#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 -static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) -{ - return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; -} -#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 -#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 -static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) -{ - return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; -} -#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 -#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 -static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) -{ - return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; -} -#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 -#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 -#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 - -#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 -#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 -#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 -static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) -{ - return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; -} -#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc -#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 -static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; -} - -#define REG_AXXX_CP_RB_RPTR 0x000001c4 - -#define REG_AXXX_CP_RB_WPTR 0x000001c5 - -#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 - -#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 - -#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 - -#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 -static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) -{ - return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; -} -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 -static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) -{ - return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; -} -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 -static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) -{ - return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; -} - -#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 -#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 -#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 -static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) -{ - return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; -} -#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 -#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 -static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) -{ - return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; -} - -#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 -#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f -#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 -static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) -{ - return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; -} -#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 -#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 -static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) -{ - return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; -} -#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 -#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 -static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) -{ - return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; -} - -#define REG_AXXX_CP_STQ_AVAIL 0x000001d8 -#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f -#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 -static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) -{ - return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; -} - -#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 -#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f -#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 -static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) -{ - return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; -} - -#define REG_AXXX_SCRATCH_UMSK 0x000001dc -#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff -#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 -static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) -{ - return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; -} -#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 -#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 -static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) -{ - return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; -} - -#define REG_AXXX_SCRATCH_ADDR 0x000001dd - -#define REG_AXXX_CP_ME_RDADDR 0x000001ea - -#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec - -#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed - -#define REG_AXXX_CP_INT_CNTL 0x000001f2 -#define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000 -#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000 -#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000 -#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000 -#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000 -#define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000 -#define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000 -#define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000 -#define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000 - -#define REG_AXXX_CP_INT_STATUS 0x000001f3 - -#define REG_AXXX_CP_INT_ACK 0x000001f4 - -#define REG_AXXX_CP_ME_CNTL 0x000001f6 -#define AXXX_CP_ME_CNTL_BUSY 0x20000000 -#define AXXX_CP_ME_CNTL_HALT 0x10000000 - -#define REG_AXXX_CP_ME_STATUS 0x000001f7 - -#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 - -#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 - -#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa - -#define REG_AXXX_CP_DEBUG 0x000001fc -#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 -#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 -#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 -#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 -#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 -#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 -#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 -#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 - -#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd -#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f -#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 -static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) -{ - return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; -} -#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 -#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 -static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) -{ - return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; -} - -#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe -#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f -#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 -static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) -{ - return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; -} -#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 -#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 -static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) -{ - return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; -} - -#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff -#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f -#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 -static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) -{ - return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; -} -#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 -#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 -static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) -{ - return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; -} - -#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 - -#define REG_AXXX_CP_STQ_ST_STAT 0x00000443 - -#define REG_AXXX_CP_ST_BASE 0x0000044d - -#define REG_AXXX_CP_ST_BUFSZ 0x0000044e - -#define REG_AXXX_CP_MEQ_STAT 0x0000044f - -#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 - -#define REG_AXXX_CP_BIN_MASK_LO 0x00000454 - -#define REG_AXXX_CP_BIN_MASK_HI 0x00000455 - -#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 - -#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 - -#define REG_AXXX_CP_IB1_BASE 0x00000458 - -#define REG_AXXX_CP_IB1_BUFSZ 0x00000459 - -#define REG_AXXX_CP_IB2_BASE 0x0000045a - -#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b - -#define REG_AXXX_CP_STAT 0x0000047f -#define AXXX_CP_STAT_CP_BUSY 0x80000000 -#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000 -#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000 -#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000 -#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000 -#define AXXX_CP_STAT_ME_BUSY 0x04000000 -#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000 -#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000 -#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000 -#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000 -#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000 -#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000 -#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000 -#define AXXX_CP_STAT_PFP_BUSY 0x00020000 -#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000 -#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000 -#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000 -#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800 -#define AXXX_CP_STAT_CSF_BUSY 0x00000400 -#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200 -#define AXXX_CP_STAT_EVENT_BUSY 0x00000100 -#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080 -#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040 -#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020 -#define AXXX_CP_STAT_RCIU_BUSY 0x00000010 -#define AXXX_CP_STAT_RBIU_BUSY 0x00000008 -#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004 -#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002 -#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 - -#define REG_AXXX_CP_SCRATCH_REG0 0x00000578 - -#define REG_AXXX_CP_SCRATCH_REG1 0x00000579 - -#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a - -#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b - -#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c - -#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d - -#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e - -#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f - -#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 - -#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 - -#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 - -#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 - -#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 - -#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 - -#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 - -#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 - -#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 - -#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 - -#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a - -#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b - -#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c - -#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d - -#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e - -#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 - -#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 - -#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 - - -#endif /* ADRENO_COMMON_XML */ diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml new file mode 100644 index 00000000000..dfb50bfdaf9 --- /dev/null +++ b/src/freedreno/registers/adreno_pm4.xml @@ -0,0 +1,1160 @@ +<?xml version="1.0" encoding="UTF-8"?> +<database xmlns="http://nouveau.freedesktop.org/" +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" +xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> + +<enum name="vgt_event_type"> + <value name="VS_DEALLOC" value="0"/> + <value name="PS_DEALLOC" value="1"/> + <value name="VS_DONE_TS" value="2"/> + <value name="PS_DONE_TS" value="3"/> + <value name="CACHE_FLUSH_TS" value="4"/> + <value name="CONTEXT_DONE" value="5"/> + <value name="CACHE_FLUSH" value="6"/> + <value name="HLSQ_FLUSH" value="7"/> <!-- on a3xx --> + <value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) --> + <value name="VIZQUERY_END" value="8"/> + <value name="SC_WAIT_WC" value="9"/> + <value name="RST_PIX_CNT" value="13"/> + <value name="RST_VTX_CNT" value="14"/> + <value name="TILE_FLUSH" value="15"/> + <value name="STAT_EVENT" value="16"/> + <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/> + <value name="ZPASS_DONE" value="21"/> + <value name="CACHE_FLUSH_AND_INV_EVENT" value="22"/> + <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/> + <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/> + <value name="VS_FETCH_DONE" value="27"/> + <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/> + + <!-- a5xx events --> + <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/> + <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/> + <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/> + <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/> + <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/> + <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/> + <value name="UNK_1C" value="28" variants="A5XX,A6XX"/> + <value name="UNK_1D" value="29" variants="A5XX,A6XX"/> + <value name="BLIT" value="30" variants="A5XX,A6XX"/> + <value name="UNK_25" value="37" variants="A5XX"/> + <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/> + <value name="UNK_2C" value="44" variants="A5XX"/> + <value name="UNK_2D" value="45" variants="A5XX"/> +</enum> + +<enum name="pc_di_primtype"> + <value name="DI_PT_NONE" value="0"/> + <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: --> + <value name="DI_PT_POINTLIST_PSIZE" value="1"/> + <value name="DI_PT_LINELIST" value="2"/> + <value name="DI_PT_LINESTRIP" value="3"/> + <value name="DI_PT_TRILIST" value="4"/> + <value name="DI_PT_TRIFAN" value="5"/> + <value name="DI_PT_TRISTRIP" value="6"/> + <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx --> + <value name="DI_PT_RECTLIST" value="8"/> + <value name="DI_PT_POINTLIST" value="9"/> + <value name="DI_PT_LINE_ADJ" value="0xa"/> + <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/> + <value name="DI_PT_TRI_ADJ" value="0xc"/> + <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/> + <value name="DI_PT_PATCHES" value="0x29"/> +</enum> + +<enum name="pc_di_src_sel"> + <value name="DI_SRC_SEL_DMA" value="0"/> + <value name="DI_SRC_SEL_IMMEDIATE" value="1"/> + <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/> + <value name="DI_SRC_SEL_RESERVED" value="3"/> +</enum> + +<enum name="pc_di_face_cull_sel"> + <value name="DI_FACE_CULL_NONE" value="0"/> + <value name="DI_FACE_CULL_FETCH" value="1"/> + <value name="DI_FACE_BACKFACE_CULL" value="2"/> + <value name="DI_FACE_FRONTFACE_CULL" value="3"/> +</enum> + +<enum name="pc_di_index_size"> + <value name="INDEX_SIZE_IGN" value="0"/> + <value name="INDEX_SIZE_16_BIT" value="0"/> + <value name="INDEX_SIZE_32_BIT" value="1"/> + <value name="INDEX_SIZE_8_BIT" value="2"/> + <value name="INDEX_SIZE_INVALID"/> +</enum> + +<enum name="pc_di_vis_cull_mode"> + <value name="IGNORE_VISIBILITY" value="0"/> + <value name="USE_VISIBILITY" value="1"/> +</enum> + +<enum name="adreno_pm4_packet_type"> + <value name="CP_TYPE0_PKT" value="0x00000000"/> + <value name="CP_TYPE1_PKT" value="0x40000000"/> + <value name="CP_TYPE2_PKT" value="0x80000000"/> + <value name="CP_TYPE3_PKT" value="0xc0000000"/> + <value name="CP_TYPE4_PKT" value="0x40000000"/> + <value name="CP_TYPE7_PKT" value="0x70000000"/> +</enum> + +<!-- + Note that in some cases, the same packet id is recycled on a later + generation, so variants attribute is used to distinguish. They + may not be completely accurate, we would probably have to analyze + the pfp and me/pm4 firmware to verify the packet is actually + handled on a particular generation. But it is at least enough to + disambiguate the packet-id's that were re-used for different + packets starting with a5xx. + --> +<enum name="adreno_pm4_type3_packets"> + <doc>initialize CP's micro-engine</doc> + <value name="CP_ME_INIT" value="0x48"/> + <doc>skip N 32-bit words to get to the next packet</doc> + <value name="CP_NOP" value="0x10"/> + <doc> + indirect buffer dispatch. prefetch parser uses this packet + type to determine whether to pre-fetch the IB + </doc> + <value name="CP_PREEMPT_ENABLE" value="0x1c"/> + <value name="CP_PREEMPT_TOKEN" value="0x1e"/> + <value name="CP_INDIRECT_BUFFER" value="0x3f"/> + <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc> + <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/> + <doc>wait for the IDLE state of the engine</doc> + <value name="CP_WAIT_FOR_IDLE" value="0x26"/> + <doc>wait until a register or memory location is a specific value</doc> + <value name="CP_WAIT_REG_MEM" value="0x3c"/> + <doc>wait until a register location is equal to a specific value</doc> + <value name="CP_WAIT_REG_EQ" value="0x52"/> + <doc>wait until a register location is >= a specific value</doc> + <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/> + <doc>wait until a read completes</doc> + <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/> + <doc>wait until all base/size writes from an IB_PFD packet have completed</doc> + <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/> + <doc>register read/modify/write</doc> + <value name="CP_REG_RMW" value="0x21"/> + <doc>Set binning configuration registers</doc> + <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/> + <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/> + <doc>reads register in chip and writes to memory</doc> + <value name="CP_REG_TO_MEM" value="0x3e"/> + <doc>write N 32-bit words to memory</doc> + <value name="CP_MEM_WRITE" value="0x3d"/> + <doc>write CP_PROG_COUNTER value to memory</doc> + <value name="CP_MEM_WRITE_CNTR" value="0x4f"/> + <doc>conditional execution of a sequence of packets</doc> + <value name="CP_COND_EXEC" value="0x44"/> + <doc>conditional write to memory or register</doc> + <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/> + <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/> + <doc>generate an event that creates a write to memory when completed</doc> + <value name="CP_EVENT_WRITE" value="0x46"/> + <doc>generate a VS|PS_done event</doc> + <value name="CP_EVENT_WRITE_SHD" value="0x58"/> + <doc>generate a cache flush done event</doc> + <value name="CP_EVENT_WRITE_CFL" value="0x59"/> + <doc>generate a z_pass done event</doc> + <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/> + <doc> + not sure the real name, but this seems to be what is used for + opencl, instead of CP_DRAW_INDX.. + </doc> + <value name="CP_RUN_OPENCL" value="0x31"/> + <doc>initiate fetch of index buffer and draw</doc> + <value name="CP_DRAW_INDX" value="0x22"/> + <doc>draw using supplied indices in packet</doc> + <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/> <!-- this is something different on a6xx and unused on a5xx --> + <doc>initiate fetch of index buffer and binIDs and draw</doc> + <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/> + <doc>initiate fetch of bin IDs and draw using supplied indices</doc> + <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/> + <doc>begin/end initiator for viz query extent processing</doc> + <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/> + <doc>fetch state sub-blocks and initiate shader code DMAs</doc> + <value name="CP_SET_STATE" value="0x25"/> + <doc>load constant into chip and to memory</doc> + <value name="CP_SET_CONSTANT" value="0x2d"/> + <doc>load sequencer instruction memory (pointer-based)</doc> + <value name="CP_IM_LOAD" value="0x27"/> + <doc>load sequencer instruction memory (code embedded in packet)</doc> + <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/> + <doc>load constants from a location in memory</doc> + <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e"/> + <doc>selective invalidation of state pointers</doc> + <value name="CP_INVALIDATE_STATE" value="0x3b"/> + <doc>dynamically changes shader instruction memory partition</doc> + <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/> + <doc>sets the 64-bit BIN_MASK register in the PFP</doc> + <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/> + <doc>sets the 64-bit BIN_SELECT register in the PFP</doc> + <value name="CP_SET_BIN_SELECT" value="0x51"/> + <doc>updates the current context, if needed</doc> + <value name="CP_CONTEXT_UPDATE" value="0x5e"/> + <doc>generate interrupt from the command stream</doc> + <value name="CP_INTERRUPT" value="0x40"/> + <doc>copy sequencer instruction memory to system memory</doc> + <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/> + + <!-- For a20x --> +<!-- TODO handle variants.. + <doc> + Program an offset that will added to the BIN_BASE value of + the 3D_DRAW_INDX_BIN packet + </doc> + <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/> + --> + + <!-- for a22x --> + <doc> + sets draw initiator flags register in PFP, gets bitwise-ORed into + every draw initiator + </doc> + <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/> + <doc>sets the register protection mode</doc> + <value name="CP_SET_PROTECTED_MODE" value="0x5f"/> + + <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/> + + <!-- for a3xx --> + <doc>load high level sequencer command</doc> + <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/> + <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/> + <doc>Conditionally load a IB based on a flag, prefetch enabled</doc> + <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/> + <doc>Conditionally load a IB based on a flag, prefetch disabled</doc> + <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/> + <doc>Load a buffer with pre-fetch enabled</doc> + <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/> + <doc>Set bin (?)</doc> + <value name="CP_SET_BIN" value="0x4c"/> + + <doc>test 2 memory locations to dword values specified</doc> + <value name="CP_TEST_TWO_MEMS" value="0x71"/> + + <doc>Write register, ignoring context state for context sensitive registers</doc> + <value name="CP_REG_WR_NO_CTXT" value="0x78"/> + + <doc>Record the real-time when this packet is processed by PFP</doc> + <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/> + + <!-- Used to switch GPU between secure and non-secure modes --> + <value name="CP_SET_SECURE_MODE" value="0x66"/> + + <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc> + <value name="CP_WAIT_FOR_ME" value="0x13"/> + + <!-- for a4xx --> + <doc> + Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple + groups of registers. Looks like it can be used to create state + objects in GPU memory, and on state change only emit pointer + (via CP_SET_DRAW_STATE), which should be nice for reducing CPU + overhead: + + (A4x) save PM4 stream pointers to execute upon a visible draw + </doc> + <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/> + <value name="CP_DRAW_INDX_OFFSET" value="0x38"/> + <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/> + <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/> + <value name="CP_DRAW_AUTO" value="0x24"/> + + <value name="CP_UNKNOWN_19" value="0x19"/> + + <doc>set to 1 for fastclear..:</doc> + <value name="CP_UNKNOWN_1A" value="0x1a"/> + + <value name="CP_UNKNOWN_4E" value="0x4e"/> + + <doc> + for A4xx + Write to register with address that does not fit into type-0 pkt + </doc> + <value name="CP_WIDE_REG_WRITE" value="0x74"/> + + <doc>copy from ME scratch RAM to a register</doc> + <value name="CP_SCRATCH_TO_REG" value="0x4d"/> + + <doc>Copy from REG to ME scratch RAM</doc> + <value name="CP_REG_TO_SCRATCH" value="0x4a"/> + + <doc>Wait for memory writes to complete</doc> + <value name="CP_WAIT_MEM_WRITES" value="0x12"/> + + <doc>Conditional execution based on register comparison</doc> + <value name="CP_COND_REG_EXEC" value="0x47"/> + + <doc>Memory to REG copy</doc> + <value name="CP_MEM_TO_REG" value="0x42"/> + + <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/> + <value name="CP_EXEC_CS" value="0x33"/> + + <doc> + for a5xx + </doc> + <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/> + <!-- switches SMMU pagetable, used on a5xx only --> + <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/> + <!-- for a6xx --> + <doc>Tells CP the current mode of GPU operation</doc> + <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/> + <doc>Instruct CP to set a few internal CP registers</doc> + <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/> + <!-- + pairs of regid and value.. seems to be used to program some TF + related regs: + --> + <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/> + <!-- A5XX Enable yield in RB only --> + <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/> + <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/> + <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/> + <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/> + <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/> + <!-- Enable/Disable/Defer A5x global preemption model --> + <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/> + <!-- Enable/Disable A5x local preemption model --> + <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/> + <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx --> + <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/> + <!-- Inform CP about current render mode (needed for a5xx preemption) --> + <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/> + <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/> + <!-- check if this works on earlier.. --> + <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/> + <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/> + + <!-- Test specified bit in specified register and set predicate --> + <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/> + + <!-- + Seems to set the mode flags which control which CP_SET_DRAW_STATE + packets are executed, based on their ENABLE_MASK values + + CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE + packets w/ ENABLE_MASK & 0x6 to execute immediately + --> + <value name="CP_SET_MODE" value="0x63" variants="A6XX"/> + + <!-- + Seems like there are now separate blocks of state for VS vs FS/CS + (probably these amounts to geometry vs fragments so that geometry + stage of the pipeline for next draw can start while fragment stage + of current draw is still running. The format of the payload of the + packets is the same, the only difference is the offsets of the regs + the firmware code that handles the packet writes. + + Note that for CL, starting with a6xx, the preferred # of local + threads is no longer the same as the max, implying that the shader + core can now run warps from unrelated shaders (ie. + CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs + CL_KERNEL_WORK_GROUP_SIZE) + --> + <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/> + <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/> + <!-- + Note: For IBO state (Image/SSBOs) which have shared state across + shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for + compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are + interchangable. + --> + <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/> + + <!-- internal packets: --> + <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/> + <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/> + <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/> + <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/> + <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/> + <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/> + <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/> + <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/> + + <!-- jmptable entry used to handle type4 packet on a5xx+: --> + <value name="PKT4" value="0x04" variants="A5XX,A6XX"/> +<!-- +unknown a6xx opcodes: + +opcode: (null) (14) (5 dwords) +opcode: (null) (55) (4 dwords) +opcode: (null) (6d) (4 dwords) + --> + <value name="CP_UNK_A6XX_14" value="0x14" variants="A6XX"/> + <value name="CP_UNK_A6XX_55" value="0x55" variants="A6XX"/> + + <!-- + Seems to always have the payload: + 00000002 00008801 00004010 + or: + 00000002 00008801 00004090 + or: + 00000002 00008801 00000010 + 00000002 00008801 00010010 + 00000002 00008801 00d64010 + ... + Note set for compute shaders.. + Is 0x8801 a register offset? + This appears to be a special sort of register write packet + more or less, but the firmware has some special handling.. + Seems like it intercepts/modifies certain register offsets, + but others are treated like a normal PKT4 reg write. I + guess there are some registers that the fw controls certain + bits. + --> + <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/> + +</enum> + + +<domain name="CP_LOAD_STATE" width="32"> + <doc>Load state, a3xx (and later?)</doc> + <enum name="adreno_state_block"> + <value name="SB_VERT_TEX" value="0"/> + <value name="SB_VERT_MIPADDR" value="1"/> + <value name="SB_FRAG_TEX" value="2"/> + <value name="SB_FRAG_MIPADDR" value="3"/> + <value name="SB_VERT_SHADER" value="4"/> + <value name="SB_GEOM_SHADER" value="5"/> + <value name="SB_FRAG_SHADER" value="6"/> + <value name="SB_COMPUTE_SHADER" value="7"/> + </enum> + <enum name="adreno_state_type"> + <value name="ST_SHADER" value="0"/> + <value name="ST_CONSTANTS" value="1"/> + </enum> + <enum name="adreno_state_src"> + <value name="SS_DIRECT" value="0"> + <doc>inline with the CP_LOAD_STATE packet</doc> + </value> + <value name="SS_INVALID_ALL_IC" value="2"/> + <value name="SS_INVALID_PART_IC" value="3"/> + <value name="SS_INDIRECT" value="4"> + <doc>in buffer pointed to by EXT_SRC_ADDR</doc> + </value> + <value name="SS_INDIRECT_TCM" value="5"/> + <value name="SS_INDIRECT_STM" value="6"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="DST_OFF" low="0" high="15" type="uint"/> + <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/> + <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/> + <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/> + <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> + </reg32> +</domain> + +<domain name="CP_LOAD_STATE4" width="32" varset="chip"> + <doc>Load state, a4xx+</doc> + <enum name="a4xx_state_block"> + <!-- + unknown: 0x7 and 0xf <- seen in compute shader + + STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption? + Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains + the gpuaddr of the following shader constants block. DST_OFF seems + to specify which shader stage: + + 16 -> vert + 36 -> tcs + 56 -> tes + 76 -> geom + 96 -> frag + + Example: + +opcode: CP_LOAD_STATE4 (30) (12 dwords) + { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } + { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 } + { EXT_SRC_ADDR_HI = 0 } + 0000: c0264100 00000000 00000000 00000000 + 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000 + +opcode: CP_LOAD_STATE4 (30) (4 dwords) + { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 } + { EXT_SRC_ADDR_HI = 0 } + 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 + 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 + 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000 + + STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords. + + --> + <value name="SB4_VS_TEX" value="0x0"/> + <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS --> + <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES --> + <value name="SB4_GS_TEX" value="0x3"/> + <value name="SB4_FS_TEX" value="0x4"/> + <value name="SB4_CS_TEX" value="0x5"/> + <value name="SB4_VS_SHADER" value="0x8"/> + <value name="SB4_HS_SHADER" value="0x9"/> + <value name="SB4_DS_SHADER" value="0xa"/> + <value name="SB4_GS_SHADER" value="0xb"/> + <value name="SB4_FS_SHADER" value="0xc"/> + <value name="SB4_CS_SHADER" value="0xd"/> + <!-- + for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each), + STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each) + + Compute has it's own dedicated SSBO state, it seems, but the rest + of the stages share state + --> + <value name="SB4_SSBO" value="0xe"/> + <value name="SB4_CS_SSBO" value="0xf"/> + </enum> + <enum name="a4xx_state_type"> + <value name="ST4_SHADER" value="0"/> + <value name="ST4_CONSTANTS" value="1"/> + <value name="ST4_UBO" value="2"/> + </enum> + <enum name="a4xx_state_src"> + <value name="SS4_DIRECT" value="0"/> + <value name="SS4_INDIRECT" value="2"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="DST_OFF" low="0" high="13" type="uint"/> + <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/> + <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/> + <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/> + <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> + </reg32> + <reg32 offset="2" name="2" variants="A5XX-"> + <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> + </reg32> +</domain> + +<!-- looks basically same CP_LOAD_STATE4 --> +<domain name="CP_LOAD_STATE6" width="32" varset="chip"> + <doc>Load state, a6xx+</doc> + <enum name="a6xx_state_block"> + <value name="SB6_VS_TEX" value="0x0"/> + <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS --> + <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES --> + <value name="SB6_GS_TEX" value="0x3"/> + <value name="SB6_FS_TEX" value="0x4"/> + <value name="SB6_CS_TEX" value="0x5"/> + <value name="SB6_VS_SHADER" value="0x8"/> + <value name="SB6_HS_SHADER" value="0x9"/> + <value name="SB6_DS_SHADER" value="0xa"/> + <value name="SB6_GS_SHADER" value="0xb"/> + <value name="SB6_FS_SHADER" value="0xc"/> + <value name="SB6_CS_SHADER" value="0xd"/> + <value name="SB6_IBO" value="0xe"/> + <value name="SB6_CS_IBO" value="0xf"/> + </enum> + <enum name="a6xx_state_type"> + <value name="ST6_SHADER" value="0"/> + <value name="ST6_CONSTANTS" value="1"/> + <value name="ST6_UBO" value="2"/> + <value name="ST6_IBO" value="3"/> + </enum> + <enum name="a6xx_state_src"> + <value name="SS6_DIRECT" value="0"/> + <value name="SS6_INDIRECT" value="2"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="DST_OFF" low="0" high="13" type="uint"/> + <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/> + <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/> + <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/> + <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> + </reg32> +</domain> + +<bitset name="vgt_draw_initiator" inline="yes"> + <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> + <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> + <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/> + <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/> + <bitfield name="NOT_EOP" pos="12" type="boolean"/> + <bitfield name="SMALL_INDEX" pos="13" type="boolean"/> + <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/> + <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/> +</bitset> + +<!-- changed on a4xx: --> +<enum name="a4xx_index_size"> + <value name="INDEX4_SIZE_8_BIT" value="0"/> + <value name="INDEX4_SIZE_16_BIT" value="1"/> + <value name="INDEX4_SIZE_32_BIT" value="2"/> +</enum> + +<enum name="a6xx_patch_type"> + <value name="TESS_QUADS" value="0"/> + <value name="TESS_TRIANGLES" value="1"/> + <value name="TESS_ISOLINES" value="2"/> +</enum> + +<bitset name="vgt_draw_initiator_a4xx" inline="yes"> + <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 --> + <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> + <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> + <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/> + <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/> + <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/> + <bitfield name="TESS_ENABLE" pos="17" type="boolean"/> +</bitset> + +<domain name="CP_DRAW_INDX" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="VIZ_QUERY" low="0" high="31"/> + </reg32> + <reg32 offset="1" name="1" type="vgt_draw_initiator"/> + <reg32 offset="2" name="2"> + <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="INDX_BASE" low="0" high="31"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="INDX_SIZE" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_DRAW_INDX_2" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="VIZ_QUERY" low="0" high="31"/> + </reg32> + <reg32 offset="1" name="1" type="vgt_draw_initiator"/> + <reg32 offset="2" name="2"> + <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> + </reg32> + <!-- followed by NUM_INDICES indices.. --> +</domain> + +<domain name="CP_DRAW_INDX_OFFSET" width="32"> + <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> + <reg32 offset="1" name="1"> + <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="3" name="3"> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="INDX_BASE" low="0" high="31"/> + </reg32> + <reg32 offset="5" name="5"> + <bitfield name="INDX_SIZE" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> + <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> + <reg32 offset="1" name="1"> + <bitfield name="INDIRECT" low="0" high="31"/> + </reg32> + <stripe variants="A5XX-"> + <reg32 offset="2" name="2"> + <bitfield name="INDIRECT_HI" low="0" high="31"/> + </reg32> + </stripe> +</domain> + +<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> + <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> + <stripe variants="A4XX"> + <reg32 offset="1" name="1"> + <bitfield name="INDX_BASE" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + <!-- max # of bytes in index buffer --> + <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="INDIRECT" low="0" high="31"/> + </reg32> + </stripe> + <stripe variants="A5XX-"> + <reg32 offset="1" name="1"> + <bitfield name="INDX_BASE_LO" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="INDX_BASE_HI" low="0" high="31"/> + </reg32> + <reg32 offset="3" name="3"> + <!-- max # of elements in index buffer --> + <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="INDIRECT_LO" low="0" high="31"/> + </reg32> + <reg32 offset="5" name="5"> + <bitfield name="INDIRECT_HI" low="0" high="31"/> + </reg32> + </stripe> +</domain> + +<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-"> + <array offset="0" name="" stride="3" length="100"> + <reg32 offset="0" name="0"> + <bitfield name="COUNT" low="0" high="15" type="uint"/> + <bitfield name="DIRTY" pos="16" type="boolean"/> + <bitfield name="DISABLE" pos="17" type="boolean"/> + <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/> + <bitfield name="LOAD_IMMED" pos="19" type="boolean"/> + <!-- + I think this is a bitmask of states that this group applies to + (ie. binning/bypass/gmem)? At least starting w/ a6xx blob + emits different VS state at the same time, with ENABLE_MASK=0x1 + for binning pass VS state, and ENABLE_MASK=0x6 for full VS. + --> + <bitfield name="ENABLE_MASK" low="20" high="23" variants="A6XX-"/> + <bitfield name="GROUP_ID" low="24" high="28" type="uint"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="ADDR_LO" low="0" high="31" type="hex"/> + </reg32> + <reg32 offset="2" name="2" variants="A5XX-"> + <bitfield name="ADDR_HI" low="0" high="31" type="hex"/> + </reg32> + </array> +</domain> + +<domain name="CP_SET_BIN" width="32"> + <doc>value at offset 0 always seems to be 0x00000000..</doc> + <reg32 offset="0" name="0"/> + <reg32 offset="1" name="1"> + <bitfield name="X1" low="0" high="15" type="uint"/> + <bitfield name="Y1" low="16" high="31" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="X2" low="0" high="15" type="uint"/> + <bitfield name="Y2" low="16" high="31" type="uint"/> + </reg32> +</domain> + +<domain name="CP_SET_BIN_DATA" width="32"> + <reg32 offset="0" name="0"> + <!-- corresponds to VSC_PIPE[n].DATA_ADDR --> + <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/> + </reg32> + <reg32 offset="1" name="1"> + <!-- seesm to correspond to VSC_SIZE_ADDRESS --> + <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_SET_BIN_DATA5" width="32"> + <reg32 offset="0" name="0"> + <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> + <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> + <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> + <bitfield name="VSC_N" low="22" high="26" type="uint"/> + </reg32> + <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> + <reg32 offset="1" name="1"> + <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> + </reg32> + <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> + <reg32 offset="3" name="3"> + <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> + </reg32> + <!-- what is this new address? --> + <reg32 offset="5" name="5"> + <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/> + </reg32> + <reg32 offset="6" name="6"> + <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_REG_TO_MEM" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="REG" low="0" high="15" type="hex"/> + <!-- + number of regsiters/dwords copied is CNT+1.. unsure + about # of bits + --> + <bitfield name="CNT" low="19" high="29" type="uint"/> + <bitfield name="64B" pos="30" type="boolean"/> + <bitfield name="ACCUMULATE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="DEST" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2" variants="A5XX-"> + <bitfield name="DEST_HI" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_MEM_TO_REG" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="REG" low="0" high="15" type="hex"/> + <!-- + number of regsiters/dwords copied is CNT+1.. unsure + about # of bits + --> + <bitfield name="CNT" low="19" high="29" type="uint"/> + <bitfield name="64B" pos="30" type="boolean"/> + <bitfield name="ACCUMULATE" pos="31" type="boolean"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="SRC" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2" variants="A5XX-"> + <bitfield name="SRC_HI" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_MEM_TO_MEM" width="32"> + <reg32 offset="0" name="0"> + <!-- + not sure how many src operands we have, but the low + bits negate the n'th src argument. + --> + <bitfield name="NEG_A" pos="0" type="boolean"/> + <bitfield name="NEG_B" pos="1" type="boolean"/> + <bitfield name="NEG_C" pos="2" type="boolean"/> + + <!-- if set treat src/dst as 64bit values --> + <bitfield name="DOUBLE" pos="29" type="boolean"/> + </reg32> + <!-- + followed by sequence of addresses.. the first is the + destination and the rest are N src addresses which are + summed (after being negated if NEG_x bit set) allowing + to do things like 'result += end - start' (which turns + out to be useful for queries and accumulating results + across multiple tiles) + --> +</domain> + +<enum name="cp_cond_function"> + <value value="0" name="WRITE_ALWAYS"/> + <value value="1" name="WRITE_LT"/> + <value value="2" name="WRITE_LE"/> + <value value="3" name="WRITE_EQ"/> + <value value="4" name="WRITE_NE"/> + <value value="5" name="WRITE_GE"/> + <value value="6" name="WRITE_GT"/> +</enum> + +<domain name="CP_COND_WRITE" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> + <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> + <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="REF" low="0" high="31"/> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="MASK" low="0" high="31"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/> + </reg32> + <reg32 offset="5" name="5"> + <bitfield name="WRITE_DATA" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_COND_WRITE5" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> + <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> + <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="REF" low="0" high="31"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="MASK" low="0" high="31"/> + </reg32> + <reg32 offset="5" name="5"> + <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/> + </reg32> + <reg32 offset="6" name="6"> + <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/> + </reg32> + <reg32 offset="7" name="7"> + <bitfield name="WRITE_DATA" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_DISPATCH_COMPUTE" width="32"> + <reg32 offset="0" name="0"/> + <reg32 offset="1" name="1"> + <bitfield name="X" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="Y" low="0" high="31"/> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="Z" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_SET_RENDER_MODE" width="32"> + <enum name="render_mode_cmd"> + <value value="1" name="BYPASS"/> + <value value="2" name="BINNING"/> + <value value="3" name="GMEM"/> + <value value="5" name="BLIT2D"/> + <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? --> + <value value="7" name="BLIT2DSCALE"/> + <!-- 8 set before going back to BYPASS exiting 2D --> + <value value="8" name="END2D"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/> + <!-- + normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in + 0x21xx range.. possibly (at least some) a5xx variants have a + 2d core? + --> + </reg32> + <!-- I think first buffer is for GPU to save context in case of ctx switch? --> + <reg32 offset="1" name="1"> + <bitfield name="ADDR_0_LO" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="ADDR_0_HI" low="0" high="31"/> + </reg32> + <reg32 offset="3" name="3"> + <!-- + set when in GMEM.. maybe indicates GMEM contents need to be + preserved on ctx switch? + --> + <bitfield name="VSC_ENABLE" pos="3" type="boolean"/> + <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/> + </reg32> + <reg32 offset="4" name="4"/> + <!-- second buffer looks like some cmdstream.. length in dwords: --> + <reg32 offset="5" name="5"> + <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="6" name="6"> + <bitfield name="ADDR_1_LO" low="0" high="31"/> + </reg32> + <reg32 offset="7" name="7"> + <bitfield name="ADDR_1_HI" low="0" high="31"/>" + </reg32> +</domain> + +<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword --> +<domain name="CP_COMPUTE_CHECKPOINT" width="32"> + <!-- I think first buffer is for GPU to save context in case of ctx switch? --> + <reg32 offset="0" name="0"> + <bitfield name="ADDR_0_LO" low="0" high="31"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="ADDR_0_HI" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + </reg32> + <!-- second buffer looks like some cmdstream.. length in dwords: --> + <reg32 offset="3" name="3"> + <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="4" name="4"/> + <reg32 offset="5" name="5"> + <bitfield name="ADDR_1_LO" low="0" high="31"/> + </reg32> + <reg32 offset="6" name="6"> + <bitfield name="ADDR_1_HI" low="0" high="31"/>" + </reg32> + <reg32 offset="7" name="7"/> +</domain> + +<domain name="CP_PERFCOUNTER_ACTION" width="32"> + <reg32 offset="0" name="0"> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="ADDR_0_LO" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="ADDR_0_HI" low="0" high="31"/> + </reg32> +</domain> + +<domain name="CP_EVENT_WRITE" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/> + <!-- when set, write back timestamp instead of value from packet: --> + <bitfield name="TIMESTAMP" pos="30" type="boolean"/> + </reg32> + <!-- + TODO what is gpuaddr for, seems to be all 0's.. maybe needed for + context switch? + --> + <reg32 offset="1" name="1"> + <bitfield name="ADDR_0_LO" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="ADDR_0_HI" low="0" high="31"/> + </reg32> + <reg32 offset="3" name="3"> + <!-- ??? --> + </reg32> +</domain> + +<domain name="CP_BLIT" width="32"> + <enum name="cp_blit_cmd"> + <value value="0" name="BLIT_OP_FILL"/> + <value value="1" name="BLIT_OP_COPY"/> + <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation --> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="SRC_X1" low="0" high="13" type="uint"/> + <bitfield name="SRC_Y1" low="16" high="29" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="SRC_X2" low="0" high="13" type="uint"/> + <bitfield name="SRC_Y2" low="16" high="29" type="uint"/> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="DST_X1" low="0" high="13" type="uint"/> + <bitfield name="DST_Y1" low="16" high="29" type="uint"/> + </reg32> + <reg32 offset="4" name="4"> + <bitfield name="DST_X2" low="0" high="13" type="uint"/> + <bitfield name="DST_Y2" low="16" high="29" type="uint"/> + </reg32> +</domain> + +<domain name="CP_EXEC_CS" width="32"> + <reg32 offset="0" name="0"> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/> + </reg32> + <reg32 offset="3" name="3"> + <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/> + </reg32> +</domain> + +<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> + <reg32 offset="0" name="0"> + </reg32> + <stripe variants="A4XX"> + <reg32 offset="1" name="1"> + <bitfield name="ADDR" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + <!-- localsize is value minus one: --> + <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> + <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> + <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> + </reg32> + </stripe> + <stripe variants="A5XX-"> + <reg32 offset="1" name="1"> + <bitfield name="ADDR_LO" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="ADDR_HI" low="0" high="31"/> + </reg32> + <reg32 offset="3" name="3"> + <!-- localsize is value minus one: --> + <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> + <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> + <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> + </reg32> + </stripe> +</domain> + +<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-"> + <doc>Tell CP the current operation mode, indicates save and restore procedure</doc> + <enum name="a6xx_render_mode"> + <value value="1" name="RM6_BYPASS"/> + <value value="2" name="RM6_BINNING"/> + <value value="4" name="RM6_GMEM"/> + <value value="5" name="RM6_BLIT2D"/> + <value value="6" name="RM6_RESOLVE"/> + <value value="0xc" name="RM6_BLIT2DSCALE"/> + </enum> + <reg32 offset="0" name="0"> + <bitfield name="MARKER" low="0" high="3"/> + <bitfield name="MODE" low="0" high="3" type="a6xx_render_mode"/> + <!-- IFPC - inter-frame power collapse --> + <bitfield name="IFPC" pos="8" type="boolean"/> + </reg32> +</domain> + +<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-"> + <doc>Set internal CP registers, used to indicate context save data addresses</doc> + <enum name="pseudo_reg"> + <value value="0" name="SMMU_INFO"/> + <value value="1" name="NON_SECURE_SAVE_ADDR"/> + <value value="2" name="SECURE_SAVE_ADDR"/> + <value value="3" name="NON_PRIV_SAVE_ADDR"/> + <value value="4" name="COUNTER"/> + </enum> + <array offset="0" name="" stride="3" length="100"> + <reg32 offset="0" name="0"> + <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="LO" low="0" high="31"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="HI" low="0" high="31"/> + </reg32> + </array> +</domain> + +<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-"> + <doc> + Tests bit in specified register and sets predicate for CP_COND_REG_EXEC. + So: + + opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0xc10 | BIT = 0 } + 0000: 70b90001 00000c10 + opcode: CP_COND_REG_EXEC (47) (3 dwords) + 0000: 70c70002 10000000 00000004 + opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + + Will execute the CP_INDIRECT_BUFFER only if b0 in the register at + offset 0x0c10 is 1 + </doc> + <reg32 offset="0" name="0"> + <!-- the register to test --> + <bitfield name="REG" low="0" high="11"/> + <!-- the bit to test --> + <bitfield name="BIT" low="20" high="24" type="uint"/> + <bitfield name="UNK25" pos="25" type="boolean"/> + </reg32> +</domain> + +</database> + diff --git a/src/freedreno/registers/adreno_pm4.xml.h b/src/freedreno/registers/adreno_pm4.xml.h deleted file mode 100644 index 629e8bfd24b..00000000000 --- a/src/freedreno/registers/adreno_pm4.xml.h +++ /dev/null @@ -1,1582 +0,0 @@ -#ifndef ADRENO_PM4_XML -#define ADRENO_PM4_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2019 by the following authors: -- Rob Clark <[email protected]> (robclark) -- Ilia Mirkin <[email protected]> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum vgt_event_type { - VS_DEALLOC = 0, - PS_DEALLOC = 1, - VS_DONE_TS = 2, - PS_DONE_TS = 3, - CACHE_FLUSH_TS = 4, - CONTEXT_DONE = 5, - CACHE_FLUSH = 6, - HLSQ_FLUSH = 7, - VIZQUERY_START = 7, - VIZQUERY_END = 8, - SC_WAIT_WC = 9, - RST_PIX_CNT = 13, - RST_VTX_CNT = 14, - TILE_FLUSH = 15, - STAT_EVENT = 16, - CACHE_FLUSH_AND_INV_TS_EVENT = 20, - ZPASS_DONE = 21, - CACHE_FLUSH_AND_INV_EVENT = 22, - PERFCOUNTER_START = 23, - PERFCOUNTER_STOP = 24, - VS_FETCH_DONE = 27, - FACENESS_FLUSH = 28, - FLUSH_SO_0 = 17, - FLUSH_SO_1 = 18, - FLUSH_SO_2 = 19, - FLUSH_SO_3 = 20, - PC_CCU_INVALIDATE_DEPTH = 24, - PC_CCU_INVALIDATE_COLOR = 25, - UNK_1C = 28, - UNK_1D = 29, - BLIT = 30, - UNK_25 = 37, - LRZ_FLUSH = 38, - UNK_2C = 44, - UNK_2D = 45, -}; - -enum pc_di_primtype { - DI_PT_NONE = 0, - DI_PT_POINTLIST_PSIZE = 1, - DI_PT_LINELIST = 2, - DI_PT_LINESTRIP = 3, - DI_PT_TRILIST = 4, - DI_PT_TRIFAN = 5, - DI_PT_TRISTRIP = 6, - DI_PT_LINELOOP = 7, - DI_PT_RECTLIST = 8, - DI_PT_POINTLIST = 9, - DI_PT_LINE_ADJ = 10, - DI_PT_LINESTRIP_ADJ = 11, - DI_PT_TRI_ADJ = 12, - DI_PT_TRISTRIP_ADJ = 13, - DI_PT_PATCHES = 41, -}; - -enum pc_di_src_sel { - DI_SRC_SEL_DMA = 0, - DI_SRC_SEL_IMMEDIATE = 1, - DI_SRC_SEL_AUTO_INDEX = 2, - DI_SRC_SEL_RESERVED = 3, -}; - -enum pc_di_face_cull_sel { - DI_FACE_CULL_NONE = 0, - DI_FACE_CULL_FETCH = 1, - DI_FACE_BACKFACE_CULL = 2, - DI_FACE_FRONTFACE_CULL = 3, -}; - -enum pc_di_index_size { - INDEX_SIZE_IGN = 0, - INDEX_SIZE_16_BIT = 0, - INDEX_SIZE_32_BIT = 1, - INDEX_SIZE_8_BIT = 2, - INDEX_SIZE_INVALID = 0, -}; - -enum pc_di_vis_cull_mode { - IGNORE_VISIBILITY = 0, - USE_VISIBILITY = 1, -}; - -enum adreno_pm4_packet_type { - CP_TYPE0_PKT = 0, - CP_TYPE1_PKT = 0x40000000, - CP_TYPE2_PKT = 0x80000000, - CP_TYPE3_PKT = 0xc0000000, - CP_TYPE4_PKT = 0x40000000, - CP_TYPE7_PKT = 0x70000000, -}; - -enum adreno_pm4_type3_packets { - CP_ME_INIT = 72, - CP_NOP = 16, - CP_PREEMPT_ENABLE = 28, - CP_PREEMPT_TOKEN = 30, - CP_INDIRECT_BUFFER = 63, - CP_INDIRECT_BUFFER_PFD = 55, - CP_WAIT_FOR_IDLE = 38, - CP_WAIT_REG_MEM = 60, - CP_WAIT_REG_EQ = 82, - CP_WAIT_REG_GTE = 83, - CP_WAIT_UNTIL_READ = 92, - CP_WAIT_IB_PFD_COMPLETE = 93, - CP_REG_RMW = 33, - CP_SET_BIN_DATA = 47, - CP_SET_BIN_DATA5 = 47, - CP_REG_TO_MEM = 62, - CP_MEM_WRITE = 61, - CP_MEM_WRITE_CNTR = 79, - CP_COND_EXEC = 68, - CP_COND_WRITE = 69, - CP_COND_WRITE5 = 69, - CP_EVENT_WRITE = 70, - CP_EVENT_WRITE_SHD = 88, - CP_EVENT_WRITE_CFL = 89, - CP_EVENT_WRITE_ZPD = 91, - CP_RUN_OPENCL = 49, - CP_DRAW_INDX = 34, - CP_DRAW_INDX_2 = 54, - CP_DRAW_INDX_BIN = 52, - CP_DRAW_INDX_2_BIN = 53, - CP_VIZ_QUERY = 35, - CP_SET_STATE = 37, - CP_SET_CONSTANT = 45, - CP_IM_LOAD = 39, - CP_IM_LOAD_IMMEDIATE = 43, - CP_LOAD_CONSTANT_CONTEXT = 46, - CP_INVALIDATE_STATE = 59, - CP_SET_SHADER_BASES = 74, - CP_SET_BIN_MASK = 80, - CP_SET_BIN_SELECT = 81, - CP_CONTEXT_UPDATE = 94, - CP_INTERRUPT = 64, - CP_IM_STORE = 44, - CP_SET_DRAW_INIT_FLAGS = 75, - CP_SET_PROTECTED_MODE = 95, - CP_BOOTSTRAP_UCODE = 111, - CP_LOAD_STATE = 48, - CP_LOAD_STATE4 = 48, - CP_COND_INDIRECT_BUFFER_PFE = 58, - CP_COND_INDIRECT_BUFFER_PFD = 50, - CP_INDIRECT_BUFFER_PFE = 63, - CP_SET_BIN = 76, - CP_TEST_TWO_MEMS = 113, - CP_REG_WR_NO_CTXT = 120, - CP_RECORD_PFP_TIMESTAMP = 17, - CP_SET_SECURE_MODE = 102, - CP_WAIT_FOR_ME = 19, - CP_SET_DRAW_STATE = 67, - CP_DRAW_INDX_OFFSET = 56, - CP_DRAW_INDIRECT = 40, - CP_DRAW_INDX_INDIRECT = 41, - CP_DRAW_AUTO = 36, - CP_UNKNOWN_19 = 25, - CP_UNKNOWN_1A = 26, - CP_UNKNOWN_4E = 78, - CP_WIDE_REG_WRITE = 116, - CP_SCRATCH_TO_REG = 77, - CP_REG_TO_SCRATCH = 74, - CP_WAIT_MEM_WRITES = 18, - CP_COND_REG_EXEC = 71, - CP_MEM_TO_REG = 66, - CP_EXEC_CS_INDIRECT = 65, - CP_EXEC_CS = 51, - CP_PERFCOUNTER_ACTION = 80, - CP_SMMU_TABLE_UPDATE = 83, - CP_SET_MARKER = 101, - CP_SET_PSEUDO_REG = 86, - CP_CONTEXT_REG_BUNCH = 92, - CP_YIELD_ENABLE = 28, - CP_SKIP_IB2_ENABLE_GLOBAL = 29, - CP_SKIP_IB2_ENABLE_LOCAL = 35, - CP_SET_SUBDRAW_SIZE = 53, - CP_SET_VISIBILITY_OVERRIDE = 100, - CP_PREEMPT_ENABLE_GLOBAL = 105, - CP_PREEMPT_ENABLE_LOCAL = 106, - CP_CONTEXT_SWITCH_YIELD = 107, - CP_SET_RENDER_MODE = 108, - CP_COMPUTE_CHECKPOINT = 110, - CP_MEM_TO_MEM = 115, - CP_BLIT = 44, - CP_REG_TEST = 57, - CP_SET_MODE = 99, - CP_LOAD_STATE6_GEOM = 50, - CP_LOAD_STATE6_FRAG = 52, - CP_LOAD_STATE6 = 54, - IN_IB_PREFETCH_END = 23, - IN_SUBBLK_PREFETCH = 31, - IN_INSTR_PREFETCH = 32, - IN_INSTR_MATCH = 71, - IN_CONST_PREFETCH = 73, - IN_INCR_UPDT_STATE = 85, - IN_INCR_UPDT_CONST = 86, - IN_INCR_UPDT_INSTR = 87, - PKT4 = 4, - CP_UNK_A6XX_14 = 20, - CP_UNK_A6XX_55 = 85, - CP_REG_WRITE = 109, -}; - -enum adreno_state_block { - SB_VERT_TEX = 0, - SB_VERT_MIPADDR = 1, - SB_FRAG_TEX = 2, - SB_FRAG_MIPADDR = 3, - SB_VERT_SHADER = 4, - SB_GEOM_SHADER = 5, - SB_FRAG_SHADER = 6, - SB_COMPUTE_SHADER = 7, -}; - -enum adreno_state_type { - ST_SHADER = 0, - ST_CONSTANTS = 1, -}; - -enum adreno_state_src { - SS_DIRECT = 0, - SS_INVALID_ALL_IC = 2, - SS_INVALID_PART_IC = 3, - SS_INDIRECT = 4, - SS_INDIRECT_TCM = 5, - SS_INDIRECT_STM = 6, -}; - -enum a4xx_state_block { - SB4_VS_TEX = 0, - SB4_HS_TEX = 1, - SB4_DS_TEX = 2, - SB4_GS_TEX = 3, - SB4_FS_TEX = 4, - SB4_CS_TEX = 5, - SB4_VS_SHADER = 8, - SB4_HS_SHADER = 9, - SB4_DS_SHADER = 10, - SB4_GS_SHADER = 11, - SB4_FS_SHADER = 12, - SB4_CS_SHADER = 13, - SB4_SSBO = 14, - SB4_CS_SSBO = 15, -}; - -enum a4xx_state_type { - ST4_SHADER = 0, - ST4_CONSTANTS = 1, - ST4_UBO = 2, -}; - -enum a4xx_state_src { - SS4_DIRECT = 0, - SS4_INDIRECT = 2, -}; - -enum a6xx_state_block { - SB6_VS_TEX = 0, - SB6_HS_TEX = 1, - SB6_DS_TEX = 2, - SB6_GS_TEX = 3, - SB6_FS_TEX = 4, - SB6_CS_TEX = 5, - SB6_VS_SHADER = 8, - SB6_HS_SHADER = 9, - SB6_DS_SHADER = 10, - SB6_GS_SHADER = 11, - SB6_FS_SHADER = 12, - SB6_CS_SHADER = 13, - SB6_IBO = 14, - SB6_CS_IBO = 15, -}; - -enum a6xx_state_type { - ST6_SHADER = 0, - ST6_CONSTANTS = 1, - ST6_UBO = 2, - ST6_IBO = 3, -}; - -enum a6xx_state_src { - SS6_DIRECT = 0, - SS6_INDIRECT = 2, -}; - -enum a4xx_index_size { - INDEX4_SIZE_8_BIT = 0, - INDEX4_SIZE_16_BIT = 1, - INDEX4_SIZE_32_BIT = 2, -}; - -enum a6xx_patch_type { - TESS_QUADS = 0, - TESS_TRIANGLES = 1, - TESS_ISOLINES = 2, -}; - -enum cp_cond_function { - WRITE_ALWAYS = 0, - WRITE_LT = 1, - WRITE_LE = 2, - WRITE_EQ = 3, - WRITE_NE = 4, - WRITE_GE = 5, - WRITE_GT = 6, -}; - -enum render_mode_cmd { - BYPASS = 1, - BINNING = 2, - GMEM = 3, - BLIT2D = 5, - BLIT2DSCALE = 7, - END2D = 8, -}; - -enum cp_blit_cmd { - BLIT_OP_FILL = 0, - BLIT_OP_COPY = 1, - BLIT_OP_SCALE = 3, -}; - -enum a6xx_render_mode { - RM6_BYPASS = 1, - RM6_BINNING = 2, - RM6_GMEM = 4, - RM6_BLIT2D = 5, - RM6_RESOLVE = 6, - RM6_BLIT2DSCALE = 12, -}; - -enum pseudo_reg { - SMMU_INFO = 0, - NON_SECURE_SAVE_ADDR = 1, - SECURE_SAVE_ADDR = 2, - NON_PRIV_SAVE_ADDR = 3, - COUNTER = 4, -}; - -#define REG_CP_LOAD_STATE_0 0x00000000 -#define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff -#define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 -static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) -{ - return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; -} -#define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 -#define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 -static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) -{ - return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; -} -#define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 -#define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 -static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) -{ - return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; -} -#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000 -#define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 -static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) -{ - return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; -} - -#define REG_CP_LOAD_STATE_1 0x00000001 -#define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 -#define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 -static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) -{ - return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; -} -#define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc -#define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 -static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; -} - -#define REG_CP_LOAD_STATE4_0 0x00000000 -#define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff -#define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0 -static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) -{ - return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK; -} -#define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000 -#define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16 -static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) -{ - return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK; -} -#define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000 -#define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18 -static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) -{ - return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK; -} -#define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000 -#define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22 -static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) -{ - return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK; -} - -#define REG_CP_LOAD_STATE4_1 0x00000001 -#define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003 -#define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0 -static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) -{ - return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK; -} -#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc -#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2 -static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; -} - -#define REG_CP_LOAD_STATE4_2 0x00000002 -#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff -#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0 -static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) -{ - return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK; -} - -#define REG_CP_LOAD_STATE6_0 0x00000000 -#define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff -#define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0 -static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val) -{ - return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK; -} -#define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000 -#define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14 -static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) -{ - return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK; -} -#define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000 -#define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16 -static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) -{ - return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK; -} -#define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000 -#define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18 -static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) -{ - return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK; -} -#define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000 -#define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22 -static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) -{ - return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK; -} - -#define REG_CP_LOAD_STATE6_1 0x00000001 -#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc -#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2 -static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) -{ - assert(!(val & 0x3)); - return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; -} - -#define REG_CP_LOAD_STATE6_2 0x00000002 -#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff -#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0 -static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) -{ - return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK; -} - -#define REG_CP_DRAW_INDX_0 0x00000000 -#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff -#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; -} - -#define REG_CP_DRAW_INDX_1 0x00000001 -#define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f -#define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; -} -#define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0 -#define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6 -static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; -} -#define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600 -#define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9 -static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; -} -#define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800 -#define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11 -static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) -{ - return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; -} -#define CP_DRAW_INDX_1_NOT_EOP 0x00001000 -#define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000 -#define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 -#define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000 -#define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24 -static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; -} - -#define REG_CP_DRAW_INDX_2 0x00000002 -#define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff -#define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; -} - -#define REG_CP_DRAW_INDX_3 0x00000003 -#define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff -#define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; -} - -#define REG_CP_DRAW_INDX_4 0x00000004 -#define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff -#define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; -} - -#define REG_CP_DRAW_INDX_2_0 0x00000000 -#define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff -#define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; -} - -#define REG_CP_DRAW_INDX_2_1 0x00000001 -#define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f -#define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; -} -#define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0 -#define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6 -static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; -} -#define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600 -#define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9 -static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; -} -#define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800 -#define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11 -static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) -{ - return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; -} -#define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000 -#define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000 -#define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 -#define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000 -#define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24 -static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; -} - -#define REG_CP_DRAW_INDX_2_2 0x00000002 -#define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff -#define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; -} - -#define REG_CP_DRAW_INDX_OFFSET_0 0x00000000 -#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f -#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0 -#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6 -static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300 -#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 -static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 -#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 -static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000 -#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT 12 -static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000 - -#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 -#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK; -} - -#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002 -#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; -} - -#define REG_CP_DRAW_INDX_OFFSET_3 0x00000003 - -#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 -#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; -} - -#define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 -#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; -} - -#define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000 -#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f -#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0 -static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 -#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6 -static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300 -#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8 -static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 -#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10 -static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 -#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT 12 -static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000 - -#define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001 -#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff -#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0 -static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; -} - - -#define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002 -#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff -#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0 -static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) -{ - return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK; -} - -#define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f -#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0 -static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6 -static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8 -static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10 -static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT 12 -static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000 - - -#define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 -#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff -#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0 -static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK; -} - -#define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 -#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff -#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0 -static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK; -} - -#define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 -#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff -#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0 -static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; -} - - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 -#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 -static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 -#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0 -static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 -#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0 -static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004 -#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0 -static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005 -#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0 -static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK; -} - -static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } - -static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } -#define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff -#define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0 -static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) -{ - return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK; -} -#define CP_SET_DRAW_STATE__0_DIRTY 0x00010000 -#define CP_SET_DRAW_STATE__0_DISABLE 0x00020000 -#define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000 -#define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000 -#define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK 0x00f00000 -#define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT 20 -static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val) -{ - return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK; -} -#define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000 -#define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24 -static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) -{ - return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK; -} - -static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } -#define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff -#define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0 -static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) -{ - return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK; -} - -static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } -#define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff -#define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0 -static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) -{ - return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK; -} - -#define REG_CP_SET_BIN_0 0x00000000 - -#define REG_CP_SET_BIN_1 0x00000001 -#define CP_SET_BIN_1_X1__MASK 0x0000ffff -#define CP_SET_BIN_1_X1__SHIFT 0 -static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) -{ - return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; -} -#define CP_SET_BIN_1_Y1__MASK 0xffff0000 -#define CP_SET_BIN_1_Y1__SHIFT 16 -static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) -{ - return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; -} - -#define REG_CP_SET_BIN_2 0x00000002 -#define CP_SET_BIN_2_X2__MASK 0x0000ffff -#define CP_SET_BIN_2_X2__SHIFT 0 -static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) -{ - return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; -} -#define CP_SET_BIN_2_Y2__MASK 0xffff0000 -#define CP_SET_BIN_2_Y2__SHIFT 16 -static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) -{ - return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; -} - -#define REG_CP_SET_BIN_DATA_0 0x00000000 -#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff -#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0 -static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; -} - -#define REG_CP_SET_BIN_DATA_1 0x00000001 -#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff -#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0 -static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; -} - -#define REG_CP_SET_BIN_DATA5_0 0x00000000 -#define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000 -#define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16 -static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK; -} -#define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000 -#define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22 -static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK; -} - -#define REG_CP_SET_BIN_DATA5_1 0x00000001 -#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff -#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0 -static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK; -} - -#define REG_CP_SET_BIN_DATA5_2 0x00000002 -#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff -#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0 -static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK; -} - -#define REG_CP_SET_BIN_DATA5_3 0x00000003 -#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff -#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0 -static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK; -} - -#define REG_CP_SET_BIN_DATA5_4 0x00000004 -#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff -#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0 -static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK; -} - -#define REG_CP_SET_BIN_DATA5_5 0x00000005 -#define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK 0xffffffff -#define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT 0 -static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK; -} - -#define REG_CP_SET_BIN_DATA5_6 0x00000006 -#define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK 0xffffffff -#define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT 0 -static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val) -{ - return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK; -} - -#define REG_CP_REG_TO_MEM_0 0x00000000 -#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff -#define CP_REG_TO_MEM_0_REG__SHIFT 0 -static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) -{ - return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK; -} -#define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000 -#define CP_REG_TO_MEM_0_CNT__SHIFT 19 -static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) -{ - return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK; -} -#define CP_REG_TO_MEM_0_64B 0x40000000 -#define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000 - -#define REG_CP_REG_TO_MEM_1 0x00000001 -#define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff -#define CP_REG_TO_MEM_1_DEST__SHIFT 0 -static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) -{ - return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; -} - -#define REG_CP_REG_TO_MEM_2 0x00000002 -#define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff -#define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0 -static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val) -{ - return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK; -} - -#define REG_CP_MEM_TO_REG_0 0x00000000 -#define CP_MEM_TO_REG_0_REG__MASK 0x0000ffff -#define CP_MEM_TO_REG_0_REG__SHIFT 0 -static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val) -{ - return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK; -} -#define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000 -#define CP_MEM_TO_REG_0_CNT__SHIFT 19 -static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val) -{ - return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK; -} -#define CP_MEM_TO_REG_0_64B 0x40000000 -#define CP_MEM_TO_REG_0_ACCUMULATE 0x80000000 - -#define REG_CP_MEM_TO_REG_1 0x00000001 -#define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff -#define CP_MEM_TO_REG_1_SRC__SHIFT 0 -static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val) -{ - return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK; -} - -#define REG_CP_MEM_TO_REG_2 0x00000002 -#define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff -#define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0 -static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val) -{ - return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK; -} - -#define REG_CP_MEM_TO_MEM_0 0x00000000 -#define CP_MEM_TO_MEM_0_NEG_A 0x00000001 -#define CP_MEM_TO_MEM_0_NEG_B 0x00000002 -#define CP_MEM_TO_MEM_0_NEG_C 0x00000004 -#define CP_MEM_TO_MEM_0_DOUBLE 0x20000000 - -#define REG_CP_COND_WRITE_0 0x00000000 -#define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007 -#define CP_COND_WRITE_0_FUNCTION__SHIFT 0 -static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) -{ - return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK; -} -#define CP_COND_WRITE_0_POLL_MEMORY 0x00000010 -#define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100 - -#define REG_CP_COND_WRITE_1 0x00000001 -#define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff -#define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0 -static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val) -{ - return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK; -} - -#define REG_CP_COND_WRITE_2 0x00000002 -#define CP_COND_WRITE_2_REF__MASK 0xffffffff -#define CP_COND_WRITE_2_REF__SHIFT 0 -static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val) -{ - return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK; -} - -#define REG_CP_COND_WRITE_3 0x00000003 -#define CP_COND_WRITE_3_MASK__MASK 0xffffffff -#define CP_COND_WRITE_3_MASK__SHIFT 0 -static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val) -{ - return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK; -} - -#define REG_CP_COND_WRITE_4 0x00000004 -#define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff -#define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0 -static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) -{ - return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK; -} - -#define REG_CP_COND_WRITE_5 0x00000005 -#define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff -#define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0 -static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val) -{ - return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK; -} - -#define REG_CP_COND_WRITE5_0 0x00000000 -#define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007 -#define CP_COND_WRITE5_0_FUNCTION__SHIFT 0 -static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) -{ - return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK; -} -#define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010 -#define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100 - -#define REG_CP_COND_WRITE5_1 0x00000001 -#define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff -#define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0 -static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) -{ - return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK; -} - -#define REG_CP_COND_WRITE5_2 0x00000002 -#define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff -#define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0 -static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) -{ - return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK; -} - -#define REG_CP_COND_WRITE5_3 0x00000003 -#define CP_COND_WRITE5_3_REF__MASK 0xffffffff -#define CP_COND_WRITE5_3_REF__SHIFT 0 -static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val) -{ - return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK; -} - -#define REG_CP_COND_WRITE5_4 0x00000004 -#define CP_COND_WRITE5_4_MASK__MASK 0xffffffff -#define CP_COND_WRITE5_4_MASK__SHIFT 0 -static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val) -{ - return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK; -} - -#define REG_CP_COND_WRITE5_5 0x00000005 -#define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff -#define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0 -static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) -{ - return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK; -} - -#define REG_CP_COND_WRITE5_6 0x00000006 -#define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff -#define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0 -static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) -{ - return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK; -} - -#define REG_CP_COND_WRITE5_7 0x00000007 -#define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff -#define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0 -static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) -{ - return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK; -} - -#define REG_CP_DISPATCH_COMPUTE_0 0x00000000 - -#define REG_CP_DISPATCH_COMPUTE_1 0x00000001 -#define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff -#define CP_DISPATCH_COMPUTE_1_X__SHIFT 0 -static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) -{ - return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; -} - -#define REG_CP_DISPATCH_COMPUTE_2 0x00000002 -#define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff -#define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0 -static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) -{ - return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; -} - -#define REG_CP_DISPATCH_COMPUTE_3 0x00000003 -#define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff -#define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0 -static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) -{ - return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; -} - -#define REG_CP_SET_RENDER_MODE_0 0x00000000 -#define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff -#define CP_SET_RENDER_MODE_0_MODE__SHIFT 0 -static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) -{ - return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK; -} - -#define REG_CP_SET_RENDER_MODE_1 0x00000001 -#define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff -#define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0 -static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) -{ - return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; -} - -#define REG_CP_SET_RENDER_MODE_2 0x00000002 -#define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff -#define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0 -static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) -{ - return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; -} - -#define REG_CP_SET_RENDER_MODE_3 0x00000003 -#define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008 -#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010 - -#define REG_CP_SET_RENDER_MODE_4 0x00000004 - -#define REG_CP_SET_RENDER_MODE_5 0x00000005 -#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff -#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0 -static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) -{ - return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; -} - -#define REG_CP_SET_RENDER_MODE_6 0x00000006 -#define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff -#define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0 -static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) -{ - return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; -} - -#define REG_CP_SET_RENDER_MODE_7 0x00000007 -#define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff -#define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0 -static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) -{ - return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000 -#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0 -static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001 -#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0 -static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002 - -#define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003 -#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0 -static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004 - -#define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005 -#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0 -static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006 -#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0 -static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007 - -#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000 - -#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001 -#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff -#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0 -static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) -{ - return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK; -} - -#define REG_CP_PERFCOUNTER_ACTION_2 0x00000002 -#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff -#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0 -static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) -{ - return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK; -} - -#define REG_CP_EVENT_WRITE_0 0x00000000 -#define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff -#define CP_EVENT_WRITE_0_EVENT__SHIFT 0 -static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) -{ - return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK; -} -#define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000 - -#define REG_CP_EVENT_WRITE_1 0x00000001 -#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff -#define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0 -static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) -{ - return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK; -} - -#define REG_CP_EVENT_WRITE_2 0x00000002 -#define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff -#define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0 -static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) -{ - return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK; -} - -#define REG_CP_EVENT_WRITE_3 0x00000003 - -#define REG_CP_BLIT_0 0x00000000 -#define CP_BLIT_0_OP__MASK 0x0000000f -#define CP_BLIT_0_OP__SHIFT 0 -static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) -{ - return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK; -} - -#define REG_CP_BLIT_1 0x00000001 -#define CP_BLIT_1_SRC_X1__MASK 0x00003fff -#define CP_BLIT_1_SRC_X1__SHIFT 0 -static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) -{ - return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK; -} -#define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000 -#define CP_BLIT_1_SRC_Y1__SHIFT 16 -static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) -{ - return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK; -} - -#define REG_CP_BLIT_2 0x00000002 -#define CP_BLIT_2_SRC_X2__MASK 0x00003fff -#define CP_BLIT_2_SRC_X2__SHIFT 0 -static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) -{ - return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK; -} -#define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000 -#define CP_BLIT_2_SRC_Y2__SHIFT 16 -static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) -{ - return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK; -} - -#define REG_CP_BLIT_3 0x00000003 -#define CP_BLIT_3_DST_X1__MASK 0x00003fff -#define CP_BLIT_3_DST_X1__SHIFT 0 -static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) -{ - return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK; -} -#define CP_BLIT_3_DST_Y1__MASK 0x3fff0000 -#define CP_BLIT_3_DST_Y1__SHIFT 16 -static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) -{ - return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK; -} - -#define REG_CP_BLIT_4 0x00000004 -#define CP_BLIT_4_DST_X2__MASK 0x00003fff -#define CP_BLIT_4_DST_X2__SHIFT 0 -static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) -{ - return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK; -} -#define CP_BLIT_4_DST_Y2__MASK 0x3fff0000 -#define CP_BLIT_4_DST_Y2__SHIFT 16 -static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) -{ - return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK; -} - -#define REG_CP_EXEC_CS_0 0x00000000 - -#define REG_CP_EXEC_CS_1 0x00000001 -#define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff -#define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0 -static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val) -{ - return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK; -} - -#define REG_CP_EXEC_CS_2 0x00000002 -#define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff -#define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0 -static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) -{ - return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK; -} - -#define REG_CP_EXEC_CS_3 0x00000003 -#define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff -#define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0 -static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) -{ - return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK; -} - -#define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000 - - -#define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001 -#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff -#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0 -static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) -{ - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK; -} - -#define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002 -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2 -static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) -{ - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK; -} -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000 -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12 -static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) -{ - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK; -} -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000 -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22 -static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) -{ - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; -} - - -#define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001 -#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff -#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 -static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK; -} - -#define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002 -#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff -#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0 -static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK; -} - -#define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003 -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2 -static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK; -} -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000 -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12 -static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK; -} -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000 -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22 -static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK; -} - -#define REG_A2XX_CP_SET_MARKER_0 0x00000000 -#define A2XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f -#define A2XX_CP_SET_MARKER_0_MARKER__SHIFT 0 -static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val) -{ - return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK; -} -#define A2XX_CP_SET_MARKER_0_MODE__MASK 0x0000000f -#define A2XX_CP_SET_MARKER_0_MODE__SHIFT 0 -static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val) -{ - return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK; -} -#define A2XX_CP_SET_MARKER_0_IFPC 0x00000100 - -static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } - -static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } -#define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007 -#define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0 -static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) -{ - return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK; -} - -static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } -#define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff -#define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0 -static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) -{ - return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK; -} - -static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } -#define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff -#define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0 -static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) -{ - return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK; -} - -#define REG_A2XX_CP_REG_TEST_0 0x00000000 -#define A2XX_CP_REG_TEST_0_REG__MASK 0x00000fff -#define A2XX_CP_REG_TEST_0_REG__SHIFT 0 -static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val) -{ - return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK; -} -#define A2XX_CP_REG_TEST_0_BIT__MASK 0x01f00000 -#define A2XX_CP_REG_TEST_0_BIT__SHIFT 20 -static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val) -{ - return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK; -} -#define A2XX_CP_REG_TEST_0_UNK25 0x02000000 - - -#endif /* ADRENO_PM4_XML */ diff --git a/src/freedreno/registers/freedreno_copyright.xml b/src/freedreno/registers/freedreno_copyright.xml new file mode 100644 index 00000000000..bb0a84a2e82 --- /dev/null +++ b/src/freedreno/registers/freedreno_copyright.xml @@ -0,0 +1,40 @@ +<?xml version="1.0" encoding="UTF-8"?> +<database xmlns="http://nouveau.freedesktop.org/" +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" +xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> + +<copyright year="2013"> + +<author name="Rob Clark" email="[email protected]"><nick name="robclark"/> +Initial Author. +</author> + +<author name="Ilia Mirkin" email="[email protected]"><nick name="imirkin"/> +many a3xx/a4xx contributions +</author> + +<license> +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +</license> + +</copyright> +</database> + diff --git a/src/freedreno/registers/gen_header.py b/src/freedreno/registers/gen_header.py new file mode 100644 index 00000000000..cb565bb2fd4 --- /dev/null +++ b/src/freedreno/registers/gen_header.py @@ -0,0 +1,337 @@ +#!/usr/bin/python3 + +import xml.parsers.expat +import sys +import os + +class Error(Exception): + def __init__(self, message): + self.message = message + +class Enum(object): + def __init__(self, name): + self.name = name + self.values = [] + + def dump(self): + prev = 0 + use_hex = False + for (name, value) in self.values: + if value > 0x1000: + use_hex = True + + print("enum %s {" % self.name) + for (name, value) in self.values: + if use_hex: + print("\t%s = 0x%08x," % (name, value)) + else: + print("\t%s = %d," % (name, value)) + print("};\n") + +class Field(object): + def __init__(self, name, low, high, shr, type, parser): + self.name = name + self.low = low + self.high = high + self.shr = shr + self.type = type + + builtin_types = [ None, "boolean", "uint", "hex", "int", "fixed", "ufixed", "float" ] + + if low < 0 or low > 31: + raise parser.error("low attribute out of range: %d" % low) + if high < 0 or high > 31: + raise parser.error("high attribute out of range: %d" % high) + if high < low: + raise parser.error("low is greater than high: low=%d, high=%d" % (low, high)) + if self.type == "boolean" and not low == high: + raise parser.error("booleans should be 1 bit fields"); + elif self.type == "float" and not (high - low == 31 or high - low == 15): + raise parser.error("floats should be 16 or 32 bit fields") + elif not self.type in builtin_types and not self.type in parser.enums: + raise parser.error("unknown type '%s'" % self.type); + + def ctype(self): + if self.type == None: + type = "uint32_t" + val = "val" + elif self.type == "boolean": + type = "bool" + val = "val" + elif self.type == "uint" or self.type == "hex": + type = "uint32_t" + val = "val" + elif self.type == "int": + type = "int32_t" + val = "val" + elif self.type == "fixed": + type = "float" + val = "((int32_t)(val * %d.0))" % (1 << self.radix) + elif self.type == "ufixed": + type = "float" + val = "((uint32_t)(val * %d.0))" % (1 << self.radix) + elif self.type == "float" and self.high - self.low == 31: + type = "float" + val = "fui(val)" + elif self.type == "float" and self.high - self.low == 15: + type = "float" + val = "util_float_to_half(val)" + else: + type = "enum %s" % self.type + val = "val" + + if self.shr > 0: + val = "%s >> %d" % (val, self.shr) + + return (type, val) + +def tab_to(name, value): + tab_count = (68 - (len(name) & ~7)) // 8 + if tab_count == 0: + tab_count = 1 + print(name + ('\t' * tab_count) + value) + +def mask(low, high): + return ((0xffffffff >> (32 - (high + 1 - low))) << low) + +class Bitset(object): + def __init__(self, name, template): + self.name = name + self.inline = False + if template: + self.fields = template.fields + else: + self.fields = [] + + def dump(self, prefix=None): + if prefix == None: + prefix = self.name + for f in self.fields: + if f.name: + name = prefix + "_" + f.name + else: + name = prefix + + if not f.name and f.low == 0 and f.shr == 0 and not f.type in ["float", "fixed", "ufixed"]: + pass + elif f.type == "boolean" or (f.type == None and f.low == f.high): + tab_to("#define %s" % name, "0x%08x" % (1 << f.low)) + else: + tab_to("#define %s__MASK" % name, "0x%08x" % mask(f.low, f.high)) + tab_to("#define %s__SHIFT" % name, "%d" % f.low) + type, val = f.ctype() + + print("static inline uint32_t %s(%s val)\n{" % (name, type)) + if f.shr > 0: + print("\tassert(!(val & 0x%x));" % mask(0, f.shr - 1)) + print("\treturn ((%s) << %s__SHIFT) & %s__MASK;\n}" % (val, name, name)) + +class Array(object): + def __init__(self, attrs, domain): + self.name = attrs["name"] + self.domain = domain + self.offset = int(attrs["offset"], 0) + self.stride = int(attrs["stride"], 0) + self.length = int(attrs["length"], 0) + + def dump(self): + print("static inline uint32_t REG_%s_%s(uint32_t i0) { return 0x%08x + 0x%x*i0; }\n" % (self.domain, self.name, self.offset, self.stride)) + +class Reg(object): + def __init__(self, attrs, domain, array): + self.name = attrs["name"] + self.domain = domain + self.array = array + self.offset = int(attrs["offset"], 0) + self.type = None + + def dump(self): + if self.array: + name = self.domain + "_" + self.array.name + "_" + self.name + offset = self.array.offset + self.offset + print("static inline uint32_t REG_%s(uint32_t i0) { return 0x%08x + 0x%x*i0; }" % (name, offset, self.array.stride)) + else: + name = self.domain + "_" + self.name + tab_to("#define REG_%s" % name, "0x%08x" % self.offset) + + if self.bitset.inline: + self.bitset.dump(name) + print("") + +def parse_variants(attrs): + if not "variants" in attrs: + return None + variant = attrs["variants"].split(",")[0] + if "-" in variant: + variant = variant[:variant.index("-")] + + return variant + +class Parser(object): + def __init__(self): + self.current_array = None + self.current_domain = None + self.current_prefix = None + self.current_stripe = None + self.current_bitset = None + self.bitsets = {} + self.enums = {} + self.file = [] + + def error(self, message): + parser, filename = self.stack[-1] + return Error("%s:%d:%d: %s" % (filename, parser.CurrentLineNumber, parser.CurrentColumnNumber, message)) + + def prefix(self): + if self.current_stripe: + return self.current_stripe + "_" + self.current_domain + elif self.current_prefix: + return self.current_prefix + "_" + self.current_domain + else: + return self.current_domain + + def parse_field(self, name, attrs): + try: + if "pos" in attrs: + high = low = int(attrs["pos"], 0) + elif "high" in attrs and "low" in attrs: + high = int(attrs["high"], 0) + low = int(attrs["low"], 0) + else: + low = 0 + high = 31 + + if "type" in attrs: + type = attrs["type"] + else: + type = None + + if "shr" in attrs: + shr = int(attrs["shr"], 0) + else: + shr = 0 + + b = Field(name, low, high, shr, type, self) + + if type == "fixed" or type == "ufixed": + b.radix = int(attrs["radix"], 0) + + self.current_bitset.fields.append(b) + except ValueError as e: + raise self.error(e); + + def do_parse(self, filename): + file = open(filename, "rb") + parser = xml.parsers.expat.ParserCreate() + self.stack.append((parser, filename)) + parser.StartElementHandler = self.start_element + parser.EndElementHandler = self.end_element + parser.ParseFile(file) + self.stack.pop() + file.close() + + def parse(self, filename): + self.path = os.path.dirname(filename) + self.stack = [] + self.do_parse(filename) + + def start_element(self, name, attrs): + if name == "import": + filename = os.path.basename(attrs["file"]) + self.do_parse(os.path.join(self.path, filename)) + elif name == "domain": + self.current_domain = attrs["name"] + if "prefix" in attrs and attrs["prefix"] == "chip": + self.current_prefix = parse_variants(attrs) + elif name == "stripe": + self.current_stripe = parse_variants(attrs) + elif name == "enum": + self.current_enum_value = 0 + self.current_enum = Enum(attrs["name"]) + self.enums[attrs["name"]] = self.current_enum + if len(self.stack) == 1: + self.file.append(self.current_enum) + elif name == "value": + if "value" in attrs: + value = int(attrs["value"], 0) + else: + value = self.current_enum_value + self.current_enum.values.append((attrs["name"], value)) + # self.current_enum_value = value + 1 + elif name == "reg32": + if "type" in attrs and attrs["type"] in self.bitsets: + self.current_bitset = self.bitsets[attrs["type"]] + else: + self.current_bitset = Bitset(attrs["name"], None) + self.current_bitset.inline = True + if "type" in attrs: + self.parse_field(None, attrs) + + self.current_reg = Reg(attrs, self.prefix(), self.current_array) + self.current_reg.bitset = self.current_bitset + + if len(self.stack) == 1: + self.file.append(self.current_reg) + elif name == "array": + self.current_array = Array(attrs, self.prefix()) + if len(self.stack) == 1: + self.file.append(self.current_array) + elif name == "bitset": + self.current_bitset = Bitset(attrs["name"], None) + if "inline" in attrs and attrs["inline"] == "yes": + self.current_bitset.inline = True + self.bitsets[self.current_bitset.name] = self.current_bitset + if len(self.stack) == 1 and not self.current_bitset.inline: + self.file.append(self.current_bitset) + elif name == "bitfield" and self.current_bitset: + self.parse_field(attrs["name"], attrs) + + def end_element(self, name): + if name == "domain": + self.current_domain = None + self.current_prefix = None + elif name == "stripe": + self.current_stripe = None + elif name == "bitset": + self.current_bitset = None + elif name == "reg32": + self.current_reg = None + elif name == "array": + self.current_array = None; + elif name == "enum": + self.current_enum = None + + def dump(self): + enums = [] + bitsets = [] + regs = [] + for e in self.file: + if isinstance(e, Enum): + enums.append(e) + elif isinstance(e, Bitset): + bitsets.append(e) + else: + regs.append(e) + + for e in enums + bitsets + regs: + e.dump() + +def main(): + p = Parser() + xml_file = sys.argv[1] + + guard = str.replace(os.path.basename(xml_file), '.', '_').upper() + print("#ifndef %s\n#define %s\n" % (guard, guard)) + + try: + p.parse(xml_file) + except Error as e: + print(e) + exit(1) + + p.dump() + + print("\n#endif /* %s */" % guard) + +if __name__ == '__main__': + main() diff --git a/src/freedreno/registers/meson.build b/src/freedreno/registers/meson.build new file mode 100644 index 00000000000..4d361504777 --- /dev/null +++ b/src/freedreno/registers/meson.build @@ -0,0 +1,41 @@ +# Copyright © 2019 Google, Inc + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +xml_files = [ + 'a2xx.xml', + 'a3xx.xml', + 'a4xx.xml', + 'a5xx.xml', + 'a6xx.xml', + 'adreno_common.xml', + 'adreno_pm4.xml', +] + +freedreno_xml_header_files = [] +foreach f : xml_files + _name = f + '.h' + freedreno_xml_header_files += custom_target( + _name, + input : ['gen_header.py', f], + output : _name, + command : [prog_python, '@INPUT@'], + capture : true, + ) +endforeach diff --git a/src/freedreno/vulkan/meson.build b/src/freedreno/vulkan/meson.build index d2234d8a782..b3b7c02664e 100644 --- a/src/freedreno/vulkan/meson.build +++ b/src/freedreno/vulkan/meson.build @@ -86,7 +86,7 @@ endif libvulkan_freedreno = shared_library( 'vulkan_freedreno', - [libtu_files, tu_entrypoints, tu_extensions_c, tu_format_table_c], + [libtu_files, tu_entrypoints, tu_extensions_c, tu_format_table_c, freedreno_xml_header_files], include_directories : [ inc_common, inc_compiler, diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index 6dc74a4e4ff..fe436e595ec 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -729,11 +729,11 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd, const struct tu_tile *tile) { tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); - tu_cs_emit(cs, A2XX_CP_SET_MARKER_0_MODE(0x7)); + tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7)); tu6_emit_marker(cmd, cs); tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); - tu_cs_emit(cs, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10); + tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10); tu6_emit_marker(cmd, cs); const uint32_t x1 = tile->begin.x; @@ -814,7 +814,7 @@ tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu6_emit_marker(cmd, cs); tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); - tu_cs_emit(cs, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10); + tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10); tu6_emit_marker(cmd, cs); tu6_emit_blit_scissor(cmd, cs); diff --git a/src/freedreno/vulkan/tu_meta_copy.c b/src/freedreno/vulkan/tu_meta_copy.c index e23e651d698..ced8661d59e 100644 --- a/src/freedreno/vulkan/tu_meta_copy.c +++ b/src/freedreno/vulkan/tu_meta_copy.c @@ -111,7 +111,7 @@ tu_copy_buffer(struct tu_cmd_buffer *cmdbuf, /* buffer copy setup */ tu_cs_emit_pkt7(&cmdbuf->cs, CP_SET_MARKER, 1); - tu_cs_emit(&cmdbuf->cs, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); + tu_cs_emit(&cmdbuf->cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); const uint32_t blit_cntl = blit_control(RB6_R8_UNORM) | 0x20000000; @@ -356,7 +356,7 @@ tu_copy_buffer_to_image(struct tu_cmd_buffer *cmdbuf, /* buffer copy setup */ tu_cs_emit_pkt7(&cmdbuf->cs, CP_SET_MARKER, 1); - tu_cs_emit(&cmdbuf->cs, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); + tu_cs_emit(&cmdbuf->cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); VkFormat format = dst_image->vk_format; const enum a6xx_color_fmt rb_fmt = tu6_get_native_format(format)->rb; @@ -546,7 +546,7 @@ tu_copy_image_to_buffer(struct tu_cmd_buffer *cmdbuf, /* buffer copy setup */ tu_cs_emit_pkt7(&cmdbuf->cs, CP_SET_MARKER, 1); - tu_cs_emit(&cmdbuf->cs, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); + tu_cs_emit(&cmdbuf->cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); VkFormat format = src_image->vk_format; const enum a6xx_color_fmt rb_fmt = tu6_get_native_format(format)->rb; diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c index afa162e9ebe..f8fdc33ec72 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c @@ -255,7 +255,7 @@ emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info) dshift = dbox->x & 0x3f; OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); uint32_t blit_cntl = blit_control(RB6_R8_UNORM) | 0x20000000; OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1); @@ -418,7 +418,7 @@ emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info) uint32_t height = DIV_ROUND_UP(u_minify(src->base.height0, info->src.level), blockheight); OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); uint32_t blit_cntl = blit_control(dfmt); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c index f3bc0ed231d..2e6a7fd21b0 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c @@ -158,7 +158,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) } OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x8)); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x8)); const unsigned *local_size = info->block; // v->shader->nir->info->cs.local_size; const unsigned *num_groups = info->grid; diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c index ff9e4bb036c..245c8b715b0 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c @@ -262,7 +262,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) emit_marker6(ring, 7); OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS)); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS)); emit_marker6(ring, 7); OUT_WFI5(ring); @@ -275,7 +275,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) emit_marker6(ring, 7); OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0xc)); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0xc)); emit_marker6(ring, 7); OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index 77eda58c3f1..27c57a0074c 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -420,7 +420,7 @@ emit_binning_pass(struct fd_batch *batch) emit_marker6(ring, 7); OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING)); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING)); emit_marker6(ring, 7); OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1); @@ -606,7 +606,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile) emit_marker6(ring, 7); OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10); emit_marker6(ring, 7); uint32_t x1 = tile->xoff; @@ -1109,7 +1109,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile) if (use_hw_binning(batch)) { OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x5) | 0x10); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10); } OUT_PKT7(ring, CP_SET_DRAW_STATE, 3); @@ -1124,13 +1124,13 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile) emit_marker6(ring, 7); OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10); emit_marker6(ring, 7); fd6_emit_ib(ring, batch->tile_fini); OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x7)); + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x7)); } static void @@ -1158,7 +1158,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) emit_marker6(ring, 7); OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */ + OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */ emit_marker6(ring, 7); OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1); diff --git a/src/gallium/drivers/freedreno/meson.build b/src/gallium/drivers/freedreno/meson.build index 45938795496..8bd251b5a23 100644 --- a/src/gallium/drivers/freedreno/meson.build +++ b/src/gallium/drivers/freedreno/meson.build @@ -232,7 +232,7 @@ endif libfreedreno = static_library( 'freedreno', - [files_libfreedreno], + [files_libfreedreno, freedreno_xml_header_files], include_directories : freedreno_includes, c_args : [freedreno_c_args, c_vis_args], cpp_args : [freedreno_cpp_args, cpp_vis_args], |