diff options
| author | Alyssa Rosenzweig <[email protected]> | 2019-07-01 20:23:50 -0700 |
|---|---|---|
| committer | Alyssa Rosenzweig <[email protected]> | 2019-07-10 06:12:05 -0700 |
| commit | b113be7683afec96426575496d76ae3beb03a5e1 (patch) | |
| tree | b0128a73aba81ed5c8a35503ea940c3ef515e289 /src | |
| parent | e92caad74476b915bb73baedbddce8af89bd62b0 (diff) | |
panfrost/midgard: Fix scalarification
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/midgard_emit.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/panfrost/midgard/midgard_schedule.c | 27 |
2 files changed, 25 insertions, 5 deletions
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_emit.c b/src/gallium/drivers/panfrost/midgard/midgard_emit.c index 2a71d1c0da1..f5d2d7212b3 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_emit.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_emit.c @@ -89,12 +89,13 @@ vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins) { bool is_int = midgard_is_integer_op(v.op); bool is_full = v.reg_mode == midgard_reg_mode_32; + bool is_inline_constant = ins->ssa_args.inline_constant; /* The output component is from the mask */ midgard_scalar_alu s = { .op = v.op, .src1 = vector_to_scalar_source(v.src1, is_int, is_full), - .src2 = vector_to_scalar_source(v.src2, is_int, is_full), + .src2 = !is_inline_constant ? vector_to_scalar_source(v.src2, is_int, is_full) : 0, .unknown = 0, .outmod = v.outmod, .output_full = is_full, diff --git a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c index ebbabae10bf..191017671cd 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c @@ -191,7 +191,6 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction int op = ains->alu.op; int units = alu_opcode_props[op].props; - bool vectorable = units & UNITS_ANY_VECTOR; bool scalarable = units & UNITS_SCALAR; bool could_scalar = is_single_component_mask(ains->mask); @@ -200,15 +199,35 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction could_scalar &= ains->alu.reg_mode != midgard_reg_mode_64; could_scalar &= ains->alu.dest_override == midgard_dest_override_none; - bool vector = vectorable && !(could_scalar && scalarable); + if (ains->alu.reg_mode == midgard_reg_mode_16) { + /* If we're running in 16-bit mode, we + * can't have any 8-bit sources on the + * scalar unit (since the scalar unit + * doesn't understand 8-bit) */ + + midgard_vector_alu_src s1 = + vector_alu_from_unsigned(ains->alu.src1); + + could_scalar &= !s1.half; + + if (!ains->ssa_args.inline_constant) { + midgard_vector_alu_src s2 = + vector_alu_from_unsigned(ains->alu.src2); + + could_scalar &= !s2.half; + } + + } + + bool scalar = could_scalar && scalarable; /* TODO: Check ahead-of-time for other scalar * hazards that otherwise get aborted out */ - if (!vector) + if (scalar) assert(units & UNITS_SCALAR); - if (vector) { + if (!scalar) { if (last_unit >= UNIT_VADD) { if (units & UNIT_VLUT) unit = UNIT_VLUT; |