diff options
| author | Vincent Lejeune <[email protected]> | 2012-10-04 23:55:02 +0200 |
|---|---|---|
| committer | Vincent Lejeune <[email protected]> | 2012-10-10 22:02:45 +0200 |
| commit | 8db11bc4ed366354aa8b8153240c4a191888785b (patch) | |
| tree | 9fb177e1e44ba292955b85fc1c06841e26c2f9a2 /src | |
| parent | 23e11ac8354b3807d9c69c19bcf958cca23ffc04 (diff) | |
radeon/llvm: use llvm intrinsic for flog2
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src')
4 files changed, 4 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp index 04dadc398d4..aee625d256a 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp @@ -35,6 +35,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::FCEIL, MVT::f32, Legal); setOperationAction(ISD::FEXP2, MVT::f32, Legal); setOperationAction(ISD::FPOW, MVT::f32, Legal); + setOperationAction(ISD::FLOG2, MVT::f32, Legal); setOperationAction(ISD::FRINT, MVT::f32, Legal); setOperationAction(ISD::UDIV, MVT::i32, Expand); diff --git a/src/gallium/drivers/radeon/AMDILIntrinsics.td b/src/gallium/drivers/radeon/AMDILIntrinsics.td index 104b32e38ca..4de57674272 100644 --- a/src/gallium/drivers/radeon/AMDILIntrinsics.td +++ b/src/gallium/drivers/radeon/AMDILIntrinsics.td @@ -180,8 +180,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in { UnaryIntFloat; def int_AMDIL_exn : GCCBuiltin<"__amdil_exn">, UnaryIntFloat; - def int_AMDIL_log : GCCBuiltin<"__amdil_log">, - UnaryIntFloat; def int_AMDIL_log_vec : GCCBuiltin<"__amdil_log_vec">, UnaryIntFloat; def int_AMDIL_ln : GCCBuiltin<"__amdil_ln">, diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index e32ea693584..620fd38321b 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -761,7 +761,7 @@ class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP < class LOG_IEEE_Common <bits<11> inst> : R600_1OP < inst, "LOG_IEEE", - [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))] + [(set R600_Reg32:$dst, (flog2 R600_Reg32:$src))] >; class LSHL_Common <bits<11> inst> : R600_2OP < diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c index 8b5eaed5e26..cc690c0211e 100644 --- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c +++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c @@ -1151,8 +1151,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx) bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill"; bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic; bld_base->op_actions[TGSI_OPCODE_KILP].intr_name = "llvm.AMDGPU.kilp"; - bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.AMDIL.log."; + bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_readonly; + bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32"; bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem; bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp"; bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem; |