diff options
| author | Marek Olšák <[email protected]> | 2016-10-23 15:29:18 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-10-26 13:02:58 +0200 |
| commit | 8a21f52d73936e23a314a288a36782a698c7c1b9 (patch) | |
| tree | ffb9cebe794ae804c944e99e86323dec4ecc8776 /src | |
| parent | 0e742926c6895dcaf8bdbe43022c8a0bc74fdd96 (diff) | |
gallium/radeon: fix incorrect bpe use in si_set_optimal_micro_tile_mode
Oh my god, I wonder what catastrophic issues this was causing on SI.
Cc: 13.0 <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 625d091fe40..b57cc922070 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -2442,29 +2442,29 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen, switch (rtex->last_msaa_resolve_target_micro_mode) { case 0: /* displayable */ switch (rtex->surface.bpe) { - case 8: + case 1: rtex->surface.tiling_index[0] = 10; break; - case 16: + case 2: rtex->surface.tiling_index[0] = 11; break; - default: /* 32, 64 */ + default: /* 4, 8 */ rtex->surface.tiling_index[0] = 12; break; } break; case 1: /* thin */ switch (rtex->surface.bpe) { - case 8: + case 1: rtex->surface.tiling_index[0] = 14; break; - case 16: + case 2: rtex->surface.tiling_index[0] = 15; break; - case 32: + case 4: rtex->surface.tiling_index[0] = 16; break; - default: /* 64, 128 */ + default: /* 8, 16 */ rtex->surface.tiling_index[0] = 17; break; } |