diff options
author | Caio Marcelo de Oliveira Filho <[email protected]> | 2019-05-23 14:17:41 -0700 |
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committer | Caio Marcelo de Oliveira Filho <[email protected]> | 2019-06-03 14:14:45 -0700 |
commit | 56114448096ab5ac25599d157f0b168137ba5bf6 (patch) | |
tree | d7b653eaf39a76f49e5c4df18467cbb71fcd5f34 /src | |
parent | 97cd865be28b3ef7508b243ed59e43cbc2a936f5 (diff) |
iris: Print binding tables when INTEL_DEBUG=bt
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
-rw-r--r-- | src/gallium/drivers/iris/iris_program.c | 53 | ||||
-rw-r--r-- | src/intel/dev/gen_debug.c | 1 | ||||
-rw-r--r-- | src/intel/dev/gen_debug.h | 1 |
3 files changed, 55 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index bd60e757d17..f18c914f62d 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -502,6 +502,55 @@ iris_setup_uniforms(const struct brw_compiler *compiler, *out_num_cbufs = num_cbufs; } +static const char *surface_group_names[] = { + [IRIS_SURFACE_GROUP_RENDER_TARGET] = "render target", + [IRIS_SURFACE_GROUP_CS_WORK_GROUPS] = "CS work groups", + [IRIS_SURFACE_GROUP_TEXTURE] = "texture", + [IRIS_SURFACE_GROUP_UBO] = "ubo", + [IRIS_SURFACE_GROUP_SSBO] = "ssbo", + [IRIS_SURFACE_GROUP_IMAGE] = "image", +}; + +static void +iris_print_binding_table(FILE *fp, const char *name, + const struct iris_binding_table *bt) +{ + STATIC_ASSERT(ARRAY_SIZE(surface_group_names) == IRIS_SURFACE_GROUP_COUNT); + + uint32_t total = 0; + uint32_t compacted = 0; + + for (int i = 0; i < IRIS_SURFACE_GROUP_COUNT; i++) { + uint32_t size = bt->sizes[i]; + total += size; + if (size) + compacted += util_bitcount64(bt->used_mask[i]); + } + + if (total == 0) { + fprintf(fp, "Binding table for %s is empty\n\n", name); + return; + } + + if (total != compacted) { + fprintf(fp, "Binding table for %s " + "(compacted to %u entries from %u entries)\n", + name, compacted, total); + } else { + fprintf(fp, "Binding table for %s (%u entries)\n", name, total); + } + + uint32_t entry = 0; + for (int i = 0; i < IRIS_SURFACE_GROUP_COUNT; i++) { + uint64_t mask = bt->used_mask[i]; + while (mask) { + int index = u_bit_scan64(&mask); + fprintf(fp, " [%u] %s #%d\n", entry++, surface_group_names[i], index); + } + } + fprintf(fp, "\n"); +} + enum { /* Max elements in a surface group. */ SURFACE_GROUP_MAX_ELEMENTS = 64, @@ -724,6 +773,10 @@ iris_setup_binding_table(struct nir_shader *nir, } bt->size_bytes = next * 4; + if (unlikely(INTEL_DEBUG & DEBUG_BT)) { + iris_print_binding_table(stderr, gl_shader_stage_name(info->stage), bt); + } + /* Apply the binding table indices. The backend compiler is not expected * to change those, as we haven't set any of the *_start entries in brw * binding_table. diff --git a/src/intel/dev/gen_debug.c b/src/intel/dev/gen_debug.c index 5fa3d29fa51..dd58e6b78c4 100644 --- a/src/intel/dev/gen_debug.c +++ b/src/intel/dev/gen_debug.c @@ -87,6 +87,7 @@ static const struct debug_control debug_control[] = { { "reemit", DEBUG_REEMIT }, { "soft64", DEBUG_SOFT64 }, { "tcs8", DEBUG_TCS_EIGHT_PATCH }, + { "bt", DEBUG_BT }, { NULL, 0 } }; diff --git a/src/intel/dev/gen_debug.h b/src/intel/dev/gen_debug.h index a6592354a64..07761143a7f 100644 --- a/src/intel/dev/gen_debug.h +++ b/src/intel/dev/gen_debug.h @@ -85,6 +85,7 @@ extern uint64_t INTEL_DEBUG; #define DEBUG_REEMIT (1ull << 41) #define DEBUG_SOFT64 (1ull << 42) #define DEBUG_TCS_EIGHT_PATCH (1ull << 43) +#define DEBUG_BT (1ull << 44) /* These flags are not compatible with the disk shader cache */ #define DEBUG_DISK_CACHE_DISABLE_MASK DEBUG_SHADER_TIME |