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authorSamuel Pitoiset <[email protected]>2019-07-16 17:11:50 +0200
committerSamuel Pitoiset <[email protected]>2019-07-17 08:32:39 +0200
commit07ff367442d52b301e05f9c4ff6d03b04ee703c1 (patch)
tree194939ffb6d04ee26403b48c469b0cba4374cd35 /src
parented53d2c4be2af281382fcf16091a6ee6739d0da0 (diff)
radv/gfx10: implement VK_EXT_post_depth_coverage
I did implement this extension a while ago but it didn't work on pre GFX10 for some reasons. Now all CTS pass. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/amd/vulkan/radv_extensions.py1
-rw-r--r--src/amd/vulkan/radv_nir_to_llvm.c1
-rw-r--r--src/amd/vulkan/radv_pipeline.c1
-rw-r--r--src/amd/vulkan/radv_shader.c1
-rw-r--r--src/amd/vulkan/radv_shader.h1
5 files changed, 5 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_extensions.py b/src/amd/vulkan/radv_extensions.py
index 8b6ba6a4df0..e9addad0035 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -120,6 +120,7 @@ EXTENSIONS = [
Extension('VK_EXT_memory_priority', 1, True),
Extension('VK_EXT_pci_bus_info', 2, True),
Extension('VK_EXT_pipeline_creation_feedback', 1, True),
+ Extension('VK_EXT_post_depth_coverage', 1, 'device->rad_info.chip_class >= GFX10'),
Extension('VK_EXT_queue_family_foreign', 1, True),
Extension('VK_EXT_sample_locations', 1, True),
Extension('VK_EXT_sampler_filter_minmax', 1, 'device->rad_info.chip_class >= GFX7'),
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index a689003d473..3e18303879e 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4637,6 +4637,7 @@ ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_sha
break;
case MESA_SHADER_FRAGMENT:
shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
+ shader_info->fs.post_depth_coverage = nir->info.fs.post_depth_coverage;
break;
case MESA_SHADER_GEOMETRY:
shader_info->gs.vertices_in = nir->info.gs.vertices_in;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a22e605ca1c..a3323ae8135 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3849,6 +3849,7 @@ radv_compute_db_shader_control(const struct radv_device *device,
S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
S_02880C_Z_ORDER(z_order) |
S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
+ S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.fs.post_depth_coverage) |
S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 6bafcb2f869..bcc050a86cc 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -270,6 +270,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
.int64_atomics = true,
.multiview = true,
.physical_storage_buffer_address = true,
+ .post_depth_coverage = true,
.runtime_descriptor_array = true,
.shader_viewport_index_layer = true,
.stencil_export = true,
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 360591349a8..fea0d1c8df1 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -283,6 +283,7 @@ struct radv_shader_variant_info {
uint32_t float16_shaded_mask;
bool can_discard;
bool early_fragment_test;
+ bool post_depth_coverage;
} fs;
struct {
unsigned block_size[3];