diff options
| author | Marek Olšák <[email protected]> | 2017-01-26 02:16:18 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-01-30 13:27:14 +0100 |
| commit | 9327780da68bf2bca8533c00bbd2ff1e91f32879 (patch) | |
| tree | 3cf2f64e4989ce61aae5984dec572cbd420429fb /src | |
| parent | 80157a2c203a265305b7c406febdf8964e3ac057 (diff) | |
winsys/amdgpu: fix ADDR_REGISTER_VALUE::backendDisables
This would be a fix if the value was used anywhere.
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index 08989b5cf53..abe2b2a67af 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -111,7 +111,7 @@ ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws) regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg; regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2; - regValue.backendDisables = ws->amdinfo.backend_disable[0]; + regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask; regValue.pTileConfig = ws->amdinfo.gb_tile_mode; regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode); if (ws->info.chip_class == SI) { |