ac/nir: move ac_nir_compiler_options and friends to radv folder

Also replace ac_ by radv_.

Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>

7 files changed, 89 insertions, 89 deletions

diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 1112369968b..c87e71f42b6 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -39,78 +39,6 @@ struct radv_pipeline_layout;
 struct ac_llvm_context;
 struct ac_shader_abi;
 
-struct ac_vs_variant_key {
-	uint32_t instance_rate_inputs;
-	uint32_t as_es:1;
-	uint32_t as_ls:1;
-	uint32_t export_prim_id:1;
-};
-
-struct ac_tes_variant_key {
-	uint32_t as_es:1;
-	uint32_t export_prim_id:1;
-};
-
-struct ac_tcs_variant_key {
-	struct ac_vs_variant_key vs_key;
-	unsigned primitive_mode;
-	unsigned input_vertices;
-	uint32_t tes_reads_tess_factors:1;
-};
-
-struct ac_fs_variant_key {
-	uint32_t col_format;
-	uint8_t log2_ps_iter_samples;
-	uint8_t log2_num_samples;
-	uint32_t is_int8;
-	uint32_t is_int10;
-	uint32_t multisample : 1;
-};
-
-struct ac_shader_variant_key {
-	union {
-		struct ac_vs_variant_key vs;
-		struct ac_fs_variant_key fs;
-		struct ac_tes_variant_key tes;
-		struct ac_tcs_variant_key tcs;
-	};
-	bool has_multiview_view_index;
-};
-
-struct ac_nir_compiler_options {
-	struct radv_pipeline_layout *layout;
-	struct ac_shader_variant_key key;
-	bool unsafe_math;
-	bool supports_spill;
-	bool clamp_shadow_reference;
-	bool dump_preoptir;
-	enum radeon_family family;
-	enum chip_class chip_class;
-};
-
-enum ac_ud_index {
-	AC_UD_SCRATCH_RING_OFFSETS = 0,
-	AC_UD_PUSH_CONSTANTS = 1,
-	AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
-	AC_UD_VIEW_INDEX = 3,
-	AC_UD_SHADER_START = 4,
-	AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
-	AC_UD_VS_BASE_VERTEX_START_INSTANCE,
-	AC_UD_VS_LS_TCS_IN_LAYOUT,
-	AC_UD_VS_MAX_UD,
-	AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
-	AC_UD_PS_MAX_UD,
-	AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
-	AC_UD_CS_MAX_UD,
-	AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
-	AC_UD_GS_MAX_UD,
-	AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
-	AC_UD_TCS_MAX_UD,
-	AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
-	AC_UD_TES_MAX_UD,
-	AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
-};
-
 /* Interpolation locations */
 #define INTERP_CENTER 0
 #define INTERP_CENTROID 1
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 25ee3b91fc6..bac71c53c76 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -46,7 +46,7 @@
 
 struct radv_shader_context {
 	struct ac_llvm_context ac;
-	const struct ac_nir_compiler_options *options;
+	const struct radv_nir_compiler_options *options;
 	struct radv_shader_variant_info *shader_info;
 	struct ac_shader_abi abi;
 
@@ -2978,7 +2978,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
                                        struct nir_shader *const *shaders,
                                        int shader_count,
                                        struct radv_shader_variant_info *shader_info,
-                                       const struct ac_nir_compiler_options *options,
+                                       const struct radv_nir_compiler_options *options,
 				       bool dump_shader)
 {
 	struct radv_shader_context ctx = {0};
@@ -3296,7 +3296,7 @@ static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
 }
 
 static void
-ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
+ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
 {
         switch (nir->info.stage) {
         case MESA_SHADER_COMPUTE:
@@ -3341,7 +3341,7 @@ radv_compile_nir_shader(LLVMTargetMachineRef tm,
 			struct radv_shader_variant_info *shader_info,
 			struct nir_shader *const *nir,
 			int nir_count,
-			const struct ac_nir_compiler_options *options,
+			const struct radv_nir_compiler_options *options,
 			bool dump_shader)
 {
 
@@ -3409,7 +3409,7 @@ radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
 			    struct ac_shader_binary *binary,
 			    struct ac_shader_config *config,
 			    struct radv_shader_variant_info *shader_info,
-			    const struct ac_nir_compiler_options *options,
+			    const struct radv_nir_compiler_options *options,
 			    bool dump_shader)
 {
 	struct radv_shader_context ctx = {0};
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index acb46ec12f8..e02e06505e4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1589,7 +1589,7 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
 }
 
 static void
-radv_fill_shader_keys(struct ac_shader_variant_key *keys,
+radv_fill_shader_keys(struct radv_shader_variant_key *keys,
                       const struct radv_pipeline_key *key,
                       nir_shader **nir)
 {
@@ -1672,7 +1672,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 	nir_shader *nir[MESA_SHADER_STAGES] = {0};
 	void *codes[MESA_SHADER_STAGES] = {0};
 	unsigned code_sizes[MESA_SHADER_STAGES] = {0};
-	struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
+	struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
 	unsigned char hash[20], gs_copy_hash[20];
 
 	for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
@@ -1787,7 +1787,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 	if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
 		if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
 			struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
-			struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
+			struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
 			key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
 			pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
 			                                                                      pipeline->layout,
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 913fbe7f934..0ff62aa7dea 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1679,13 +1679,14 @@ struct radv_fence {
 
 /* radv_nir_to_llvm.c */
 struct radv_shader_variant_info;
+struct radv_nir_compiler_options;
 
 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
 				 struct nir_shader *geom_shader,
 				 struct ac_shader_binary *binary,
 				 struct ac_shader_config *config,
 				 struct radv_shader_variant_info *shader_info,
-				 const struct ac_nir_compiler_options *options,
+				 const struct radv_nir_compiler_options *options,
 				 bool dump_shader);
 
 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
@@ -1694,14 +1695,14 @@ void radv_compile_nir_shader(LLVMTargetMachineRef tm,
 			     struct radv_shader_variant_info *shader_info,
 			     struct nir_shader *const *nir,
 			     int nir_count,
-			     const struct ac_nir_compiler_options *options,
+			     const struct radv_nir_compiler_options *options,
 			     bool dump_shader);
 
 /* radv_shader_info.h */
 struct radv_shader_info;
 
 void radv_nir_shader_info_pass(const struct nir_shader *nir,
-			       const struct ac_nir_compiler_options *options,
+			       const struct radv_nir_compiler_options *options,
 			       struct radv_shader_info *info);
 
 struct radeon_winsys_sem;
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index e11f19323f7..3eddc089d40 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -444,7 +444,7 @@ shader_variant_create(struct radv_device *device,
 		      struct nir_shader * const *shaders,
 		      int shader_count,
 		      gl_shader_stage stage,
-		      struct ac_nir_compiler_options *options,
+		      struct radv_nir_compiler_options *options,
 		      bool gs_copy_shader,
 		      void **code_out,
 		      unsigned *code_size_out)
@@ -517,11 +517,11 @@ radv_shader_variant_create(struct radv_device *device,
 			   struct nir_shader *const *shaders,
 			   int shader_count,
 			   struct radv_pipeline_layout *layout,
-			   const struct ac_shader_variant_key *key,
+			   const struct radv_shader_variant_key *key,
 			   void **code_out,
 			   unsigned *code_size_out)
 {
-	struct ac_nir_compiler_options options = {0};
+	struct radv_nir_compiler_options options = {0};
 
 	options.layout = layout;
 	if (key)
@@ -541,7 +541,7 @@ radv_create_gs_copy_shader(struct radv_device *device,
 			   unsigned *code_size_out,
 			   bool multiview)
 {
-	struct ac_nir_compiler_options options = {0};
+	struct radv_nir_compiler_options options = {0};
 
 	options.key.has_multiview_view_index = multiview;
 
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index a9b465cd80c..e7478fd56fc 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -53,6 +53,77 @@ struct radv_shader_module {
 	char data[0];
 };
 
+struct radv_vs_variant_key {
+	uint32_t instance_rate_inputs;
+	uint32_t as_es:1;
+	uint32_t as_ls:1;
+	uint32_t export_prim_id:1;
+};
+
+struct radv_tes_variant_key {
+	uint32_t as_es:1;
+	uint32_t export_prim_id:1;
+};
+
+struct radv_tcs_variant_key {
+	struct radv_vs_variant_key vs_key;
+	unsigned primitive_mode;
+	unsigned input_vertices;
+	uint32_t tes_reads_tess_factors:1;
+};
+
+struct radv_fs_variant_key {
+	uint32_t col_format;
+	uint8_t log2_ps_iter_samples;
+	uint8_t log2_num_samples;
+	uint32_t is_int8;
+	uint32_t is_int10;
+	uint32_t multisample : 1;
+};
+
+struct radv_shader_variant_key {
+	union {
+		struct radv_vs_variant_key vs;
+		struct radv_fs_variant_key fs;
+		struct radv_tes_variant_key tes;
+		struct radv_tcs_variant_key tcs;
+	};
+	bool has_multiview_view_index;
+};
+
+struct radv_nir_compiler_options {
+	struct radv_pipeline_layout *layout;
+	struct radv_shader_variant_key key;
+	bool unsafe_math;
+	bool supports_spill;
+	bool clamp_shadow_reference;
+	bool dump_preoptir;
+	enum radeon_family family;
+	enum chip_class chip_class;
+};
+
+enum radv_ud_index {
+	AC_UD_SCRATCH_RING_OFFSETS = 0,
+	AC_UD_PUSH_CONSTANTS = 1,
+	AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
+	AC_UD_VIEW_INDEX = 3,
+	AC_UD_SHADER_START = 4,
+	AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
+	AC_UD_VS_BASE_VERTEX_START_INSTANCE,
+	AC_UD_VS_LS_TCS_IN_LAYOUT,
+	AC_UD_VS_MAX_UD,
+	AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
+	AC_UD_PS_MAX_UD,
+	AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
+	AC_UD_CS_MAX_UD,
+	AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
+	AC_UD_GS_MAX_UD,
+	AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
+	AC_UD_TCS_MAX_UD,
+	AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
+	AC_UD_TES_MAX_UD,
+	AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
+};
 struct radv_shader_info {
 	bool loads_push_constants;
 	uint32_t desc_set_used_mask;
@@ -224,7 +295,7 @@ radv_shader_variant_create(struct radv_device *device,
 			   struct nir_shader *const *shaders,
 			   int shader_count,
 			   struct radv_pipeline_layout *layout,
-			   const struct ac_shader_variant_key *key,
+			   const struct radv_shader_variant_key *key,
 			   void **code_out,
 			   unsigned *code_size_out);
 
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index a6d8033bcb1..3cce0c2f6e4 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -288,7 +288,7 @@ gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 
 void
 radv_nir_shader_info_pass(const struct nir_shader *nir,
-			  const struct ac_nir_compiler_options *options,
+			  const struct radv_nir_compiler_options *options,
 			  struct radv_shader_info *info)
 {
 	struct nir_function *func =