diff options
| author | Marek Olšák <[email protected]> | 2017-08-10 21:50:59 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-08-11 20:38:29 +0200 |
| commit | d1285a710329dca907ebab0154b6c16b89b945ef (patch) | |
| tree | 055a53df1dc331f8e59803dfa89c79019f828a97 /src | |
| parent | 27fef5d52d44c8684fa4e7a21bd7a4284f3688ee (diff) | |
radeonsi/gfx9: fix the scissor bug workaround
otherwise there is corruption in most apps.
Fixes: 0fe0320 radeonsi: use optimal packet order when doing a pipeline sync
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 23e9778fa54..deb0691f5c3 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1368,11 +1368,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) if (!si_upload_vertex_buffer_descriptors(sctx)) return; - /* GFX9 scissor bug workaround. There is also a more efficient but - * more involved alternative workaround. */ + /* GFX9 scissor bug workaround. This must be done before VPORT scissor + * registers are changed. There is also a more efficient but more + * involved alternative workaround. + */ if (sctx->b.chip_class == GFX9 && - si_is_atom_dirty(sctx, &sctx->b.scissors.atom)) + si_is_atom_dirty(sctx, &sctx->b.scissors.atom)) { sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH; + si_emit_cache_flush(sctx); + } /* Use optimal packet order based on whether we need to sync the pipeline. */ if (unlikely(sctx->b.flags & (SI_CONTEXT_FLUSH_AND_INV_CB | |