diff options
| author | Michel Dänzer <[email protected]> | 2012-08-31 19:04:08 +0200 |
|---|---|---|
| committer | Michel Dänzer <[email protected]> | 2012-09-06 16:46:55 +0200 |
| commit | cfebaf9dbd4839075786eb340a247f41bdcf9fa6 (patch) | |
| tree | 5ff89186e3bfd2efc0fa802dd9fddb3ec8fa4fc9 /src | |
| parent | 5edb80cee0e7d291db29963f01f2940fbd990398 (diff) | |
radeonsi: Enable whole quad mode for pixel shaders.
Fixes wrong mipmap level being sampled at some triangle edges.
Signed-off-by: Michel Dänzer <[email protected]>
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/radeonsi_shader.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c index 8c9214933ff..1c330b5fd3a 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_shader.c +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c @@ -75,7 +75,7 @@ struct si_shader_context struct tgsi_token * tokens; struct si_pipe_shader *shader; unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */ -/* unsigned num_inputs; */ + unsigned ninput_emitted; /* struct list_head inputs; */ /* unsigned * input_mappings *//* From TGSI to SI hw */ /* struct tgsi_shader_info info;*/ @@ -319,6 +319,14 @@ static void declare_input_fs( return; } + if (!si_shader_ctx->ninput_emitted++) { + /* Enable whole quad mode */ + lp_build_intrinsic(gallivm->builder, + "llvm.SI.wqm", + LLVMVoidTypeInContext(gallivm->context), + NULL, 0); + } + /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */ for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { LLVMValueRef args[3]; @@ -689,7 +697,7 @@ int si_pipe_shader_create( dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE); - memset(&si_shader_ctx.radeon_bld, 0, sizeof(si_shader_ctx.radeon_bld)); + memset(&si_shader_ctx, 0, sizeof(si_shader_ctx)); radeon_llvm_context_init(&si_shader_ctx.radeon_bld); bld_base = &si_shader_ctx.radeon_bld.soa.bld_base; |