diff options
| author | Marek Olšák <[email protected]> | 2017-07-29 17:19:01 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-08-04 02:10:04 +0200 |
| commit | c60c5accd1b20514dbbbbab7ac40004ad7122b44 (patch) | |
| tree | ed9892d93a617dae97d0185eedd53b21ab771926 /src | |
| parent | 0141beadd8da5c857fe76f42a49ce379f0c700af (diff) | |
ac/surface: align DCC size for surfaces that use tile swizzle
Note that dcc_alignment = pipe_interleave_bytes * num_pipes * num_banks,
which is greater than the previous open-coded alignment.
Reviewed-by: Dave Airlie <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/common/ac_surface.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 3716d3ddb04..823a65d038f 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -734,9 +734,16 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, * complicated. */ if (surf->dcc_size && config->info.levels > 1) { + /* The smallest miplevels that are never compressed by DCC + * still read the DCC buffer via TC if the base level uses DCC, + * and for some reason the DCC buffer needs to be larger if + * the miptree uses non-zero tile_swizzle. Otherwise there are + * VM faults. + * + * "dcc_alignment * 4" was determined by trial and error. + */ surf->dcc_size = align64(surf->surf_size >> 8, - info->pipe_interleave_bytes * - info->num_tile_pipes); + surf->dcc_alignment * 4); } /* Make sure HTILE covers the whole miptree, because the shader reads |