diff options
| author | Marek Olšák <[email protected]> | 2018-04-13 17:15:06 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-04-27 17:56:04 -0400 |
| commit | 6d19120da851c0d3f97376c733d674f7c8ab0457 (patch) | |
| tree | a1bc40e9e60a0be4e4450f20214f3fdad8d23c7c /src | |
| parent | 2d69b485f557d8d438edf7e99ad4b15bb2594061 (diff) | |
radeonsi/gfx9: workaround for INTERP with indirect indexing
and clean up the conditions.
Reviewed-by: Nicolai Hähnle <[email protected]>
Cc: 18.0 18.1 <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_get.c | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index cb28920bbed..04ab0f46bbd 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -477,12 +477,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* TODO: Indirect indexing of GS inputs is unimplemented. */ - return shader != PIPE_SHADER_GEOMETRY && - (sscreen->llvm_has_working_vgpr_indexing || - /* TCS and TES load inputs directly from LDS or - * offchip memory, so indirect indexing is trivial. */ - shader == PIPE_SHADER_TESS_CTRL || - shader == PIPE_SHADER_TESS_EVAL); + if (shader == PIPE_SHADER_GEOMETRY) + return 0; + + if (shader == PIPE_SHADER_VERTEX && + !sscreen->llvm_has_working_vgpr_indexing) + return 0; + + /* TCS and TES load inputs directly from LDS or offchip + * memory, so indirect indexing is always supported. + * PS has to support indirect indexing, because we can't + * lower that to TEMPs for INTERP instructions. + */ + return 1; case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: return sscreen->llvm_has_working_vgpr_indexing || |