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authorFrancisco Jerez <[email protected]>2016-04-25 17:25:26 -0700
committerFrancisco Jerez <[email protected]>2016-05-27 23:19:20 -0700
commit52cc80d85945f14d4556eb5df5b269338adf8299 (patch)
tree82bcb0dc8818c994b5e59618c17830a4606bd8c7 /src
parentc5f224145a41079ddcc77c0d7df8b4b75ed2d4fe (diff)
i965/fs: Fix CSE temporary copy for some LOAD_PAYLOAD corner cases.
If the LOAD_PAYLOAD instruction only has header sources it's possible for the number of registers written to be less than or equal to the SIMD component size, in which case it would take the single-MOV path at the bottom which would cause the channel enable masks to be applied incorrectly to the header contents and/or cause it to write past the end of the allocated temporary. If the instruction is either LOAD_PAYLOAD or doesn't write exactly one component the MOV path is going to mess up the program so just don't use it. Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_cse.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index b9752453faa..b17a082780a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -191,7 +191,8 @@ create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate)
DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE);
fs_inst *copy;
- if (written > dst_width) {
+ if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD ||
+ written != dst_width) {
fs_reg *payload;
int sources, header_size;
if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {