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authorMarek Olšák <[email protected]>2015-02-22 18:46:53 +0100
committerMarek Olšák <[email protected]>2015-07-23 00:59:33 +0200
commitbac12c8948681a23fd1a8f8a6bbb5523ccfe0939 (patch)
tree896a210d253f5ce595865a39e97184fd3495323c /src
parenta193c4978b0b536266afc7887457ab11473671d7 (diff)
radeonsi: enable tessellation, update GL3.txt & release notes
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index b545a4f4a5f..c2985b8d224 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -293,9 +293,11 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_VERTEXID_NOBASE:
- case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
return 0;
+ case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
+ return 30;
+
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
@@ -375,6 +377,13 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
break;
+ case PIPE_SHADER_TESS_CTRL:
+ case PIPE_SHADER_TESS_EVAL:
+ /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
+ if (HAVE_LLVM < 0x0306 ||
+ (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
+ return 0;
+ break;
case PIPE_SHADER_COMPUTE:
switch (param) {
case PIPE_SHADER_CAP_PREFERRED_IR:
@@ -401,7 +410,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
}
break;
default:
- /* TODO: support tessellation */
return 0;
}
@@ -433,7 +441,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
/* Indirection of geometry shader input dimension is not
* handled yet
*/
- return shader < PIPE_SHADER_GEOMETRY;
+ return shader != PIPE_SHADER_GEOMETRY;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: