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authorAlex Deucher <[email protected]>2010-11-17 11:30:52 -0500
committerAlex Deucher <[email protected]>2010-11-17 11:30:52 -0500
commit75e52556a8e72f2841ef03de91255f260160ebd2 (patch)
treed9cd37af19a9e89fa2cdd022295536b447d9afd3 /src
parent1d39df42c429a99b3c3b77b6da3517d8567eafb7 (diff)
r600c/evergreen: texture align is group_bytes just like 6xx/7xx
Default group bytes to 512 on evergreen. Don't query tiling config yet for evergreen, the current info returned is not adequate for evergreen (no way to get bank info).
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common_context.c13
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.c16
2 files changed, 15 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index edae7e4b83b..fecdd119059 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -246,16 +246,9 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
if (IS_R600_CLASS(radeon->radeonScreen)) {
- int chip_family = radeon->radeonScreen->chip_family;
- if (chip_family >= CHIP_FAMILY_CEDAR) {
- radeon->texture_row_align = 512;
- radeon->texture_rect_row_align = 512;
- radeon->texture_compressed_row_align = 512;
- } else {
- radeon->texture_row_align = radeon->radeonScreen->group_bytes;
- radeon->texture_rect_row_align = radeon->radeonScreen->group_bytes;
- radeon->texture_compressed_row_align = radeon->radeonScreen->group_bytes;
- }
+ radeon->texture_row_align = radeon->radeonScreen->group_bytes;
+ radeon->texture_rect_row_align = radeon->radeonScreen->group_bytes;
+ radeon->texture_compressed_row_align = radeon->radeonScreen->group_bytes;
} else if (IS_R200_CLASS(radeon->radeonScreen) ||
IS_R100_CLASS(radeon->radeonScreen)) {
radeon->texture_row_align = 32;
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 1ea52f96d7e..b379240579d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1323,7 +1323,11 @@ radeonCreateScreen( __DRIscreen *sPriv )
screen->chip_flags |= RADEON_CLASS_R600;
/* set group bytes for r6xx+ */
- screen->group_bytes = 256;
+ if (screen->chip_family >= CHIP_FAMILY_CEDAR)
+ screen->group_bytes = 512;
+ else
+ screen->group_bytes = 256;
+
screen->cpp = dri_priv->bpp / 8;
screen->AGPMode = dri_priv->AGPMode;
@@ -1568,9 +1572,13 @@ radeonCreateScreen2(__DRIscreen *sPriv)
else
screen->chip_flags |= RADEON_CLASS_R600;
- /* r6xx+ tiling, default to 256 group bytes */
- screen->group_bytes = 256;
- if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6)) {
+ /* r6xx+ tiling, default group bytes */
+ if (screen->chip_family >= CHIP_FAMILY_CEDAR)
+ screen->group_bytes = 512;
+ else
+ screen->group_bytes = 256;
+ if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6) &&
+ (screen->chip_family < CHIP_FAMILY_CEDAR)) {
ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
if (ret)
fprintf(stderr, "failed to get tiling info\n");