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authorFrancisco Jerez <[email protected]>2019-09-27 14:50:00 -0700
committerFrancisco Jerez <[email protected]>2019-10-11 12:24:16 -0700
commit6965a02e09de2d31e5fa951ffa2ae401b2197fb1 (patch)
tree6e0a9b8d975f70cce46d2a47cb229e07ee3e0966 /src
parenteeaad2992cc45c22f5e188d0a814db795112964d (diff)
intel/ir: Represent physical edge of unconditional CONTINUE instruction.
This edge doesn't exist in the original scalar program, but it represents a potential control flow path the EU will take in cases where control flow isn't uniform across channels of the same SIMD thread. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/intel/compiler/brw_cfg.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_cfg.cpp b/src/intel/compiler/brw_cfg.cpp
index d5e0a08c74c..87a423d998f 100644
--- a/src/intel/compiler/brw_cfg.cpp
+++ b/src/intel/compiler/brw_cfg.cpp
@@ -334,6 +334,8 @@ cfg_t::cfg_t(exec_list *instructions)
next = new_block();
if (inst->predicate)
cur->add_successor(mem_ctx, next, bblock_link_logical);
+ else
+ cur->add_successor(mem_ctx, next, bblock_link_physical);
set_next_block(&cur, next, ip);
break;