r600g: align flushing of cb/db with DDX/r600c.

the DDX and r600c both flush cb/db after the draw is emitted,
as long as they do that, r600g can't be different, as it races.

We end up with r600g flush, set CB, DDX set CB, flush. This
was causing misrendering on my evergreen, where sometimes the drawing
would go to an old CB.

5 files changed, 95 insertions, 32 deletions

diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index eb370698bbd..76a05f81fc5 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -119,6 +119,9 @@ struct r600_context_hw_states {
 	struct radeon_state	scissor;
 	struct radeon_state	dsa;
 	struct radeon_state	cb_cntl;
+
+	struct radeon_state	db_flush;
+	struct radeon_state	cb_flush;
 };
 
 #define R600_MAX_CONSTANT 256 /* magic */
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 93b0cf1a534..28c686a494c 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -595,6 +595,54 @@ static void r600_bind_shader_sampler(struct r600_context *rctx, struct r600_shad
 	}
 }
 
+
+static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	struct pipe_surface *surf;
+	int i;
+
+	radeon_state_init(flush, rscreen->rw, R600_STATE_CB_FLUSH, 0, 0);
+
+	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
+		surf = rctx->framebuffer->state.framebuffer.cbufs[i];
+		
+		rtex = (struct r600_resource_texture*)surf->texture;
+		rbuffer = &rtex->resource;
+		/* just need to the bo to the flush list */
+		flush->bo[i] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		flush->placement[i] = RADEON_GEM_DOMAIN_VRAM;
+	}
+	flush->nbo = rctx->framebuffer->state.framebuffer.nr_cbufs;
+	return radeon_state_pm4(flush);
+}
+
+static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	struct pipe_surface *surf;
+	int i;
+
+	surf = rctx->framebuffer->state.framebuffer.zsbuf;
+
+	if (!surf)
+		return 0;
+		
+	radeon_state_init(flush, rscreen->rw, R600_STATE_DB_FLUSH, 0, 0);
+	rtex = (struct r600_resource_texture*)surf->texture;
+	rbuffer = &rtex->resource;
+	/* just need to the bo to the flush list */
+	flush->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	flush->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+
+	flush->nbo = 1;
+	return radeon_state_pm4(flush);
+}
+
 int r600_context_hw_states(struct pipe_context *ctx)
 {
 	struct r600_context *rctx = r600_context(ctx);
@@ -605,6 +653,10 @@ int r600_context_hw_states(struct pipe_context *ctx)
 	rctx->vtbl->scissor(rctx, &rctx->hw_states.scissor);
 	rctx->vtbl->dsa(rctx, &rctx->hw_states.dsa);
 	rctx->vtbl->cb_cntl(rctx, &rctx->hw_states.cb_cntl);
+							       
+	/* setup flushes */
+	setup_db_flush(rctx, &rctx->hw_states.db_flush);
+	setup_cb_flush(rctx, &rctx->hw_states.cb_flush);
 
 	/* bind states */
 	radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
@@ -614,6 +666,9 @@ int r600_context_hw_states(struct pipe_context *ctx)
 
 	radeon_draw_bind(&rctx->draw, &rctx->config);
 
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
+
 	if (rctx->viewport) {
 		radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
 	}
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 0a8cb73e7dc..5759f363ead 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -212,6 +212,8 @@ enum r600_stype {
 	R600_STATE_UCP,
 	R600_STATE_VGT,
 	R600_STATE_DRAW,
+	R600_STATE_CB_FLUSH,
+	R600_STATE_DB_FLUSH,
 };
 
 #include "r600_states_inc.h"
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index 23eed81e04d..3160beace7e 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -43,8 +43,8 @@ static int r600_state_pm4_generic(struct radeon_state *state);
 static int r600_state_pm4_query_begin(struct radeon_state *state);
 static int r600_state_pm4_query_end(struct radeon_state *state);
 static int r700_state_pm4_config(struct radeon_state *state);
-static int r700_state_pm4_cb0(struct radeon_state *state);
-static int r700_state_pm4_db(struct radeon_state *state);
+static int r600_state_pm4_db_flush(struct radeon_state *state);
+static int r600_state_pm4_cb_flush(struct radeon_state *state);
 
 #include "r600_states.h"
 
@@ -84,6 +84,8 @@ struct radeon_stype_info r600_stypes[] = {
 	{ R600_STATE_UCP, 1, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
 	{ R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) },
 	{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) },
+	{ R600_STATE_CB_FLUSH, 1, 0, r600_state_pm4_cb_flush, SUB_NONE(CB_FLUSH) },
+	{ R600_STATE_DB_FLUSH, 1, 0, r600_state_pm4_db_flush, SUB_NONE(DB_FLUSH) },
 };
 #define STYPES_SIZE Elements(r600_stypes)
 
@@ -224,8 +226,6 @@ static int r600_state_pm4_cb0(struct radeon_state *state)
 {
 	int r;
 
-	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
-				S_0085F0_CB0_DEST_BASE_ENA(1));
 	r = r600_state_pm4_generic(state);
 	if (r)
 		return r;
@@ -234,24 +234,10 @@ static int r600_state_pm4_cb0(struct radeon_state *state)
 	return 0;
 }
 
-static int r700_state_pm4_cb0(struct radeon_state *state)
-{
-	int r;
-
-	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
-				S_0085F0_CB0_DEST_BASE_ENA(1));
-	r = r600_state_pm4_generic(state);
-	if (r)
-		return r;
-	return 0;
-}
-
 static int r600_state_pm4_db(struct radeon_state *state)
 {
 	int r;
 
-	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
-				S_0085F0_DB_DEST_BASE_ENA(1));
 	r = r600_state_pm4_generic(state);
 	if (r)
 		return r;
@@ -260,18 +246,6 @@ static int r600_state_pm4_db(struct radeon_state *state)
 	return 0;
 }
 
-static int r700_state_pm4_db(struct radeon_state *state)
-{
-	int r;
-
-	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
-				S_0085F0_DB_DEST_BASE_ENA(1));
-	r = r600_state_pm4_generic(state);
-	if (r)
-		return r;
-	return 0;
-}
-
 static int r600_state_pm4_config(struct radeon_state *state)
 {
 	state->pm4[state->cpm4++] = PKT3(PKT3_START_3D_CMDBUF, 0);
@@ -391,6 +365,28 @@ static int r600_state_pm4_draw(struct radeon_state *state)
 	return 0;
 }
 
+static int r600_state_pm4_cb_flush(struct radeon_state *state)
+{
+	if (!state->nbo)
+		return 0;
+
+	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
+				  S_0085F0_CB0_DEST_BASE_ENA(1));
+
+	return 0;
+}
+
+static int r600_state_pm4_db_flush(struct radeon_state *state)
+{
+	if (!state->nbo)
+		return 0;
+
+	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
+				S_0085F0_DB_DEST_BASE_ENA(1));
+
+	return 0;
+}
+
 static int r600_state_pm4_resource(struct radeon_state *state)
 {
 	u32 flags, type, nbo, offset, soffset;
@@ -464,10 +460,11 @@ static void r600_modify_type_array(struct radeon *radeon)
 			info->pm4 = r700_state_pm4_config;
 			break;
 		case R600_STATE_CB0:
-			info->pm4 = r700_state_pm4_cb0;
+			info->pm4 = r600_state_pm4_generic;
 			break;
 		case R600_STATE_DB:
-			info->pm4 = r700_state_pm4_db;
+			info->pm4 = r600_state_pm4_generic;
+			break;
 		};
 	}
 }
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index a0175fb603f..77937380736 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -513,4 +513,10 @@ static const struct radeon_register R600_names_VGT_EVENT[] = {
 	{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
 };
 
+static const struct radeon_register R600_names_CB_FLUSH[] = {
+};
+
+static const struct radeon_register R600_names_DB_FLUSH[] = {
+};
+
 #endif