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authorKenneth Graunke <[email protected]>2012-01-07 21:57:46 -0800
committerKenneth Graunke <[email protected]>2012-01-08 14:38:03 -0800
commit37240d2132d25588ad05ae5394c237f45d8ad881 (patch)
tree3480f5c3f82565f66d684e3ed7a1c93c57048512 /src
parented22f8ed2c12d2cbeae245ea51e44cb308994ec2 (diff)
i965: Actually enable SIMD16 dispatch on Ivybridge.
Commit acf82657f4d607e4477f03752613d42f239e4bd3 supposedly enabled SIMD16 dispatch, but neglected to set the "16 Pixel Dispatch Enable" bit, so nothing actually got enabled. Furthermore, it neglected to set up the Dispatch GRF Start Register for kernel 2, which is the SIMD16 program. Increases performance in Nexuiz by ~15% at 800x600 (n=3). NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_state.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index a99483668f6..f63cf54cdb4 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -163,14 +163,19 @@ upload_ps_state(struct brw_context *brw)
if (brw->fragment_program->Base.InputsRead != 0)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
- if (brw->wm.prog_data->dispatch_width == 8)
+ if (brw->wm.prog_data->dispatch_width == 8) {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
- else
+ if (brw->wm.prog_data->prog_offset_16)
+ dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
+ } else {
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
+ }
/* BRW_NEW_CURBE_OFFSETS */
dw5 |= (brw->wm.prog_data->first_curbe_grf <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+ dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+ GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));