diff options
| author | D Scott Phillips <[email protected]> | 2020-04-30 23:12:07 +0000 |
|---|---|---|
| committer | Eric Engestrom <[email protected]> | 2020-05-05 18:56:45 +0200 |
| commit | 263451f9c9174f8d3d0a2ba9743066d36906a509 (patch) | |
| tree | 9923b45dea2438c64978b79159df4dfadccd5534 /src | |
| parent | 3668e27ec3d0e57699f92da72c4ef324bb0c7f85 (diff) | |
anv,iris: Fix input vertex max for tcs on gen12
gen12 does away with the single patch dispatch mode for tcs, and
increases some limits so that 8_patch mode can always work. Make the
necessary changes so we don't try to fall back to single patch mode.
Fixes KHR-GL46.tessellation_shader.single.max_patch_vertices and others
Fixes: 44754279ace7 ("intel/fs/gen12: Use TCS 8_PATCH mode.")
Reviewed-by: Kenneth Graunke <[email protected]>
Acked-by: Jason Ekstrand <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4843>
(cherry picked from commit 65b05ebdda18c1cebd88c72cc8f50530addb80c6)
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4_tcs.cpp | 2 | ||||
| -rw-r--r-- | src/intel/genxml/gen12.xml | 2 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_pipeline.c | 7 |
4 files changed, 10 insertions, 3 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 0d434124aaf..a5b825f1baf 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -4178,6 +4178,8 @@ iris_store_tcs_state(struct iris_context *ice, * more than 2 times the number of instance count. */ assert((devinfo->max_tcs_threads / 2) > tcs_prog_data->instances); + hs.DispatchGRFStartRegisterForURBData = prog_data->dispatch_grf_start_reg & 0x1f; + hs.DispatchGRFStartRegisterForURBData5 = prog_data->dispatch_grf_start_reg >> 5; #endif hs.InstanceCount = tcs_prog_data->instances - 1; diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 852c5a9865c..e9a6880cfbe 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -394,7 +394,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, if (compiler->use_tcs_8_patch && nir->info.tess.tcs_vertices_out <= (devinfo->gen >= 12 ? 32 : 16) && - 2 + has_primitive_id + key->input_vertices <= 31) { + 2 + has_primitive_id + key->input_vertices <= (devinfo->gen >= 12 ? 63 : 31)) { /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the * "Instance" field limits the number of output vertices to [1, 16] on * gen11 and below, or [1, 32] on gen12 and above. Secondly, the diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 9be40f66003..3eebc30f4be 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -1964,7 +1964,7 @@ <value name="9-12 Samplers" value="3"/> <value name="13-16 Samplers" value="4"/> </field> - <field name="Instance Count" start="64" end="67" type="uint"/> + <field name="Instance Count" start="64" end="68" type="uint"/> <field name="Maximum Number of Threads" start="72" end="80" type="uint"/> <field name="Statistics Enable" start="93" end="93" type="bool"/> <field name="Enable" start="95" end="95" type="bool"/> diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index c6f479168b6..5277d22489e 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1624,7 +1624,12 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline, hs.VertexURBEntryReadLength = 0; hs.VertexURBEntryReadOffset = 0; hs.DispatchGRFStartRegisterForURBData = - tcs_prog_data->base.base.dispatch_grf_start_reg; + tcs_prog_data->base.base.dispatch_grf_start_reg & 0x1f; +#if GEN_GEN >= 12 + hs.DispatchGRFStartRegisterForURBData5 = + tcs_prog_data->base.base.dispatch_grf_start_reg >> 5; +#endif + hs.PerThreadScratchSpace = get_scratch_space(tcs_bin); hs.ScratchSpaceBasePointer = |