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authorDave Airlie <[email protected]>2017-01-20 10:21:19 +1000
committerDave Airlie <[email protected]>2017-01-31 09:30:15 +1000
commit8f41fe4389a820d243651a31c7e44ba57735b3ff (patch)
treef34537af05ef133d71c461ab3449e0b05ec156e2 /src
parent99936d360610ee06fec5c29e73dd295402e2c357 (diff)
radv: add gs ring size calculations to pipeline.
Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/amd/vulkan/radv_pipeline.c32
-rw-r--r--src/amd/vulkan/radv_private.h2
2 files changed, 34 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4b5c5435dfd..279a0767efd 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1450,6 +1450,37 @@ radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es)
return key;
}
+static void
+calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
+{
+ struct radv_device *device = pipeline->device;
+ unsigned num_se = device->physical_device->rad_info.max_se;
+ unsigned wave_size = 64;
+ unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
+ unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
+ unsigned alignment = 256 * num_se;
+ /* The maximum size is 63.999 MB per SE. */
+ unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
+
+ struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
+ struct ac_shader_variant_info *es_info = &pipeline->shaders[MESA_SHADER_VERTEX]->info;
+ /* Calculate the minimum size. */
+ unsigned min_esgs_ring_size = align(es_info->vs.esgs_itemsize * gs_vertex_reuse *
+ wave_size, alignment);
+ /* These are recommended sizes, not minimum sizes. */
+ unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
+ es_info->vs.esgs_itemsize * gs_info->gs.vertices_in;
+ unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
+ gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
+
+ min_esgs_ring_size = align(min_esgs_ring_size, alignment);
+ esgs_ring_size = align(esgs_ring_size, alignment);
+ gsvs_ring_size = align(gsvs_ring_size, alignment);
+
+ pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
+ pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
+}
+
VkResult
radv_pipeline_init(struct radv_pipeline *pipeline,
struct radv_device *device,
@@ -1504,6 +1535,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
pipeline->layout, &key);
pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
+ calculate_gs_ring_sizes(pipeline);
}
if (!modules[MESA_SHADER_FRAGMENT]) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 2579f43dd61..3a0318b9fc2 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -939,6 +939,8 @@ struct radv_pipeline {
unsigned prim;
unsigned gs_out;
bool prim_restart_enable;
+ unsigned esgs_ring_size;
+ unsigned gsvs_ring_size;
} graphics;
};