summaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
authorTopi Pohjolainen <[email protected]>2016-12-28 17:49:56 +0200
committerTopi Pohjolainen <[email protected]>2017-01-27 08:57:26 +0200
commit19412abb3f1b865a3e3810e725052a5a478aaf76 (patch)
treedd5eee404ba316b0cb058229883f523bc17b8317 /src
parent26a9e039fdc63c04d5b3383d91c5eea1494c0f8f (diff)
i965: Remove check for hiz on earlier gens than SNB
Only caller, brw_workaround_depthstencil_alignment(), returns early for gen6+. While at it, reduce scope for brw_get_depthstencil_tile_masks() as well. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h6
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c18
2 files changed, 2 insertions, 22 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index aa1499a1fe1..01e651b09f0 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1246,12 +1246,6 @@ brw_meta_resolve_color(struct brw_context *brw,
/*======================================================================
* brw_misc_state.c
*/
-void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
- uint32_t depth_level,
- uint32_t depth_layer,
- struct intel_mipmap_tree *stencil_mt,
- uint32_t *out_tile_mask_x,
- uint32_t *out_tile_mask_y);
void brw_workaround_depthstencil_alignment(struct brw_context *brw,
GLbitfield clear_mask);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 40a8d07bfb4..616c0dff862 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -165,7 +165,7 @@ brw_depthbuffer_format(struct brw_context *brw)
* packet. If the 3 buffers don't agree on the drawing offset ANDed with this
* mask, then we're in trouble.
*/
-void
+static void
brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
uint32_t depth_level,
uint32_t depth_layer,
@@ -179,21 +179,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
intel_get_tile_masks(depth_mt->tiling, depth_mt->tr_mode,
depth_mt->cpp,
&tile_mask_x, &tile_mask_y);
-
- if (intel_miptree_level_has_hiz(depth_mt, depth_level)) {
- uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
- intel_get_tile_masks(depth_mt->hiz_buf->mt->tiling,
- depth_mt->hiz_buf->mt->tr_mode,
- depth_mt->hiz_buf->mt->cpp,
- &hiz_tile_mask_x,
- &hiz_tile_mask_y);
-
- /* Each HiZ row represents 2 rows of pixels */
- hiz_tile_mask_y = hiz_tile_mask_y << 1 | 1;
-
- tile_mask_x |= hiz_tile_mask_x;
- tile_mask_y |= hiz_tile_mask_y;
- }
+ assert(!intel_miptree_level_has_hiz(depth_mt, depth_level));
}
if (stencil_mt) {