diff options
| author | Nicolai Hähnle <[email protected]> | 2017-03-30 17:07:34 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <[email protected]> | 2017-03-31 18:15:50 +0200 |
| commit | d10fbe5159ce1f7e05e959bb44e50f40a2402fb5 (patch) | |
| tree | cee3b29d02141b0f3614269427bed83dd4144ad4 /src | |
| parent | c22841d8d20c7d981ba8bbfd10300952586a6b69 (diff) | |
st/glsl_to_tgsi: fix 64-bit integer bit shifts
Fix a bug that was caused by a type mismatch in the shift count between
GLSL and TGSI. I briefly considered adjusting the TGSI semantics, but
since both LLVM and AMD GCN require both arguments to be of the same type,
it makes more sense to keep TGSI as-is -- it reflects the underlying
implementation better.
I'm also sending out piglit tests that expose this error.
v2: use the right number of components for the temporary register
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 369dff77075..7da08daa3c5 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -2102,13 +2102,23 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op) break; } case ir_binop_lshift: - if (native_integers) { - emit_asm(ir, TGSI_OPCODE_SHL, result_dst, op[0], op[1]); - break; - } case ir_binop_rshift: if (native_integers) { - emit_asm(ir, TGSI_OPCODE_ISHR, result_dst, op[0], op[1]); + unsigned opcode = ir->operation == ir_binop_lshift ? TGSI_OPCODE_SHL + : TGSI_OPCODE_ISHR; + st_src_reg count; + + if (glsl_base_type_is_64bit(op[0].type)) { + /* GLSL shift operations have 32-bit shift counts, but TGSI uses + * 64 bits. + */ + count = get_temp(glsl_type::u64vec(ir->operands[1]->type->components())); + emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]); + } else { + count = op[1]; + } + + emit_asm(ir, opcode, result_dst, op[0], count); break; } case ir_binop_bit_and: |