amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.

6 files changed, 56 insertions, 92 deletions

diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 7272c49affe..cf08566f869 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -896,7 +896,7 @@ VOID CiLib::HwlOptimizeTileMode(
     {
         UINT_32 thickness = Thickness(tileMode);
 
-        if (pInOut->maxBaseAlign < Block64K)
+        if ((pInOut->maxBaseAlign != 0) && (pInOut->maxBaseAlign < Block64K))
         {
             tileMode = (thickness == 1) ? ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK;
         }
@@ -1213,7 +1213,7 @@ VOID CiLib::HwlSetupTileInfo(
     INT macroModeIndex = TileIndexInvalid;
 
     // Fail-safe code
-    if (!IsLinear(tileMode))
+    if (IsLinear(tileMode) == FALSE)
     {
         // Thick tile modes must use thick micro tile mode but Bonaire does not support due to
         // old derived netlists (UBTS 404321)
@@ -1825,9 +1825,6 @@ INT_32 CiLib::HwlComputeMacroModeIndex(
 
         if (flags.prt || IsPrtTileMode(tileMode))
         {
-            // Unknown - assume it is 1/2 of table size
-            const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
-
             macroModeIndex += PrtMacroModeOffset;
             *pTileInfo = m_macroTileTable[macroModeIndex];
         }
@@ -2027,25 +2024,27 @@ UINT_64 CiLib::HwlComputeMetadataNibbleAddress(
 ****************************************************************************************************
 */
 VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled(
-    AddrTileMode        tileMode,           ///< [in] tile mode
-    UINT_32             bpp,                ///< [in] bits per pixel
-    ADDR_SURFACE_FLAGS  flags,              ///< [in] surface flags
-    UINT_32             mipLevel,           ///< [in] mip level
-    UINT_32             numSamples,         ///< [in] number of samples
-    ADDR_TILEINFO*      pTileInfo,          ///< [in,out] bank structure.
-    UINT_32*            pBaseAlign,         ///< [out] base address alignment in bytes
-    UINT_32*            pPitchAlign,        ///< [out] pitch alignment in pixels
-    UINT_32*            pHeightAlign,       ///< [out] height alignment in pixels
-    UINT_32*            pMacroTileWidth,    ///< [out] macro tile width in pixels
-    UINT_32*            pMacroTileHeight    ///< [out] macro tile height in pixels
+    AddrTileMode                      tileMode,           ///< [in] tile mode
+    UINT_32                           bpp,                ///< [in] bits per pixel
+    ADDR_SURFACE_FLAGS                flags,              ///< [in] surface flags
+    UINT_32                           mipLevel,           ///< [in] mip level
+    UINT_32                           numSamples,         ///< [in] number of samples
+    ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut                ///< [in,out] Surface output
     ) const
 {
+    // This is to workaround a H/W limitation that DCC doesn't work when pipe config is switched to
+    // P4. In theory, all asics that have such switching should be patched but we now only know what
+    // to pad for Fiji.
     if ((m_settings.isFiji == TRUE) &&
         (flags.dccCompatible == TRUE) &&
+        (flags.prt == FALSE) &&
         (mipLevel == 0) &&
-        (tileMode == ADDR_TM_PRT_TILED_THIN1))
+        (tileMode == ADDR_TM_PRT_TILED_THIN1) &&
+        (pOut->dccUnsupport == TRUE))
     {
-        *pPitchAlign = PowTwoAlign(*pPitchAlign, 256);
+        pOut->pitchAlign   = PowTwoAlign(pOut->pitchAlign, 256);
+        // In case the client still requests DCC usage.
+        pOut->dccUnsupport = FALSE;
     }
 }
 
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 7fa6b75e864..93b2853d066 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -177,9 +177,7 @@ protected:
 
     virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
         AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
-        UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
-        UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
-        UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
+        UINT_32 mipLevel, UINT_32 numSamples, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
 
 private:
     VOID ReadGbTileMode(
@@ -207,6 +205,8 @@ private:
         UINT_32 numOfSamplesPerSplit) const;
 
     static const UINT_32    MacroTileTableSize = 16;
+    static const UINT_32    PrtMacroModeOffset = MacroTileTableSize / 2;
+
     ADDR_TILEINFO           m_macroTileTable[MacroTileTableSize];
     UINT_32                 m_noOfMacroEntries;
     BOOL_32                 m_allowNonDispThickModes;
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 2d1123a3ccd..7942d20d75a 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -463,12 +463,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMacroTiled(
                                                pIn->flags,
                                                pIn->mipLevel,
                                                numSamples,
-                                               pOut->pTileInfo,
-                                               &pOut->baseAlign,
-                                               &pOut->pitchAlign,
-                                               &pOut->heightAlign,
-                                               &pOut->blockWidth,
-                                               &pOut->blockHeight);
+                                               pOut);
 
     if (valid)
     {
@@ -521,12 +516,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMacroTiled(
                                                        pIn->flags,
                                                        pIn->mipLevel,
                                                        numSamples,
-                                                       pOut->pTileInfo,
-                                                       &pOut->baseAlign,
-                                                       &pOut->pitchAlign,
-                                                       &pOut->heightAlign,
-                                                       &pOut->blockWidth,
-                                                       &pOut->blockHeight);
+                                                       pOut);
         }
 
         //
@@ -854,19 +844,16 @@ BOOL_32 EgBasedLib::HwlReduceBankWidthHeight(
 ****************************************************************************************************
 */
 BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
-    AddrTileMode        tileMode,           ///< [in] tile mode
-    UINT_32             bpp,                ///< [in] bits per pixel
-    ADDR_SURFACE_FLAGS  flags,              ///< [in] surface flags
-    UINT_32             mipLevel,           ///< [in] mip level
-    UINT_32             numSamples,         ///< [in] number of samples
-    ADDR_TILEINFO*      pTileInfo,          ///< [in,out] bank structure.
-    UINT_32*            pBaseAlign,         ///< [out] base address alignment in bytes
-    UINT_32*            pPitchAlign,        ///< [out] pitch alignment in pixels
-    UINT_32*            pHeightAlign,       ///< [out] height alignment in pixels
-    UINT_32*            pMacroTileWidth,    ///< [out] macro tile width in pixels
-    UINT_32*            pMacroTileHeight    ///< [out] macro tile height in pixels
+    AddrTileMode                      tileMode,           ///< [in] tile mode
+    UINT_32                           bpp,                ///< [in] bits per pixel
+    ADDR_SURFACE_FLAGS                flags,              ///< [in] surface flags
+    UINT_32                           mipLevel,           ///< [in] mip level
+    UINT_32                           numSamples,         ///< [in] number of samples
+    ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut                ///< [in,out] Surface output
     ) const
 {
+    ADDR_TILEINFO* pTileInfo = pOut->pTileInfo;
+
     BOOL_32 valid = SanityCheckMacroTiled(pTileInfo);
 
     if (valid)
@@ -924,10 +911,10 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
         macroTileWidth = MicroTileWidth * pTileInfo->bankWidth * pipes *
             pTileInfo->macroAspectRatio;
 
-        *pPitchAlign = macroTileWidth;
-        *pMacroTileWidth = macroTileWidth;
+        pOut->pitchAlign = macroTileWidth;
+        pOut->blockWidth = macroTileWidth;
 
-        AdjustPitchAlignment(flags, pPitchAlign);
+        AdjustPitchAlignment(flags, &pOut->pitchAlign);
 
         //
         // The required granularity for height is the macro tile height.
@@ -935,18 +922,16 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
         macroTileHeight = MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks /
             pTileInfo->macroAspectRatio;
 
-        *pHeightAlign = macroTileHeight;
-        *pMacroTileHeight = macroTileHeight;
+        pOut->heightAlign = macroTileHeight;
+        pOut->blockHeight = macroTileHeight;
 
         //
         // Compute base alignment
         //
-        *pBaseAlign = pipes *
-            pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize;
+        pOut->baseAlign =
+            pipes * pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize;
 
-        HwlComputeSurfaceAlignmentsMacroTiled(tileMode, bpp, flags, mipLevel, numSamples,
-                                              pTileInfo, pBaseAlign, pPitchAlign, pHeightAlign,
-                                              pMacroTileWidth, pMacroTileHeight);
+        HwlComputeSurfaceAlignmentsMacroTiled(tileMode, bpp, flags, mipLevel, numSamples, pOut);
     }
 
     return valid;
@@ -1169,16 +1154,12 @@ BOOL_32 EgBasedLib::HwlGetAlignmentInfoMacroTiled(
 
     ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
 
-    UINT_32 baseAlign;
-    UINT_32 pitchAlign;
-    UINT_32 heightAlign;
-    UINT_32 macroTileWidth;
-    UINT_32 macroTileHeight;
     UINT_32 numSamples = (pIn->numFrags == 0) ? pIn->numSamples : pIn->numFrags;
 
     ADDR_ASSERT(pIn->pTileInfo);
     ADDR_TILEINFO tileInfo = *pIn->pTileInfo;
     ADDR_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
+    out.pTileInfo = &tileInfo;
 
     if (UseTileIndex(pIn->tileIndex))
     {
@@ -1202,18 +1183,13 @@ BOOL_32 EgBasedLib::HwlGetAlignmentInfoMacroTiled(
                                                pIn->flags,
                                                pIn->mipLevel,
                                                numSamples,
-                                               &tileInfo,
-                                               &baseAlign,
-                                               &pitchAlign,
-                                               &heightAlign,
-                                               &macroTileWidth,
-                                               &macroTileHeight);
+                                               &out);
 
     if (valid)
     {
-        *pPitchAlign = pitchAlign;
-        *pHeightAlign = heightAlign;
-        *pSizeAlign = baseAlign;
+        *pPitchAlign  = out.pitchAlign;
+        *pHeightAlign = out.heightAlign;
+        *pSizeAlign   = out.baseAlign;
     }
 
     return valid;
diff --git a/src/amd/addrlib/r800/egbaddrlib.h b/src/amd/addrlib/r800/egbaddrlib.h
index 50fd3d927ad..dbe712a6714 100644
--- a/src/amd/addrlib/r800/egbaddrlib.h
+++ b/src/amd/addrlib/r800/egbaddrlib.h
@@ -303,9 +303,7 @@ protected:
 
     virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
         AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
-        UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
-        UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
-        UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const
+        UINT_32 mipLevel, UINT_32 numSamples, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
     {
     }
 
@@ -340,9 +338,7 @@ private:
     BOOL_32 ComputeSurfaceAlignmentsMacroTiled(
         AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
         UINT_32 mipLevel, UINT_32 numSamples,
-        ADDR_TILEINFO* pTileInfo,
-        UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
-        UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
+        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
 
     /// Surface addressing functions
     UINT_64 DispatchComputeSurfaceAddrFromCoord(
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index 299951edc01..c1f6dac15a1 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -3381,22 +3381,17 @@ ADDR_E_RETURNCODE SiLib::HwlGetMaxAlignments(
 ****************************************************************************************************
 */
 VOID SiLib::HwlComputeSurfaceAlignmentsMacroTiled(
-    AddrTileMode        tileMode,           ///< [in] tile mode
-    UINT_32             bpp,                ///< [in] bits per pixel
-    ADDR_SURFACE_FLAGS  flags,              ///< [in] surface flags
-    UINT_32             mipLevel,           ///< [in] mip level
-    UINT_32             numSamples,         ///< [in] number of samples
-    ADDR_TILEINFO*      pTileInfo,          ///< [in,out] bank structure.
-    UINT_32*            pBaseAlign,         ///< [out] base address alignment in bytes
-    UINT_32*            pPitchAlign,        ///< [out] pitch alignment in pixels
-    UINT_32*            pHeightAlign,       ///< [out] height alignment in pixels
-    UINT_32*            pMacroTileWidth,    ///< [out] macro tile width in pixels
-    UINT_32*            pMacroTileHeight    ///< [out] macro tile height in pixels
+    AddrTileMode                      tileMode,           ///< [in] tile mode
+    UINT_32                           bpp,                ///< [in] bits per pixel
+    ADDR_SURFACE_FLAGS                flags,              ///< [in] surface flags
+    UINT_32                           mipLevel,           ///< [in] mip level
+    UINT_32                           numSamples,         ///< [in] number of samples
+    ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut                ///< [in,out] Surface output
     ) const
 {
     if ((mipLevel == 0) && (flags.prt))
     {
-        UINT_32 macroTileSize = (*pMacroTileWidth) * (*pMacroTileHeight) * numSamples * bpp / 8;
+        UINT_32 macroTileSize = pOut->blockWidth * pOut->blockHeight * numSamples * bpp / 8;
 
         if (macroTileSize < PrtTileSize)
         {
@@ -3404,8 +3399,8 @@ VOID SiLib::HwlComputeSurfaceAlignmentsMacroTiled(
 
             ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
 
-            *pPitchAlign *= numMacroTiles;
-            *pBaseAlign  *= numMacroTiles;
+            pOut->pitchAlign *= numMacroTiles;
+            pOut->baseAlign  *= numMacroTiles;
         }
     }
 }
diff --git a/src/amd/addrlib/r800/siaddrlib.h b/src/amd/addrlib/r800/siaddrlib.h
index 53ec68ba06a..6daaa2388a7 100644
--- a/src/amd/addrlib/r800/siaddrlib.h
+++ b/src/amd/addrlib/r800/siaddrlib.h
@@ -249,9 +249,7 @@ protected:
 
     virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
         AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
-        UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
-        UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
-        UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
+        UINT_32 mipLevel, UINT_32 numSamples, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
 
     // Get equation table pointer and number of equations
     virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
@@ -286,7 +284,7 @@ protected:
     UINT_32 GetPipePerSurf(AddrPipeCfg pipeConfig) const;
 
     static const UINT_32    TileTableSize = 32;
-    TileConfig          m_tileTable[TileTableSize];
+    TileConfig              m_tileTable[TileTableSize];
     UINT_32                 m_noOfEntries;
 
     // Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp)