iris: Drop 'engine' from iris_batch.

For the moment, everything is I915_EXEC_RENDER, so this isn't necessary.
But even should that change, I don't think we want to handle multiple
engines in this manner.

Nowadays, we have batch->name (IRIS_BATCH_RENDER, IRIS_BATCH_COMPUTE,
possibly an IRIS_BATCH_BLIT for blorp batches someday), which describes
the functional usage of the batch.  We can simply check that and select
an engine for that class of work (assuming there ever is more than one).

Reviewed-by: Tapani Pälli <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>

3 files changed, 2 insertions, 13 deletions

diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c
index a44715a9458..2b5c62d4277 100644
--- a/src/gallium/drivers/iris/iris_batch.c
+++ b/src/gallium/drivers/iris/iris_batch.c
@@ -181,7 +181,6 @@ iris_init_batch(struct iris_batch *batch,
                 struct hash_table_u64 *state_sizes,
                 struct iris_batch *all_batches,
                 enum iris_batch_name name,
-                uint8_t engine,
                 int priority)
 {
    batch->screen = screen;
@@ -191,11 +190,6 @@ iris_init_batch(struct iris_batch *batch,
    batch->state_sizes = state_sizes;
    batch->name = name;
 
-   /* engine should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
-   assert((engine & ~I915_EXEC_RING_MASK) == 0);
-   assert(util_bitcount(engine) == 1);
-   batch->engine = engine;
-
    batch->hw_ctx_id = iris_create_hw_context(screen->bufmgr);
    assert(batch->hw_ctx_id);
 
@@ -587,7 +581,7 @@ submit_batch(struct iris_batch *batch)
       .batch_start_offset = 0,
       /* This must be QWord aligned. */
       .batch_len = ALIGN(batch->primary_batch_size, 8),
-      .flags = batch->engine |
+      .flags = I915_EXEC_RENDER |
                I915_EXEC_NO_RELOC |
                I915_EXEC_BATCH_FIRST |
                I915_EXEC_HANDLE_LUT,
diff --git a/src/gallium/drivers/iris/iris_batch.h b/src/gallium/drivers/iris/iris_batch.h
index aaa425f5736..3912541c6dd 100644
--- a/src/gallium/drivers/iris/iris_batch.h
+++ b/src/gallium/drivers/iris/iris_batch.h
@@ -75,9 +75,6 @@ struct iris_batch {
 
    uint32_t hw_ctx_id;
 
-   /** Which engine this batch targets - a I915_EXEC_RING_MASK value */
-   uint8_t engine;
-
    /** The validation list */
    struct drm_i915_gem_exec_object2 *validation_list;
    struct iris_bo **exec_bos;
@@ -138,7 +135,6 @@ void iris_init_batch(struct iris_batch *batch,
                      struct hash_table_u64 *state_sizes,
                      struct iris_batch *all_batches,
                      enum iris_batch_name name,
-                     uint8_t ring,
                      int priority);
 void iris_chain_to_new_batch(struct iris_batch *batch);
 void iris_batch_free(struct iris_batch *batch);
diff --git a/src/gallium/drivers/iris/iris_context.c b/src/gallium/drivers/iris/iris_context.c
index b95ef707bf5..e7b3a06a315 100644
--- a/src/gallium/drivers/iris/iris_context.c
+++ b/src/gallium/drivers/iris/iris_context.c
@@ -307,8 +307,7 @@ iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
       iris_init_batch(&ice->batches[i], screen, &ice->vtbl, &ice->dbg,
                       &ice->reset, ice->state.sizes,
-                      ice->batches, (enum iris_batch_name) i,
-                      I915_EXEC_RENDER, priority);
+                      ice->batches, (enum iris_batch_name) i, priority);
    }
 
    ice->vtbl.init_render_context(&ice->batches[IRIS_BATCH_RENDER]);