diff options
| author | Eric Anholt <[email protected]> | 2017-12-28 15:42:14 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2018-01-03 14:31:36 -0800 |
| commit | 7836c85919a289e806c4dbd3e7d080914049b130 (patch) | |
| tree | 7f4be4f926d6d56a2b8cf5a0bb909835eb070e7b /src | |
| parent | 635131a238eb1efa075a6b422ac9add863422cd7 (diff) | |
broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS.
Apparently the other funcs will have observable differences when early Z
is enabled.
Fixes (new) simulator assertion failures in
dEQP-GLES3.functional.rasterizer_discard.basic.clear_depth.
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/vc5/vc5_state.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/vc5/vc5_state.c b/src/gallium/drivers/vc5/vc5_state.c index 35d5e1df509..0d6699ae57b 100644 --- a/src/gallium/drivers/vc5/vc5_state.c +++ b/src/gallium/drivers/vc5/vc5_state.c @@ -165,8 +165,10 @@ vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx, cso->depth.func == PIPE_FUNC_LEQUAL) && (!cso->stencil[0].enabled || (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP && + cso->stencil[0].func == PIPE_FUNC_ALWAYS && (!cso->stencil[1].enabled || - cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP)))); + (cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP && + cso->stencil[1].func == PIPE_FUNC_ALWAYS))))); } const struct pipe_stencil_state *front = &cso->stencil[0]; |