diff options
| author | Matt Turner <[email protected]> | 2017-10-23 10:44:39 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2018-02-28 11:15:47 -0800 |
| commit | 3a584a15c0b1dd6c31a6520a0f749306f48d5782 (patch) | |
| tree | 2d61172b60df79b1dd8c16422b65608652436ee4 /src | |
| parent | 432674ce93ceee2abd7e0cc4171bc36a499d4c1f (diff) | |
intel/compiler/fs: Don't generate integer DWord multiply on Gen11
Like CHV et al., Gen11 does not support 32x32 -> 32/64-bit integer
multiplies.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/common/gen_device_info.c | 4 | ||||
| -rw-r--r-- | src/intel/common/gen_device_info.h | 1 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs.cpp | 6 |
3 files changed, 6 insertions, 5 deletions
diff --git a/src/intel/common/gen_device_info.c b/src/intel/common/gen_device_info.c index 7bed806b369..1773009d33c 100644 --- a/src/intel/common/gen_device_info.c +++ b/src/intel/common/gen_device_info.c @@ -382,6 +382,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = { .has_llc = true, \ .has_sample_with_hiz = false, \ .has_pln = true, \ + .has_integer_dword_mul = true, \ .has_64bit_types = true, \ .supports_simd16_3src = true, \ .has_surface_tile_offset = true, \ @@ -464,6 +465,7 @@ static const struct gen_device_info gen_device_info_bdw_gt3 = { static const struct gen_device_info gen_device_info_chv = { GEN8_FEATURES, .is_cherryview = 1, .gt = 1, .has_llc = false, + .has_integer_dword_mul = false, .num_slices = 1, .num_subslices = { 2, }, .num_thread_per_eu = 7, @@ -514,6 +516,7 @@ static const struct gen_device_info gen_device_info_chv = { #define GEN9_LP_FEATURES \ GEN8_FEATURES, \ GEN9_HW_INFO, \ + .has_integer_dword_mul = false, \ .gt = 1, \ .has_llc = false, \ .has_sample_with_hiz = true, \ @@ -818,6 +821,7 @@ static const struct gen_device_info gen_device_info_cnl_5x8 = { GEN8_FEATURES, \ GEN11_HW_INFO, \ .has_64bit_types = false, \ + .has_integer_dword_mul = false, \ .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \ .num_subslices = _subslices diff --git a/src/intel/common/gen_device_info.h b/src/intel/common/gen_device_info.h index 9b635ff178f..b8044d00032 100644 --- a/src/intel/common/gen_device_info.h +++ b/src/intel/common/gen_device_info.h @@ -60,6 +60,7 @@ struct gen_device_info bool has_pln; bool has_64bit_types; + bool has_integer_dword_mul; bool has_compr4; bool has_surface_tile_offset; bool supports_simd16_3src; diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index bed632d21b9..113f62c46c7 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -3549,11 +3549,7 @@ fs_visitor::lower_integer_multiplication() inst->dst.type != BRW_REGISTER_TYPE_UD)) continue; - /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit - * operation directly, but CHV/BXT cannot. - */ - if (devinfo->gen >= 8 && - !devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo)) + if (devinfo->has_integer_dword_mul) continue; if (inst->src[1].file == IMM && |