diff options
| author | Marek Olšák <[email protected]> | 2013-12-27 19:14:55 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2014-01-06 18:40:41 +0100 |
| commit | 2748b7da7e2a65bc46d12187b27585902a88f0aa (patch) | |
| tree | 5175ed3f1a600829fe77fb08e4d9fce0e89377cf /src | |
| parent | d41f5396f3cb619729021390c273f838d92f11fb (diff) | |
radeonsi: disable HTILE for 1D-tiled depth-stencil buffers
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index c7ef2777c20..caf3743e72f 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -466,6 +466,11 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen, unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; unsigned num_pipes = rscreen->tiling_info.num_channels; + /* HTILE doesn't work with 1D tiling (there's massive corruption + * in glxgears). */ + if (rtex->surface.level[0].mode != RADEON_SURF_MODE_2D) + return 0; + switch (num_pipes) { case 2: cl_width = 32; |