diff options
author | Kenneth Graunke <[email protected]> | 2011-02-09 01:05:40 -0800 |
---|---|---|
committer | Kenneth Graunke <[email protected]> | 2011-05-17 23:32:59 -0700 |
commit | 24d0ed72c1817b624e3021b12a0987b2c5edd71b (patch) | |
tree | 6d56d3deeb11402a2050dc56f4576628dfad0b34 /src | |
parent | a924d69b57a82c02f2d4fba3fc0b31bf6a4f744e (diff) |
i965: Initial Ivybridge CC state setup.
The state itself still seems to be the same; the only change is that
each part (CC, BLEND, DEPTH_STENCIL) can now be uploaded independently.
Thus, we still rely on the code in gen6_cc.c to set up the state.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
-rw-r--r-- | src/mesa/drivers/dri/i965/Makefile | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_state.h | 3 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen7_cc_state.c | 89 |
5 files changed, 98 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile index efe0871aa2e..dcecf3a741e 100644 --- a/src/mesa/drivers/dri/i965/Makefile +++ b/src/mesa/drivers/dri/i965/Makefile @@ -97,6 +97,7 @@ DRIVER_SOURCES = \ gen6_viewport_state.c \ gen6_vs_state.c \ gen6_wm_state.c \ + gen7_cc_state.c \ gen7_sf_state.c \ gen7_urb.c \ gen7_wm_state.c diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index c569995e112..5e6f88a7530 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -874,6 +874,8 @@ #define CMD_VF_STATISTICS_965 0x780b #define CMD_VF_STATISTICS_GM45 0x680b #define _3DSTATE_CC_STATE_POINTERS 0x780e /* GEN6+ */ +#define _3DSTATE_BLEND_STATE_POINTERS 0x7824 /* GEN7+ */ +#define _3DSTATE_DEPTH_STENCIL_STATE_POINTERS 0x7825 /* GEN7+ */ #define _3DSTATE_URB 0x7805 /* GEN6 */ # define GEN6_URB_VS_SIZE_SHIFT 16 diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 6125aea8373..e9af591c915 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -111,6 +111,9 @@ extern const struct brw_tracked_state gen6_vs_constants; extern const struct brw_tracked_state gen6_vs_state; extern const struct brw_tracked_state gen6_wm_constants; extern const struct brw_tracked_state gen6_wm_state; +extern const struct brw_tracked_state gen7_blend_state_pointer; +extern const struct brw_tracked_state gen7_cc_state_pointer; +extern const struct brw_tracked_state gen7_depth_stencil_state_pointer; extern const struct brw_tracked_state gen7_ps_state; extern const struct brw_tracked_state gen7_sbe_state; extern const struct brw_tracked_state gen7_sf_state; diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index accc8d47b54..79a173d4790 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -195,7 +195,9 @@ const struct brw_tracked_state *gen7_atoms[] = &gen6_blend_state, /* must do before cc unit */ &gen6_color_calc_state, /* must do before cc unit */ &gen6_depth_stencil_state, /* must do before cc unit */ - &gen6_cc_state_pointers, + &gen7_blend_state_pointer, + &gen7_cc_state_pointer, + &gen7_depth_stencil_state_pointer, &brw_vs_constants, /* Before vs_surfaces and constant_buffer */ &brw_wm_constants, /* Before wm_surfaces and constant_buffer */ diff --git a/src/mesa/drivers/dri/i965/gen7_cc_state.c b/src/mesa/drivers/dri/i965/gen7_cc_state.c new file mode 100644 index 00000000000..b7395aa791b --- /dev/null +++ b/src/mesa/drivers/dri/i965/gen7_cc_state.c @@ -0,0 +1,89 @@ +/* + * Copyright © 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "brw_context.h" +#include "brw_state.h" +#include "brw_defines.h" +#include "brw_util.h" +#include "intel_batchbuffer.h" +#include "main/macros.h" + +static void +upload_cc_state_pointers(struct brw_context *brw) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); + OUT_BATCH(brw->cc.state_offset | 1); + ADVANCE_BATCH(); +} + +const struct brw_tracked_state gen7_cc_state_pointer = { + .dirty = { + .mesa = 0, + .brw = BRW_NEW_BATCH, + .cache = CACHE_NEW_COLOR_CALC_STATE + }, + .emit = upload_cc_state_pointers, +}; + +static void +upload_blend_state_pointer(struct brw_context *brw) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2)); + OUT_BATCH(brw->cc.blend_state_offset | 1); + ADVANCE_BATCH(); +} + +const struct brw_tracked_state gen7_blend_state_pointer = { + .dirty = { + .mesa = 0, + .brw = BRW_NEW_BATCH, + .cache = CACHE_NEW_BLEND_STATE + }, + .emit = upload_blend_state_pointer, +}; + +static void +upload_depth_stencil_state_pointer(struct brw_context *brw) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2)); + OUT_BATCH(brw->cc.depth_stencil_state_offset | 1); + ADVANCE_BATCH(); +} + +const struct brw_tracked_state gen7_depth_stencil_state_pointer = { + .dirty = { + .mesa = 0, + .brw = BRW_NEW_BATCH, + .cache = CACHE_NEW_DEPTH_STENCIL_STATE + }, + .emit = upload_depth_stencil_state_pointer, +}; |